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ARM: OMAP3: PRM/CM: Cleanup unused header
Cleanup unused parts of the PRM and CM regbit headers leaving only whats used. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Rajendra Nayak
Paul Walmsley
parent
45ffdd324c
commit
7be914f2a3
@ -20,798 +20,49 @@
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#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
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/*
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* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
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* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
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*/
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#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
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#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
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#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
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#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
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#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
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/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_CPSW_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
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/* Used by CM_CEFUSE_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
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/* Used by CM_GFX_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
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/* Used by CM_GFX_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
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#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
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/* Used by CM_PER_L3S_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4FW_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
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/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
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/* Used by CM_CEFUSE_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
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/* Used by CM_RTC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
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/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
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/* Used by CM_PER_LCDC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
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/* Used by CM_PER_LCDC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
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/* Used by CM_MPU_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
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/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
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/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
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/* Used by CM_RTC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
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#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
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#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
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/* Used by CLKSEL_GFX_FCLK */
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
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/* Used by CM_CLKOUT_CTRL */
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#define AM33XX_CLKOUT2DIV_SHIFT 3
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#define AM33XX_CLKOUT2DIV_WIDTH 3
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#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
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/* Used by CM_CLKOUT_CTRL */
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#define AM33XX_CLKOUT2EN_SHIFT 7
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#define AM33XX_CLKOUT2EN_WIDTH 1
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#define AM33XX_CLKOUT2EN_MASK (1 << 7)
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/* Used by CM_CLKOUT_CTRL */
|
||||
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
|
||||
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
|
||||
* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
|
||||
* CLKSEL_TIMER7_CLK
|
||||
*/
|
||||
#define AM33XX_CLKSEL_SHIFT 0
|
||||
#define AM33XX_CLKSEL_WIDTH 1
|
||||
#define AM33XX_CLKSEL_MASK (0x01 << 0)
|
||||
|
||||
/*
|
||||
* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
|
||||
* CM_CPTS_RFT_CLKSEL
|
||||
*/
|
||||
#define AM33XX_CLKSEL_0_0_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_0_WIDTH 1
|
||||
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
|
||||
|
||||
#define AM33XX_CLKSEL_0_1_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_1_WIDTH 2
|
||||
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
|
||||
|
||||
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
|
||||
#define AM33XX_CLKSEL_0_2_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_2_WIDTH 3
|
||||
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
|
||||
* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
|
||||
* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
|
||||
* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
|
||||
* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
|
||||
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
|
||||
*/
|
||||
#define AM33XX_CLKTRCTRL_SHIFT 0
|
||||
#define AM33XX_CLKTRCTRL_WIDTH 2
|
||||
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
|
||||
* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
|
||||
* CM_SSC_DELTAMSTEP_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DELTAMSTEP_SHIFT 0
|
||||
#define AM33XX_DELTAMSTEP_WIDTH 20
|
||||
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
|
||||
|
||||
/*
|
||||
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
|
||||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
|
||||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_WIDTH 7
|
||||
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
|
||||
|
||||
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_EN_SHIFT 0
|
||||
#define AM33XX_DPLL_EN_WIDTH 3
|
||||
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
|
||||
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
|
||||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_MULT_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_WIDTH 11
|
||||
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
|
||||
|
||||
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
|
||||
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
|
||||
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
|
||||
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_SD_DIV_SHIFT 24
|
||||
#define AM33XX_DPLL_SD_DIV_WIDTH 8
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
|
||||
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_SSC_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
|
||||
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
|
||||
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
|
||||
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
|
||||
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
|
||||
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
|
||||
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
|
||||
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
|
||||
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
|
||||
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
|
||||
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
|
||||
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
|
||||
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
|
||||
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
|
||||
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
|
||||
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
|
||||
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
|
||||
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
|
||||
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
|
||||
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
|
||||
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
|
||||
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
|
||||
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
|
||||
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
|
||||
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
|
||||
* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
|
||||
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_IDLEST_SHIFT 16
|
||||
#define AM33XX_IDLEST_WIDTH 2
|
||||
#define AM33XX_IDLEST_MASK (0x3 << 16)
|
||||
|
||||
/* Used by CM_MAC_CLKSEL */
|
||||
#define AM33XX_MII_CLK_SEL_SHIFT 2
|
||||
#define AM33XX_MII_CLK_SEL_WIDTH 1
|
||||
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
|
||||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
|
||||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
|
||||
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
|
||||
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
|
||||
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
|
||||
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
|
||||
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
|
||||
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
|
||||
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
|
||||
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
|
||||
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
|
||||
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
|
||||
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
|
||||
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
|
||||
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
|
||||
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
|
||||
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
|
||||
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
|
||||
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
|
||||
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
|
||||
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
|
||||
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
|
||||
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
|
||||
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
|
||||
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
|
||||
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
|
||||
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
|
||||
* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
|
||||
* CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_MODULEMODE_SHIFT 0
|
||||
#define AM33XX_MODULEMODE_WIDTH 2
|
||||
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_WKUP_GPIO0_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO1_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO2_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO3_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO4_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO5_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO6_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
|
||||
* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
|
||||
* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
|
||||
* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
|
||||
* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
|
||||
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_STBYST_SHIFT 18
|
||||
#define AM33XX_STBYST_WIDTH 1
|
||||
#define AM33XX_STBYST_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
|
||||
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLK_SHIFT 0
|
||||
#define AM33XX_ST_DPLL_CLK_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
|
||||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
|
||||
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
|
||||
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_MN_BYPASS_SHIFT 8
|
||||
#define AM33XX_ST_MN_BYPASS_WIDTH 1
|
||||
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
|
||||
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
|
||||
|
||||
/* Used by CONTROL_SEC_CLK_CTRL */
|
||||
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
|
||||
#endif
|
||||
|
||||
@ -14,833 +14,201 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* Bits shared between registers */
|
||||
|
||||
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
|
||||
#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
|
||||
#define OMAP3430ES2_EN_MMC3_SHIFT 30
|
||||
#define OMAP3430_EN_MSPRO_MASK (1 << 23)
|
||||
#define OMAP3430_EN_MSPRO_SHIFT 23
|
||||
#define OMAP3430_EN_HDQ_MASK (1 << 22)
|
||||
#define OMAP3430_EN_HDQ_SHIFT 22
|
||||
#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
|
||||
#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
|
||||
#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
|
||||
#define OMAP3430ES1_EN_D2D_SHIFT 3
|
||||
#define OMAP3430_EN_SSI_MASK (1 << 0)
|
||||
#define OMAP3430_EN_SSI_SHIFT 0
|
||||
|
||||
/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
|
||||
#define OMAP3430ES2_EN_USBTLL_SHIFT 2
|
||||
#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
|
||||
|
||||
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
|
||||
#define OMAP3430_EN_WDT2_MASK (1 << 5)
|
||||
#define OMAP3430_EN_WDT2_SHIFT 5
|
||||
|
||||
/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
|
||||
#define OMAP3430_EN_CAM_MASK (1 << 0)
|
||||
#define OMAP3430_EN_CAM_SHIFT 0
|
||||
|
||||
/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
|
||||
#define OMAP3430_EN_WDT3_MASK (1 << 12)
|
||||
#define OMAP3430_EN_WDT3_SHIFT 12
|
||||
|
||||
/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
|
||||
#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
|
||||
|
||||
|
||||
/* Bits specific to each register */
|
||||
|
||||
/* CM_FCLKEN_IVA2 */
|
||||
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
|
||||
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
|
||||
|
||||
/* CM_CLKEN_PLL_IVA2 */
|
||||
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
|
||||
#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
|
||||
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
|
||||
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
|
||||
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
|
||||
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
|
||||
#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
|
||||
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_IDLEST_IVA2 */
|
||||
#define OMAP3430_ST_IVA2_SHIFT 0
|
||||
#define OMAP3430_ST_IVA2_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_PLL_IVA2 */
|
||||
#define OMAP3430_ST_IVA2_CLK_SHIFT 0
|
||||
#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_PLL_IVA2 */
|
||||
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
|
||||
#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKSEL1_PLL_IVA2 */
|
||||
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
|
||||
#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
|
||||
#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
|
||||
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
|
||||
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
|
||||
#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
/* CM_CLKSEL2_PLL_IVA2 */
|
||||
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
|
||||
/* CM_CLKSTCTRL_IVA2 */
|
||||
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_IVA2 */
|
||||
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
|
||||
|
||||
/* CM_REVISION specific bits */
|
||||
|
||||
/* CM_SYSCONFIG specific bits */
|
||||
|
||||
/* CM_CLKEN_PLL_MPU */
|
||||
#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
|
||||
#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
|
||||
#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
|
||||
#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
|
||||
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
|
||||
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
|
||||
#define OMAP3430_EN_MPU_DPLL_SHIFT 0
|
||||
#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_IDLEST_MPU */
|
||||
#define OMAP3430_ST_MPU_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_PLL_MPU */
|
||||
#define OMAP3430_ST_MPU_CLK_SHIFT 0
|
||||
#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
|
||||
#define OMAP3430_ST_MPU_CLK_WIDTH 1
|
||||
|
||||
/* CM_AUTOIDLE_PLL_MPU */
|
||||
#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
|
||||
#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKSEL1_PLL_MPU */
|
||||
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
|
||||
#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
|
||||
#define OMAP3430_MPU_CLK_SRC_WIDTH 3
|
||||
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
|
||||
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
|
||||
#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
/* CM_CLKSEL2_PLL_MPU */
|
||||
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
|
||||
/* CM_CLKSTCTRL_MPU */
|
||||
#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_MPU */
|
||||
#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN1_CORE specific bits */
|
||||
#define OMAP3430_EN_MODEM_MASK (1 << 31)
|
||||
#define OMAP3430_EN_MODEM_SHIFT 31
|
||||
|
||||
/* CM_ICLKEN1_CORE specific bits */
|
||||
#define OMAP3430_EN_ICR_MASK (1 << 29)
|
||||
#define OMAP3430_EN_ICR_SHIFT 29
|
||||
#define OMAP3430_EN_AES2_MASK (1 << 28)
|
||||
#define OMAP3430_EN_AES2_SHIFT 28
|
||||
#define OMAP3430_EN_SHA12_MASK (1 << 27)
|
||||
#define OMAP3430_EN_SHA12_SHIFT 27
|
||||
#define OMAP3430_EN_DES2_MASK (1 << 26)
|
||||
#define OMAP3430_EN_DES2_SHIFT 26
|
||||
#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
|
||||
#define OMAP3430ES1_EN_FAC_SHIFT 8
|
||||
#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
|
||||
#define OMAP3430_EN_MAILBOXES_SHIFT 7
|
||||
#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
|
||||
#define OMAP3430_EN_OMAPCTRL_SHIFT 6
|
||||
#define OMAP3430_EN_SAD2D_MASK (1 << 3)
|
||||
#define OMAP3430_EN_SAD2D_SHIFT 3
|
||||
#define OMAP3430_EN_SDRC_MASK (1 << 1)
|
||||
#define OMAP3430_EN_SDRC_SHIFT 1
|
||||
|
||||
/* AM35XX specific CM_ICLKEN1_CORE bits */
|
||||
#define AM35XX_EN_IPSS_MASK (1 << 4)
|
||||
#define AM35XX_EN_IPSS_SHIFT 4
|
||||
|
||||
/* CM_ICLKEN2_CORE */
|
||||
#define OMAP3430_EN_PKA_MASK (1 << 4)
|
||||
#define OMAP3430_EN_PKA_SHIFT 4
|
||||
#define OMAP3430_EN_AES1_MASK (1 << 3)
|
||||
#define OMAP3430_EN_AES1_SHIFT 3
|
||||
#define OMAP3430_EN_RNG_MASK (1 << 2)
|
||||
#define OMAP3430_EN_RNG_SHIFT 2
|
||||
#define OMAP3430_EN_SHA11_MASK (1 << 1)
|
||||
#define OMAP3430_EN_SHA11_SHIFT 1
|
||||
#define OMAP3430_EN_DES1_MASK (1 << 0)
|
||||
#define OMAP3430_EN_DES1_SHIFT 0
|
||||
|
||||
/* CM_ICLKEN3_CORE */
|
||||
#define OMAP3430_EN_MAD2D_SHIFT 3
|
||||
#define OMAP3430_EN_MAD2D_MASK (1 << 3)
|
||||
|
||||
/* CM_FCLKEN3_CORE specific bits */
|
||||
#define OMAP3430ES2_EN_TS_SHIFT 1
|
||||
#define OMAP3430ES2_EN_TS_MASK (1 << 1)
|
||||
#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
|
||||
#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST1_CORE specific bits */
|
||||
#define OMAP3430ES2_ST_MMC3_SHIFT 30
|
||||
#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
|
||||
#define OMAP3430_ST_ICR_SHIFT 29
|
||||
#define OMAP3430_ST_ICR_MASK (1 << 29)
|
||||
#define OMAP3430_ST_AES2_SHIFT 28
|
||||
#define OMAP3430_ST_AES2_MASK (1 << 28)
|
||||
#define OMAP3430_ST_SHA12_SHIFT 27
|
||||
#define OMAP3430_ST_SHA12_MASK (1 << 27)
|
||||
#define OMAP3430_ST_DES2_SHIFT 26
|
||||
#define OMAP3430_ST_DES2_MASK (1 << 26)
|
||||
#define OMAP3430_ST_MSPRO_SHIFT 23
|
||||
#define OMAP3430_ST_MSPRO_MASK (1 << 23)
|
||||
#define AM35XX_ST_UART4_SHIFT 23
|
||||
#define AM35XX_ST_UART4_MASK (1 << 23)
|
||||
#define OMAP3430_ST_HDQ_SHIFT 22
|
||||
#define OMAP3430_ST_HDQ_MASK (1 << 22)
|
||||
#define OMAP3430ES1_ST_FAC_SHIFT 8
|
||||
#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
|
||||
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
|
||||
#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
|
||||
#define OMAP3430_ST_MAILBOXES_SHIFT 7
|
||||
#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
|
||||
#define OMAP3430_ST_OMAPCTRL_SHIFT 6
|
||||
#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
|
||||
#define OMAP3430_ST_SAD2D_SHIFT 3
|
||||
#define OMAP3430_ST_SAD2D_MASK (1 << 3)
|
||||
#define OMAP3430_ST_SDMA_SHIFT 2
|
||||
#define OMAP3430_ST_SDMA_MASK (1 << 2)
|
||||
#define OMAP3430_ST_SDRC_SHIFT 1
|
||||
#define OMAP3430_ST_SDRC_MASK (1 << 1)
|
||||
#define OMAP3430_ST_SSI_STDBY_SHIFT 0
|
||||
#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
|
||||
|
||||
/* AM35xx specific CM_IDLEST1_CORE bits */
|
||||
#define AM35XX_ST_IPSS_SHIFT 5
|
||||
#define AM35XX_ST_IPSS_MASK (1 << 5)
|
||||
|
||||
/* CM_IDLEST2_CORE */
|
||||
#define OMAP3430_ST_PKA_SHIFT 4
|
||||
#define OMAP3430_ST_PKA_MASK (1 << 4)
|
||||
#define OMAP3430_ST_AES1_SHIFT 3
|
||||
#define OMAP3430_ST_AES1_MASK (1 << 3)
|
||||
#define OMAP3430_ST_RNG_SHIFT 2
|
||||
#define OMAP3430_ST_RNG_MASK (1 << 2)
|
||||
#define OMAP3430_ST_SHA11_SHIFT 1
|
||||
#define OMAP3430_ST_SHA11_MASK (1 << 1)
|
||||
#define OMAP3430_ST_DES1_SHIFT 0
|
||||
#define OMAP3430_ST_DES1_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST3_CORE */
|
||||
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
|
||||
#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
|
||||
#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
|
||||
#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE1_CORE */
|
||||
#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
|
||||
#define OMAP3430_AUTO_MODEM_SHIFT 31
|
||||
#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
|
||||
#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
|
||||
#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
|
||||
#define OMAP3430ES2_AUTO_ICR_SHIFT 29
|
||||
#define OMAP3430_AUTO_AES2_MASK (1 << 28)
|
||||
#define OMAP3430_AUTO_AES2_SHIFT 28
|
||||
#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
|
||||
#define OMAP3430_AUTO_SHA12_SHIFT 27
|
||||
#define OMAP3430_AUTO_DES2_MASK (1 << 26)
|
||||
#define OMAP3430_AUTO_DES2_SHIFT 26
|
||||
#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
|
||||
#define OMAP3430_AUTO_MMC2_SHIFT 25
|
||||
#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
|
||||
#define OMAP3430_AUTO_MMC1_SHIFT 24
|
||||
#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
|
||||
#define OMAP3430_AUTO_MSPRO_SHIFT 23
|
||||
#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
|
||||
#define OMAP3430_AUTO_HDQ_SHIFT 22
|
||||
#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
|
||||
#define OMAP3430_AUTO_MCSPI4_SHIFT 21
|
||||
#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
|
||||
#define OMAP3430_AUTO_MCSPI3_SHIFT 20
|
||||
#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
|
||||
#define OMAP3430_AUTO_MCSPI2_SHIFT 19
|
||||
#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
|
||||
#define OMAP3430_AUTO_MCSPI1_SHIFT 18
|
||||
#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
|
||||
#define OMAP3430_AUTO_I2C3_SHIFT 17
|
||||
#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
|
||||
#define OMAP3430_AUTO_I2C2_SHIFT 16
|
||||
#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
|
||||
#define OMAP3430_AUTO_I2C1_SHIFT 15
|
||||
#define OMAP3430_AUTO_UART2_MASK (1 << 14)
|
||||
#define OMAP3430_AUTO_UART2_SHIFT 14
|
||||
#define OMAP3430_AUTO_UART1_MASK (1 << 13)
|
||||
#define OMAP3430_AUTO_UART1_SHIFT 13
|
||||
#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
|
||||
#define OMAP3430_AUTO_GPT11_SHIFT 12
|
||||
#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
|
||||
#define OMAP3430_AUTO_GPT10_SHIFT 11
|
||||
#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
|
||||
#define OMAP3430_AUTO_MCBSP5_SHIFT 10
|
||||
#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
|
||||
#define OMAP3430_AUTO_MCBSP1_SHIFT 9
|
||||
#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
|
||||
#define OMAP3430ES1_AUTO_FAC_SHIFT 8
|
||||
#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
|
||||
#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
|
||||
#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
|
||||
#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
|
||||
#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
|
||||
#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
|
||||
#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
|
||||
#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
|
||||
#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
|
||||
#define OMAP3430ES1_AUTO_D2D_SHIFT 3
|
||||
#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
|
||||
#define OMAP3430_AUTO_SAD2D_SHIFT 3
|
||||
#define OMAP3430_AUTO_SSI_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_SSI_SHIFT 0
|
||||
|
||||
/* CM_AUTOIDLE2_CORE */
|
||||
#define OMAP3430_AUTO_PKA_MASK (1 << 4)
|
||||
#define OMAP3430_AUTO_PKA_SHIFT 4
|
||||
#define OMAP3430_AUTO_AES1_MASK (1 << 3)
|
||||
#define OMAP3430_AUTO_AES1_SHIFT 3
|
||||
#define OMAP3430_AUTO_RNG_MASK (1 << 2)
|
||||
#define OMAP3430_AUTO_RNG_SHIFT 2
|
||||
#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
|
||||
#define OMAP3430_AUTO_SHA11_SHIFT 1
|
||||
#define OMAP3430_AUTO_DES1_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_DES1_SHIFT 0
|
||||
|
||||
/* CM_AUTOIDLE3_CORE */
|
||||
#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
|
||||
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
|
||||
#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
|
||||
#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
|
||||
#define OMAP3430_AUTO_MAD2D_SHIFT 3
|
||||
#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
|
||||
|
||||
/* CM_CLKSEL_CORE */
|
||||
#define OMAP3430_CLKSEL_SSI_SHIFT 8
|
||||
#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
|
||||
#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
|
||||
#define OMAP3430_CLKSEL_GPT11_SHIFT 7
|
||||
#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
|
||||
#define OMAP3430_CLKSEL_GPT10_SHIFT 6
|
||||
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
|
||||
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
|
||||
#define OMAP3430_CLKSEL_L4_SHIFT 2
|
||||
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
|
||||
#define OMAP3430_CLKSEL_L4_WIDTH 2
|
||||
#define OMAP3430_CLKSEL_L3_SHIFT 0
|
||||
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
|
||||
#define OMAP3430_CLKSEL_L3_WIDTH 2
|
||||
#define OMAP3630_CLKSEL_96M_SHIFT 12
|
||||
#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
|
||||
#define OMAP3630_CLKSEL_96M_WIDTH 2
|
||||
|
||||
/* CM_CLKSTCTRL_CORE */
|
||||
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
|
||||
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
|
||||
#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
|
||||
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
|
||||
#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_CORE */
|
||||
#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
|
||||
#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
|
||||
#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
|
||||
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
|
||||
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_GFX */
|
||||
#define OMAP3430ES1_EN_3D_MASK (1 << 2)
|
||||
#define OMAP3430ES1_EN_3D_SHIFT 2
|
||||
#define OMAP3430ES1_EN_2D_MASK (1 << 1)
|
||||
#define OMAP3430ES1_EN_2D_SHIFT 1
|
||||
|
||||
/* CM_ICLKEN_GFX specific bits */
|
||||
|
||||
/* CM_IDLEST_GFX specific bits */
|
||||
|
||||
/* CM_CLKSEL_GFX specific bits */
|
||||
|
||||
/* CM_SLEEPDEP_GFX specific bits */
|
||||
|
||||
/* CM_CLKSTCTRL_GFX */
|
||||
#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
|
||||
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_GFX */
|
||||
#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
|
||||
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_SGX */
|
||||
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
|
||||
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
|
||||
|
||||
/* CM_IDLEST_SGX */
|
||||
#define OMAP3430ES2_ST_SGX_SHIFT 1
|
||||
#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
|
||||
|
||||
/* CM_ICLKEN_SGX */
|
||||
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSEL_SGX */
|
||||
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKSTCTRL_SGX */
|
||||
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_SGX */
|
||||
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_WKUP specific bits */
|
||||
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
|
||||
#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
|
||||
|
||||
/* CM_ICLKEN_WKUP specific bits */
|
||||
#define OMAP3430_EN_WDT1_MASK (1 << 4)
|
||||
#define OMAP3430_EN_WDT1_SHIFT 4
|
||||
#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
|
||||
#define OMAP3430_EN_32KSYNC_SHIFT 2
|
||||
|
||||
/* CM_IDLEST_WKUP specific bits */
|
||||
#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
|
||||
#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
|
||||
#define OMAP3430_ST_WDT2_SHIFT 5
|
||||
#define OMAP3430_ST_WDT2_MASK (1 << 5)
|
||||
#define OMAP3430_ST_WDT1_SHIFT 4
|
||||
#define OMAP3430_ST_WDT1_MASK (1 << 4)
|
||||
#define OMAP3430_ST_32KSYNC_SHIFT 2
|
||||
#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
|
||||
|
||||
/* CM_AUTOIDLE_WKUP */
|
||||
#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
|
||||
#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
|
||||
#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
|
||||
#define OMAP3430_AUTO_WDT2_SHIFT 5
|
||||
#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
|
||||
#define OMAP3430_AUTO_WDT1_SHIFT 4
|
||||
#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
|
||||
#define OMAP3430_AUTO_GPIO1_SHIFT 3
|
||||
#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
|
||||
#define OMAP3430_AUTO_32KSYNC_SHIFT 2
|
||||
#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
|
||||
#define OMAP3430_AUTO_GPT12_SHIFT 1
|
||||
#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_GPT1_SHIFT 0
|
||||
|
||||
/* CM_CLKSEL_WKUP */
|
||||
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
|
||||
#define OMAP3430_CLKSEL_RM_SHIFT 1
|
||||
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
|
||||
#define OMAP3430_CLKSEL_RM_WIDTH 2
|
||||
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
|
||||
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKEN_PLL */
|
||||
#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
|
||||
#define OMAP3430_PWRDN_CAM_SHIFT 30
|
||||
#define OMAP3430_PWRDN_DSS1_SHIFT 29
|
||||
#define OMAP3430_PWRDN_TV_SHIFT 28
|
||||
#define OMAP3430_PWRDN_96M_SHIFT 27
|
||||
#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
|
||||
#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
|
||||
#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
|
||||
#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
|
||||
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
|
||||
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
|
||||
#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
|
||||
#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
|
||||
#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
|
||||
#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
|
||||
#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
|
||||
#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
|
||||
#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
|
||||
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
|
||||
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
|
||||
#define OMAP3430_EN_CORE_DPLL_SHIFT 0
|
||||
#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKEN2_PLL */
|
||||
#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
|
||||
#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
|
||||
#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
|
||||
#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_IDLEST_CKGEN */
|
||||
#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
|
||||
#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
|
||||
#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
|
||||
#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
|
||||
#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
|
||||
#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
|
||||
#define OMAP3430_ST_CORE_CLK_SHIFT 0
|
||||
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST2_CKGEN */
|
||||
#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
|
||||
#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
|
||||
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
|
||||
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
|
||||
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
|
||||
#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_PLL */
|
||||
#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
|
||||
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
|
||||
#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
|
||||
#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_AUTOIDLE2_PLL */
|
||||
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
|
||||
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKSEL1_PLL */
|
||||
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
|
||||
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
|
||||
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
|
||||
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
|
||||
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
|
||||
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
|
||||
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
|
||||
#define OMAP3430_SOURCE_96M_SHIFT 6
|
||||
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
|
||||
#define OMAP3430_SOURCE_96M_WIDTH 1
|
||||
#define OMAP3430_SOURCE_54M_SHIFT 5
|
||||
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
|
||||
#define OMAP3430_SOURCE_54M_WIDTH 1
|
||||
#define OMAP3430_SOURCE_48M_SHIFT 3
|
||||
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
|
||||
|
||||
/* CM_CLKSEL2_PLL */
|
||||
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
|
||||
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
|
||||
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
|
||||
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
|
||||
#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
|
||||
#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
|
||||
#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
|
||||
#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
|
||||
|
||||
/* CM_CLKSEL3_PLL */
|
||||
#define OMAP3430_DIV_96M_SHIFT 0
|
||||
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
|
||||
#define OMAP3430_DIV_96M_WIDTH 5
|
||||
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
|
||||
#define OMAP3630_DIV_96M_WIDTH 6
|
||||
|
||||
/* CM_CLKSEL4_PLL */
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
|
||||
#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
/* CM_CLKSEL5_PLL */
|
||||
#define OMAP3430ES2_DIV_120M_SHIFT 0
|
||||
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
|
||||
#define OMAP3430ES2_DIV_120M_WIDTH 5
|
||||
|
||||
/* CM_CLKOUT_CTRL */
|
||||
#define OMAP3430_CLKOUT2_EN_SHIFT 7
|
||||
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
|
||||
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
|
||||
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
|
||||
#define OMAP3430_CLKOUT2_DIV_WIDTH 3
|
||||
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
|
||||
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
|
||||
|
||||
/* CM_FCLKEN_DSS */
|
||||
#define OMAP3430_EN_TV_MASK (1 << 2)
|
||||
#define OMAP3430_EN_TV_SHIFT 2
|
||||
#define OMAP3430_EN_DSS2_MASK (1 << 1)
|
||||
#define OMAP3430_EN_DSS2_SHIFT 1
|
||||
#define OMAP3430_EN_DSS1_MASK (1 << 0)
|
||||
#define OMAP3430_EN_DSS1_SHIFT 0
|
||||
|
||||
/* CM_ICLKEN_DSS */
|
||||
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
|
||||
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
|
||||
|
||||
/* CM_IDLEST_DSS */
|
||||
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
|
||||
#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
|
||||
#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
|
||||
#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
|
||||
#define OMAP3430ES1_ST_DSS_SHIFT 0
|
||||
#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_DSS */
|
||||
#define OMAP3430_AUTO_DSS_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_DSS_SHIFT 0
|
||||
|
||||
/* CM_CLKSEL_DSS */
|
||||
#define OMAP3430_CLKSEL_TV_SHIFT 8
|
||||
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
|
||||
#define OMAP3430_CLKSEL_TV_WIDTH 5
|
||||
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
|
||||
#define OMAP3630_CLKSEL_TV_WIDTH 6
|
||||
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
|
||||
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
|
||||
#define OMAP3430_CLKSEL_DSS1_WIDTH 5
|
||||
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
|
||||
#define OMAP3630_CLKSEL_DSS1_WIDTH 6
|
||||
|
||||
/* CM_SLEEPDEP_DSS specific bits */
|
||||
|
||||
/* CM_CLKSTCTRL_DSS */
|
||||
#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_DSS */
|
||||
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_CAM specific bits */
|
||||
#define OMAP3430_EN_CSI2_MASK (1 << 1)
|
||||
#define OMAP3430_EN_CSI2_SHIFT 1
|
||||
|
||||
/* CM_ICLKEN_CAM specific bits */
|
||||
|
||||
/* CM_IDLEST_CAM */
|
||||
#define OMAP3430_ST_CAM_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_CAM */
|
||||
#define OMAP3430_AUTO_CAM_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_CAM_SHIFT 0
|
||||
|
||||
/* CM_CLKSEL_CAM */
|
||||
#define OMAP3430_CLKSEL_CAM_SHIFT 0
|
||||
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
|
||||
#define OMAP3430_CLKSEL_CAM_WIDTH 5
|
||||
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
|
||||
#define OMAP3630_CLKSEL_CAM_WIDTH 6
|
||||
|
||||
/* CM_SLEEPDEP_CAM specific bits */
|
||||
|
||||
/* CM_CLKSTCTRL_CAM */
|
||||
#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_CAM */
|
||||
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_PER specific bits */
|
||||
|
||||
/* CM_ICLKEN_PER specific bits */
|
||||
|
||||
/* CM_IDLEST_PER */
|
||||
#define OMAP3430_ST_WDT3_SHIFT 12
|
||||
#define OMAP3430_ST_WDT3_MASK (1 << 12)
|
||||
#define OMAP3430_ST_MCBSP4_SHIFT 2
|
||||
#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
|
||||
#define OMAP3430_ST_MCBSP3_SHIFT 1
|
||||
#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
|
||||
#define OMAP3430_ST_MCBSP2_SHIFT 0
|
||||
#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_PER */
|
||||
#define OMAP3630_AUTO_UART4_MASK (1 << 18)
|
||||
#define OMAP3630_AUTO_UART4_SHIFT 18
|
||||
#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
|
||||
#define OMAP3430_AUTO_GPIO6_SHIFT 17
|
||||
#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
|
||||
#define OMAP3430_AUTO_GPIO5_SHIFT 16
|
||||
#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
|
||||
#define OMAP3430_AUTO_GPIO4_SHIFT 15
|
||||
#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
|
||||
#define OMAP3430_AUTO_GPIO3_SHIFT 14
|
||||
#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
|
||||
#define OMAP3430_AUTO_GPIO2_SHIFT 13
|
||||
#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
|
||||
#define OMAP3430_AUTO_WDT3_SHIFT 12
|
||||
#define OMAP3430_AUTO_UART3_MASK (1 << 11)
|
||||
#define OMAP3430_AUTO_UART3_SHIFT 11
|
||||
#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
|
||||
#define OMAP3430_AUTO_GPT9_SHIFT 10
|
||||
#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
|
||||
#define OMAP3430_AUTO_GPT8_SHIFT 9
|
||||
#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
|
||||
#define OMAP3430_AUTO_GPT7_SHIFT 8
|
||||
#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
|
||||
#define OMAP3430_AUTO_GPT6_SHIFT 7
|
||||
#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
|
||||
#define OMAP3430_AUTO_GPT5_SHIFT 6
|
||||
#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
|
||||
#define OMAP3430_AUTO_GPT4_SHIFT 5
|
||||
#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
|
||||
#define OMAP3430_AUTO_GPT3_SHIFT 4
|
||||
#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
|
||||
#define OMAP3430_AUTO_GPT2_SHIFT 3
|
||||
#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
|
||||
#define OMAP3430_AUTO_MCBSP4_SHIFT 2
|
||||
#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
|
||||
#define OMAP3430_AUTO_MCBSP3_SHIFT 1
|
||||
#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
|
||||
#define OMAP3430_AUTO_MCBSP2_SHIFT 0
|
||||
|
||||
/* CM_CLKSEL_PER */
|
||||
#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
|
||||
#define OMAP3430_CLKSEL_GPT9_SHIFT 7
|
||||
#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
|
||||
#define OMAP3430_CLKSEL_GPT8_SHIFT 6
|
||||
#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
|
||||
#define OMAP3430_CLKSEL_GPT7_SHIFT 5
|
||||
#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
|
||||
#define OMAP3430_CLKSEL_GPT6_SHIFT 4
|
||||
#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
|
||||
#define OMAP3430_CLKSEL_GPT5_SHIFT 3
|
||||
#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
|
||||
#define OMAP3430_CLKSEL_GPT4_SHIFT 2
|
||||
#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
|
||||
#define OMAP3430_CLKSEL_GPT3_SHIFT 1
|
||||
#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
|
||||
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
|
||||
|
||||
/* CM_SLEEPDEP_PER specific bits */
|
||||
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* CM_CLKSTCTRL_PER */
|
||||
#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_PER */
|
||||
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSEL1_EMU */
|
||||
#define OMAP3430_DIV_DPLL4_SHIFT 24
|
||||
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
|
||||
#define OMAP3430_DIV_DPLL4_WIDTH 5
|
||||
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
|
||||
#define OMAP3630_DIV_DPLL4_WIDTH 6
|
||||
#define OMAP3430_DIV_DPLL3_SHIFT 16
|
||||
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
|
||||
#define OMAP3430_DIV_DPLL3_WIDTH 5
|
||||
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
|
||||
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
|
||||
#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
|
||||
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
|
||||
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
|
||||
#define OMAP3430_CLKSEL_PCLK_WIDTH 3
|
||||
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
|
||||
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
|
||||
#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
|
||||
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
|
||||
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
|
||||
#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
|
||||
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
|
||||
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
|
||||
#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
|
||||
#define OMAP3430_MUX_CTRL_SHIFT 0
|
||||
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
|
||||
#define OMAP3430_MUX_CTRL_WIDTH 2
|
||||
|
||||
/* CM_CLKSTCTRL_EMU */
|
||||
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_EMU */
|
||||
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSEL2_EMU specific bits */
|
||||
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
|
||||
#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
|
||||
#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
|
||||
|
||||
/* CM_CLKSEL3_EMU specific bits */
|
||||
#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
|
||||
#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
|
||||
#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
|
||||
#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
|
||||
|
||||
/* CM_POLCTRL */
|
||||
#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_NEON */
|
||||
#define OMAP3430_ST_NEON_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSTCTRL_NEON */
|
||||
#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
|
||||
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
|
||||
|
||||
/* CM_FCLKEN_USBHOST */
|
||||
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
|
||||
#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
|
||||
#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
|
||||
#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
|
||||
|
||||
/* CM_ICLKEN_USBHOST */
|
||||
#define OMAP3430ES2_EN_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_USBHOST */
|
||||
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
|
||||
#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
|
||||
#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
|
||||
#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
|
||||
|
||||
/* CM_AUTOIDLE_USBHOST */
|
||||
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
|
||||
|
||||
/* CM_SLEEPDEP_USBHOST */
|
||||
#define OMAP3430ES2_EN_MPU_SHIFT 1
|
||||
#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
|
||||
#define OMAP3430ES2_EN_IVA2_SHIFT 2
|
||||
#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* CM_CLKSTCTRL_USBHOST */
|
||||
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
|
||||
|
||||
/* CM_CLKSTST_USBHOST */
|
||||
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
|
||||
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
|
||||
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
|
||||
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
|
||||
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -18,340 +18,34 @@
|
||||
|
||||
#include "prm.h"
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
|
||||
#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
|
||||
#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_AIPOFF_SHIFT 8
|
||||
#define AM33XX_AIPOFF_MASK (1 << 8)
|
||||
|
||||
/* Used by PM_WKUP_PWRSTST */
|
||||
#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
|
||||
#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
|
||||
#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
|
||||
#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
|
||||
#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
|
||||
#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
|
||||
#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
|
||||
#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
|
||||
#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
|
||||
#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
|
||||
#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
|
||||
#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
|
||||
|
||||
/* Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_EMULATION_M3_RST_SHIFT 6
|
||||
#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
|
||||
|
||||
/* Used by RM_MPU_RSTST */
|
||||
#define AM33XX_EMULATION_MPU_RST_SHIFT 5
|
||||
#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
|
||||
#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
|
||||
#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC4_SHIFT 6
|
||||
#define AM33XX_ENFUNC4_MASK (1 << 6)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
|
||||
#define AM33XX_ENFUNC5_SHIFT 7
|
||||
#define AM33XX_ENFUNC5_MASK (1 << 7)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
|
||||
#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_FORCEWKUP_EN_SHIFT 10
|
||||
#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_FORCEWKUP_ST_SHIFT 10
|
||||
#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL */
|
||||
#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
|
||||
#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL */
|
||||
#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
|
||||
#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
|
||||
|
||||
/* Used by PM_GFX_PWRSTST */
|
||||
#define AM33XX_GFX_MEM_STATEST_SHIFT 4
|
||||
#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
|
||||
|
||||
/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
|
||||
#define AM33XX_GFX_RST_SHIFT 0
|
||||
#define AM33XX_GFX_RST_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
|
||||
#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
|
||||
#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
|
||||
|
||||
/* Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
|
||||
#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
|
||||
|
||||
/* Used by RM_MPU_RSTST */
|
||||
#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
|
||||
#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_ICEPICK_RST_SHIFT 9
|
||||
#define AM33XX_ICEPICK_RST_MASK (1 << 9)
|
||||
|
||||
/* Used by RM_PER_RSTCTRL */
|
||||
#define AM33XX_PRUSS_LRST_SHIFT 1
|
||||
#define AM33XX_PRUSS_LRST_MASK (1 << 1)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
|
||||
#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
|
||||
#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
|
||||
#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
|
||||
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
|
||||
*/
|
||||
#define AM33XX_INTRANSITION_SHIFT 20
|
||||
#define AM33XX_INTRANSITION_MASK (1 << 20)
|
||||
|
||||
/* Used by PM_CEFUSE_PWRSTST */
|
||||
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
|
||||
#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
|
||||
|
||||
/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
|
||||
#define AM33XX_LOGICRETSTATE_SHIFT 2
|
||||
#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
|
||||
|
||||
/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
|
||||
#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
|
||||
#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
|
||||
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
|
||||
*/
|
||||
#define AM33XX_LOGICSTATEST_SHIFT 2
|
||||
#define AM33XX_LOGICSTATEST_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
|
||||
* PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
|
||||
*/
|
||||
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
|
||||
#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
|
||||
#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
|
||||
#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_L1_STATEST_SHIFT 6
|
||||
#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
|
||||
#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
|
||||
#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_L2_STATEST_SHIFT 8
|
||||
#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
|
||||
#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
|
||||
|
||||
/* Used by PM_MPU_PWRSTCTRL */
|
||||
#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
|
||||
#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
|
||||
|
||||
/* Used by PM_MPU_PWRSTST */
|
||||
#define AM33XX_MPU_RAM_STATEST_SHIFT 4
|
||||
#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
|
||||
#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
|
||||
#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
|
||||
|
||||
/* Used by RM_PER_RSTCTRL */
|
||||
#define AM33XX_PCI_LRST_SHIFT 0
|
||||
#define AM33XX_PCI_LRST_MASK (1 << 0)
|
||||
|
||||
/* Renamed from PCI_LRST Used by RM_PER_RSTST */
|
||||
#define AM33XX_PCI_LRST_5_5_SHIFT 5
|
||||
#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
|
||||
#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
|
||||
#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_PER_MEM_STATEST_SHIFT 17
|
||||
#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
|
||||
|
||||
/*
|
||||
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
|
||||
* PM_MPU_PWRSTCTRL
|
||||
*/
|
||||
#define AM33XX_POWERSTATE_SHIFT 0
|
||||
#define AM33XX_POWERSTATE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
|
||||
#define AM33XX_POWERSTATEST_SHIFT 0
|
||||
#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
|
||||
#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
|
||||
|
||||
/* Used by PM_PER_PWRSTCTRL */
|
||||
#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
|
||||
#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
|
||||
|
||||
/* Used by PM_PER_PWRSTST */
|
||||
#define AM33XX_RAM_MEM_STATEST_SHIFT 21
|
||||
#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_RETMODE_ENABLE_SHIFT 0
|
||||
#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* Used by REVISION_PRM */
|
||||
#define AM33XX_REV_SHIFT 0
|
||||
#define AM33XX_REV_MASK (0xff << 0)
|
||||
|
||||
/* Used by PRM_RSTTIME */
|
||||
#define AM33XX_RSTTIME1_SHIFT 0
|
||||
#define AM33XX_RSTTIME1_MASK (0xff << 0)
|
||||
|
||||
/* Used by PRM_RSTTIME */
|
||||
#define AM33XX_RSTTIME2_SHIFT 8
|
||||
#define AM33XX_RSTTIME2_MASK (0x1f << 8)
|
||||
|
||||
/* Used by PRM_RSTCTRL */
|
||||
#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
|
||||
#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
|
||||
|
||||
/* Used by PRM_RSTCTRL */
|
||||
#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
|
||||
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_SLPCNT_VALUE_SHIFT 16
|
||||
#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_SRAMLDO_STATUS_SHIFT 8
|
||||
#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
|
||||
#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
|
||||
#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_STARTUP_COUNT_SHIFT 24
|
||||
#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
|
||||
|
||||
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
|
||||
#define AM33XX_TRANSITION_EN_SHIFT 8
|
||||
#define AM33XX_TRANSITION_EN_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
|
||||
#define AM33XX_TRANSITION_ST_SHIFT 8
|
||||
#define AM33XX_TRANSITION_ST_MASK (1 << 8)
|
||||
|
||||
/* Used by PRM_SRAM_COUNT */
|
||||
#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
|
||||
#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_WDT0_RST_SHIFT 3
|
||||
#define AM33XX_WDT0_RST_MASK (1 << 3)
|
||||
|
||||
/* Used by PRM_RSTST */
|
||||
#define AM33XX_WDT1_RST_SHIFT 4
|
||||
#define AM33XX_WDT1_RST_MASK (1 << 4)
|
||||
|
||||
/* Used by RM_WKUP_RSTCTRL */
|
||||
#define AM33XX_WKUP_M3_LRST_SHIFT 3
|
||||
#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
|
||||
|
||||
/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
|
||||
#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
|
||||
#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
|
||||
|
||||
#endif
|
||||
|
||||
@ -16,115 +16,25 @@
|
||||
|
||||
#include "prm3xxx.h"
|
||||
|
||||
/* Shared register bits */
|
||||
|
||||
/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
|
||||
#define OMAP3430_ON_SHIFT 24
|
||||
#define OMAP3430_ON_MASK (0xff << 24)
|
||||
#define OMAP3430_ONLP_SHIFT 16
|
||||
#define OMAP3430_ONLP_MASK (0xff << 16)
|
||||
#define OMAP3430_RET_SHIFT 8
|
||||
#define OMAP3430_RET_MASK (0xff << 8)
|
||||
#define OMAP3430_OFF_SHIFT 0
|
||||
#define OMAP3430_OFF_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
|
||||
#define OMAP3430_ERROROFFSET_SHIFT 24
|
||||
#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
|
||||
#define OMAP3430_ERRORGAIN_SHIFT 16
|
||||
#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
|
||||
#define OMAP3430_INITVOLTAGE_SHIFT 8
|
||||
#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
|
||||
#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
|
||||
#define OMAP3430_INITVDD_MASK (1 << 2)
|
||||
#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
|
||||
#define OMAP3430_VPENABLE_MASK (1 << 0)
|
||||
|
||||
/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
|
||||
#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
|
||||
#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
|
||||
#define OMAP3430_VSTEPMIN_SHIFT 0
|
||||
#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
|
||||
#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
|
||||
#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
|
||||
#define OMAP3430_VSTEPMAX_SHIFT 0
|
||||
#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
|
||||
#define OMAP3430_VDDMAX_SHIFT 24
|
||||
#define OMAP3430_VDDMAX_MASK (0xff << 24)
|
||||
#define OMAP3430_VDDMIN_SHIFT 16
|
||||
#define OMAP3430_VDDMIN_MASK (0xff << 16)
|
||||
#define OMAP3430_TIMEOUT_SHIFT 0
|
||||
#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
|
||||
|
||||
/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
|
||||
#define OMAP3430_VPVOLTAGE_SHIFT 0
|
||||
#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
|
||||
#define OMAP3430_VPINIDLE_MASK (1 << 0)
|
||||
|
||||
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
|
||||
#define OMAP3430_EN_PER_SHIFT 7
|
||||
#define OMAP3430_EN_PER_MASK (1 << 7)
|
||||
|
||||
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
|
||||
#define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
|
||||
|
||||
/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
|
||||
#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
|
||||
|
||||
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
|
||||
#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
|
||||
* PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
|
||||
* PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
|
||||
*/
|
||||
#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
|
||||
#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
|
||||
|
||||
/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
|
||||
#define OMAP3430_WKUP_ST_MASK (1 << 0)
|
||||
|
||||
/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
|
||||
#define OMAP3430_WKUP_EN_MASK (1 << 0)
|
||||
|
||||
/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
|
||||
#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
|
||||
#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
|
||||
#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
|
||||
#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
|
||||
#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
|
||||
#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
|
||||
#define OMAP3430_GRPSEL_I2C3_SHIFT 17
|
||||
#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
|
||||
#define OMAP3430_GRPSEL_I2C2_SHIFT 16
|
||||
#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
|
||||
#define OMAP3430_GRPSEL_I2C1_SHIFT 15
|
||||
#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
|
||||
#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
|
||||
#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
|
||||
#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
|
||||
#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
|
||||
#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
|
||||
#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
|
||||
#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
|
||||
#define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
|
||||
|
||||
/*
|
||||
* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
|
||||
* PM_PWSTCTRL_PER shared bits
|
||||
*/
|
||||
#define OMAP3430_MEMONSTATE_SHIFT 16
|
||||
#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
|
||||
#define OMAP3430_MEMRETSTATE_MASK (1 << 8)
|
||||
|
||||
/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
|
||||
#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
|
||||
#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
|
||||
#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
|
||||
@ -132,480 +42,89 @@
|
||||
#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
|
||||
#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
|
||||
#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
|
||||
#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
|
||||
#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
|
||||
#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
|
||||
#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
|
||||
#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
|
||||
#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
|
||||
#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
|
||||
#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
|
||||
#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
|
||||
#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
|
||||
#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
|
||||
|
||||
/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
|
||||
#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
|
||||
#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
|
||||
#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
|
||||
#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
|
||||
#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
|
||||
#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
|
||||
|
||||
/* Bits specific to each register */
|
||||
|
||||
/* RM_RSTCTRL_IVA2 */
|
||||
#define OMAP3430_RST3_IVA2_MASK (1 << 2)
|
||||
#define OMAP3430_RST2_IVA2_MASK (1 << 1)
|
||||
#define OMAP3430_RST1_IVA2_MASK (1 << 0)
|
||||
|
||||
/* RM_RSTST_IVA2 specific bits */
|
||||
#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
|
||||
#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
|
||||
#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
|
||||
#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
|
||||
#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
|
||||
#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
|
||||
|
||||
/* PM_WKDEP_IVA2 specific bits */
|
||||
|
||||
/* PM_PWSTCTRL_IVA2 specific bits */
|
||||
#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
|
||||
#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
|
||||
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
|
||||
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
|
||||
#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
|
||||
#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
|
||||
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
|
||||
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
|
||||
#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
|
||||
#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
|
||||
#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
|
||||
#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
|
||||
|
||||
/* PM_PWSTST_IVA2 specific bits */
|
||||
#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
|
||||
#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
|
||||
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
|
||||
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
|
||||
#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
|
||||
#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
|
||||
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
|
||||
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
|
||||
|
||||
/* PM_PREPWSTST_IVA2 specific bits */
|
||||
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
|
||||
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
|
||||
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
|
||||
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
|
||||
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
|
||||
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
|
||||
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
|
||||
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
|
||||
|
||||
/* PRM_IRQSTATUS_IVA2 specific bits */
|
||||
#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
|
||||
#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
|
||||
|
||||
/* PRM_IRQENABLE_IVA2 specific bits */
|
||||
#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
|
||||
#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
|
||||
|
||||
/* PRM_REVISION specific bits */
|
||||
|
||||
/* PRM_SYSCONFIG specific bits */
|
||||
|
||||
/* PRM_IRQSTATUS_MPU specific bits */
|
||||
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
|
||||
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
|
||||
#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
|
||||
#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
|
||||
#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
|
||||
#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
|
||||
#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
|
||||
#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
|
||||
#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
|
||||
#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
|
||||
#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
|
||||
#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
|
||||
#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
|
||||
#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
|
||||
#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
|
||||
#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
|
||||
#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
|
||||
#define OMAP3430_IO_ST_MASK (1 << 9)
|
||||
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
|
||||
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
|
||||
#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
|
||||
#define OMAP3430_MPU_DPLL_ST_SHIFT 7
|
||||
#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
|
||||
#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
|
||||
#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
|
||||
#define OMAP3430_CORE_DPLL_ST_SHIFT 5
|
||||
#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
|
||||
#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
|
||||
#define OMAP3430_EVGENON_ST_MASK (1 << 2)
|
||||
#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
|
||||
|
||||
/* PRM_IRQENABLE_MPU specific bits */
|
||||
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
|
||||
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
|
||||
#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
|
||||
#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
|
||||
#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
|
||||
#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
|
||||
#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
|
||||
#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
|
||||
#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
|
||||
#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
|
||||
#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
|
||||
#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
|
||||
#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
|
||||
#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
|
||||
#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
|
||||
#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
|
||||
#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
|
||||
#define OMAP3430_IO_EN_MASK (1 << 9)
|
||||
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
|
||||
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
|
||||
#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
|
||||
#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
|
||||
#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
|
||||
#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
|
||||
#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
|
||||
#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
|
||||
#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
|
||||
#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
|
||||
#define OMAP3430_EVGENON_EN_MASK (1 << 2)
|
||||
#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
|
||||
|
||||
/* RM_RSTST_MPU specific bits */
|
||||
#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
|
||||
|
||||
/* PM_WKDEP_MPU specific bits */
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_EVGENCTRL_MPU */
|
||||
#define OMAP3430_OFFLOADMODE_SHIFT 3
|
||||
#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
|
||||
#define OMAP3430_ONLOADMODE_SHIFT 1
|
||||
#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
|
||||
#define OMAP3430_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* PM_EVGENONTIM_MPU */
|
||||
#define OMAP3430_ONTIMEVAL_SHIFT 0
|
||||
#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
|
||||
|
||||
/* PM_EVGENOFFTIM_MPU */
|
||||
#define OMAP3430_OFFTIMEVAL_SHIFT 0
|
||||
#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
|
||||
|
||||
/* PM_PWSTCTRL_MPU specific bits */
|
||||
#define OMAP3430_L2CACHEONSTATE_SHIFT 16
|
||||
#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
|
||||
#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
|
||||
#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
|
||||
|
||||
/* PM_PWSTST_MPU specific bits */
|
||||
#define OMAP3430_L2CACHESTATEST_SHIFT 6
|
||||
#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
|
||||
#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
|
||||
|
||||
/* PM_PREPWSTST_MPU specific bits */
|
||||
#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
|
||||
#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
|
||||
#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
|
||||
|
||||
/* RM_RSTCTRL_CORE */
|
||||
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
|
||||
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
|
||||
|
||||
/* RM_RSTST_CORE specific bits */
|
||||
#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
|
||||
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
|
||||
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
|
||||
|
||||
/* PM_WKEN1_CORE specific bits */
|
||||
|
||||
/* PM_MPUGRPSEL1_CORE specific bits */
|
||||
#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
|
||||
|
||||
/* PM_IVA2GRPSEL1_CORE specific bits */
|
||||
|
||||
/* PM_WKST1_CORE specific bits */
|
||||
|
||||
/* PM_PWSTCTRL_CORE specific bits */
|
||||
#define OMAP3430_MEM2ONSTATE_SHIFT 18
|
||||
#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
|
||||
#define OMAP3430_MEM1ONSTATE_SHIFT 16
|
||||
#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
|
||||
#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
|
||||
#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
|
||||
|
||||
/* PM_PWSTST_CORE specific bits */
|
||||
#define OMAP3430_MEM2STATEST_SHIFT 6
|
||||
#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
|
||||
#define OMAP3430_MEM1STATEST_SHIFT 4
|
||||
#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
|
||||
|
||||
/* PM_PREPWSTST_CORE specific bits */
|
||||
#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
|
||||
#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
|
||||
#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
|
||||
#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
|
||||
|
||||
/* RM_RSTST_GFX specific bits */
|
||||
|
||||
/* PM_WKDEP_GFX specific bits */
|
||||
#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_PWSTCTRL_GFX specific bits */
|
||||
|
||||
/* PM_PWSTST_GFX specific bits */
|
||||
|
||||
/* PM_PREPWSTST_GFX specific bits */
|
||||
|
||||
/* PM_WKEN_WKUP specific bits */
|
||||
#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
|
||||
#define OMAP3430_EN_IO_MASK (1 << 8)
|
||||
#define OMAP3430_EN_GPIO1_MASK (1 << 3)
|
||||
|
||||
/* PM_MPUGRPSEL_WKUP specific bits */
|
||||
|
||||
/* PM_IVA2GRPSEL_WKUP specific bits */
|
||||
|
||||
/* PM_WKST_WKUP specific bits */
|
||||
#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
|
||||
#define OMAP3430_ST_IO_MASK (1 << 8)
|
||||
|
||||
/* PRM_CLKSEL */
|
||||
#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
|
||||
#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
|
||||
#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
|
||||
|
||||
/* PRM_CLKOUT_CTRL */
|
||||
#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
|
||||
#define OMAP3430_CLKOUT_EN_SHIFT 7
|
||||
|
||||
/* RM_RSTST_DSS specific bits */
|
||||
|
||||
/* PM_WKEN_DSS */
|
||||
#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
|
||||
|
||||
/* PM_WKDEP_DSS specific bits */
|
||||
#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_PWSTCTRL_DSS specific bits */
|
||||
|
||||
/* PM_PWSTST_DSS specific bits */
|
||||
|
||||
/* PM_PREPWSTST_DSS specific bits */
|
||||
|
||||
/* RM_RSTST_CAM specific bits */
|
||||
|
||||
/* PM_WKDEP_CAM specific bits */
|
||||
#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_PWSTCTRL_CAM specific bits */
|
||||
|
||||
/* PM_PWSTST_CAM specific bits */
|
||||
|
||||
/* PM_PREPWSTST_CAM specific bits */
|
||||
|
||||
/* PM_PWSTCTRL_USBHOST specific bits */
|
||||
#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
|
||||
|
||||
/* RM_RSTST_PER specific bits */
|
||||
|
||||
/* PM_WKEN_PER specific bits */
|
||||
|
||||
/* PM_MPUGRPSEL_PER specific bits */
|
||||
|
||||
/* PM_IVA2GRPSEL_PER specific bits */
|
||||
|
||||
/* PM_WKST_PER specific bits */
|
||||
|
||||
/* PM_WKDEP_PER specific bits */
|
||||
#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_PWSTCTRL_PER specific bits */
|
||||
|
||||
/* PM_PWSTST_PER specific bits */
|
||||
|
||||
/* PM_PREPWSTST_PER specific bits */
|
||||
|
||||
/* RM_RSTST_EMU specific bits */
|
||||
|
||||
/* PM_PWSTST_EMU specific bits */
|
||||
|
||||
/* PRM_VC_SMPS_SA */
|
||||
#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
|
||||
#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
|
||||
#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
|
||||
#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
|
||||
|
||||
/* PRM_VC_SMPS_VOL_RA */
|
||||
#define OMAP3430_VOLRA1_SHIFT 16
|
||||
#define OMAP3430_VOLRA1_MASK (0xff << 16)
|
||||
#define OMAP3430_VOLRA0_SHIFT 0
|
||||
#define OMAP3430_VOLRA0_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VC_SMPS_CMD_RA */
|
||||
#define OMAP3430_CMDRA1_SHIFT 16
|
||||
#define OMAP3430_CMDRA1_MASK (0xff << 16)
|
||||
#define OMAP3430_CMDRA0_SHIFT 0
|
||||
#define OMAP3430_CMDRA0_MASK (0xff << 0)
|
||||
|
||||
/* PRM_VC_CMD_VAL_0 specific bits */
|
||||
#define OMAP3430_VC_CMD_ON_SHIFT 24
|
||||
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
|
||||
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
|
||||
#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
|
||||
#define OMAP3430_VC_CMD_RET_SHIFT 8
|
||||
#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
|
||||
#define OMAP3430_VC_CMD_OFF_SHIFT 0
|
||||
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
|
||||
|
||||
/* PRM_VC_CMD_VAL_1 specific bits */
|
||||
|
||||
/* PRM_VC_CH_CONF */
|
||||
#define OMAP3430_CMD1_MASK (1 << 20)
|
||||
#define OMAP3430_RACEN1_MASK (1 << 19)
|
||||
#define OMAP3430_RAC1_MASK (1 << 18)
|
||||
#define OMAP3430_RAV1_MASK (1 << 17)
|
||||
#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
|
||||
#define OMAP3430_CMD0_MASK (1 << 4)
|
||||
#define OMAP3430_RACEN0_MASK (1 << 3)
|
||||
#define OMAP3430_RAC0_MASK (1 << 2)
|
||||
#define OMAP3430_RAV0_MASK (1 << 1)
|
||||
#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
|
||||
|
||||
/* PRM_VC_I2C_CFG */
|
||||
#define OMAP3430_HSMASTER_MASK (1 << 5)
|
||||
#define OMAP3430_SREN_MASK (1 << 4)
|
||||
#define OMAP3430_HSEN_MASK (1 << 3)
|
||||
#define OMAP3430_MCODE_SHIFT 0
|
||||
#define OMAP3430_MCODE_MASK (0x7 << 0)
|
||||
|
||||
/* PRM_VC_BYPASS_VAL */
|
||||
#define OMAP3430_VALID_MASK (1 << 24)
|
||||
#define OMAP3430_DATA_SHIFT 16
|
||||
#define OMAP3430_DATA_MASK (0xff << 16)
|
||||
#define OMAP3430_REGADDR_SHIFT 8
|
||||
#define OMAP3430_REGADDR_MASK (0xff << 8)
|
||||
#define OMAP3430_SLAVEADDR_SHIFT 0
|
||||
#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
|
||||
|
||||
/* PRM_RSTCTRL */
|
||||
#define OMAP3430_RST_DPLL3_MASK (1 << 2)
|
||||
#define OMAP3430_RST_GS_MASK (1 << 1)
|
||||
|
||||
/* PRM_RSTTIME */
|
||||
#define OMAP3430_RSTTIME2_SHIFT 8
|
||||
#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
|
||||
#define OMAP3430_RSTTIME1_SHIFT 0
|
||||
#define OMAP3430_RSTTIME1_MASK (0xff << 0)
|
||||
|
||||
/* PRM_RSTST */
|
||||
#define OMAP3430_ICECRUSHER_RST_SHIFT 10
|
||||
#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
|
||||
#define OMAP3430_ICEPICK_RST_SHIFT 9
|
||||
#define OMAP3430_ICEPICK_RST_MASK (1 << 9)
|
||||
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
|
||||
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
|
||||
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
|
||||
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
|
||||
#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
|
||||
#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
|
||||
#define OMAP3430_SECURE_WD_RST_SHIFT 5
|
||||
#define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
|
||||
#define OMAP3430_MPU_WD_RST_SHIFT 4
|
||||
#define OMAP3430_MPU_WD_RST_MASK (1 << 4)
|
||||
#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
|
||||
#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
|
||||
#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
|
||||
#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
|
||||
#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
|
||||
#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
|
||||
|
||||
/* PRM_VOLTCTRL */
|
||||
#define OMAP3430_SEL_VMODE_MASK (1 << 4)
|
||||
#define OMAP3430_SEL_OFF_MASK (1 << 3)
|
||||
#define OMAP3430_AUTO_OFF_MASK (1 << 2)
|
||||
#define OMAP3430_AUTO_RET_MASK (1 << 1)
|
||||
#define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
|
||||
|
||||
/* PRM_SRAM_PCHARGE */
|
||||
#define OMAP3430_PCHARGE_TIME_SHIFT 0
|
||||
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
|
||||
|
||||
/* PRM_CLKSRC_CTRL */
|
||||
#define OMAP3430_SYSCLKDIV_SHIFT 6
|
||||
#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
|
||||
#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
|
||||
#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
|
||||
#define OMAP3430_SYSCLKSEL_SHIFT 0
|
||||
#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
|
||||
|
||||
/* PRM_VOLTSETUP1 */
|
||||
#define OMAP3430_SETUP_TIME2_SHIFT 16
|
||||
#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
|
||||
#define OMAP3430_SETUP_TIME1_SHIFT 0
|
||||
#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
|
||||
|
||||
/* PRM_VOLTOFFSET */
|
||||
#define OMAP3430_OFFSET_TIME_SHIFT 0
|
||||
#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
|
||||
|
||||
/* PRM_CLKSETUP */
|
||||
#define OMAP3430_SETUP_TIME_SHIFT 0
|
||||
#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
|
||||
|
||||
/* PRM_POLCTRL */
|
||||
#define OMAP3430_OFFMODE_POL_MASK (1 << 3)
|
||||
#define OMAP3430_CLKOUT_POL_MASK (1 << 2)
|
||||
#define OMAP3430_CLKREQ_POL_MASK (1 << 1)
|
||||
#define OMAP3430_EXTVOL_POL_MASK (1 << 0)
|
||||
|
||||
/* PRM_VOLTSETUP2 */
|
||||
#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
|
||||
#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
|
||||
|
||||
/* PRM_VP1_CONFIG specific bits */
|
||||
|
||||
/* PRM_VP1_VSTEPMIN specific bits */
|
||||
|
||||
/* PRM_VP1_VSTEPMAX specific bits */
|
||||
|
||||
/* PRM_VP1_VLIMITTO specific bits */
|
||||
|
||||
/* PRM_VP1_VOLTAGE specific bits */
|
||||
|
||||
/* PRM_VP1_STATUS specific bits */
|
||||
|
||||
/* PRM_VP2_CONFIG specific bits */
|
||||
|
||||
/* PRM_VP2_VSTEPMIN specific bits */
|
||||
|
||||
/* PRM_VP2_VSTEPMAX specific bits */
|
||||
|
||||
/* PRM_VP2_VLIMITTO specific bits */
|
||||
|
||||
/* PRM_VP2_VOLTAGE specific bits */
|
||||
|
||||
/* PRM_VP2_STATUS specific bits */
|
||||
|
||||
/* RM_RSTST_NEON specific bits */
|
||||
|
||||
/* PM_WKDEP_NEON specific bits */
|
||||
|
||||
/* PM_PWSTCTRL_NEON specific bits */
|
||||
|
||||
/* PM_PWSTST_NEON specific bits */
|
||||
|
||||
/* PM_PREPWSTST_NEON specific bits */
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user