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msm:disp:dpu1: add support for display for SC7180 target
Add display hw catalog changes for SC7180 target. Changes in v1: - Configure register offsets and capabilities for the display hw blocks. Changes in v2: - mdss_irq data type has changed in the dependent patch, accommodate the necessary changes. - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - fix kernel checkpatch errors in v2 Changes in v4: - move documentation into seperate patch (Rob Herring). This patch has dependency on the below series https://patchwork.kernel.org/patch/11253647/ Co-developed-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> [rebase on hw catalog const'ification, and add more const's] Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Kalyan Thota
Rob Clark
parent
854f94226a
commit
7bdc0c4b81
@ -11,11 +11,17 @@
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#include "dpu_hw_catalog_format.h"
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#include "dpu_kms.h"
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#define VIG_SDM845_MASK \
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(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
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#define VIG_MASK \
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(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
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BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
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BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
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#define VIG_SDM845_MASK \
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(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
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#define VIG_SC7180_MASK \
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(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4))
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#define DMA_SDM845_MASK \
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(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
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BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
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@ -27,6 +33,9 @@
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#define MIXER_SDM845_MASK \
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(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
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#define MIXER_SC7180_MASK \
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(BIT(DPU_DIM_LAYER))
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#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
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#define PINGPONG_SDM845_SPLIT_MASK \
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@ -60,6 +69,16 @@ static const struct dpu_caps sdm845_dpu_caps = {
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.has_idle_pc = true,
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};
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static const struct dpu_caps sc7180_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x9,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
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.ubwc_version = DPU_HW_UBWC_VER_20,
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.has_dim_layer = true,
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.has_idle_pc = true,
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};
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static const struct dpu_mdp_cfg sdm845_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -85,6 +104,23 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc7180_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.highest_bank_bit = 0x3,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.reg_off = 0x2BC, .bit_off = 8},
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},
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};
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/*************************************************************
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* CTL sub blocks config
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*************************************************************/
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@ -116,6 +152,24 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sc7180_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0xE4,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x1200, .len = 0xE4,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x1400, .len = 0xE4,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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};
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/*************************************************************
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* SSPP sub blocks config
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*************************************************************/
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@ -203,9 +257,23 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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};
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static const struct dpu_sspp_cfg sc7180_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
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sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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};
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/*************************************************************
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* MIXER sub blocks config
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*************************************************************/
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/* SDM845 */
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static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
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.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.maxblendstages = 11, /* excluding base layer */
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@ -215,23 +283,46 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
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},
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};
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#define LM_BLK(_name, _id, _base, _pp, _lmpair) \
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#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair) \
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{ \
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.name = _name, .id = _id, \
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.base = _base, .len = 0x320, \
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.features = MIXER_SDM845_MASK, \
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.sblk = &sdm845_lm_sblk, \
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.features = _fmask, \
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.sblk = _sblk, \
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.pingpong = _pp, \
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.lm_pair_mask = (1 << _lmpair) \
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}
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static const struct dpu_lm_cfg sdm845_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, PINGPONG_0, LM_1),
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LM_BLK("lm_1", LM_1, 0x45000, PINGPONG_1, LM_0),
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LM_BLK("lm_2", LM_2, 0x46000, PINGPONG_2, LM_5),
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LM_BLK("lm_3", LM_3, 0x0, PINGPONG_MAX, 0),
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LM_BLK("lm_4", LM_4, 0x0, PINGPONG_MAX, 0),
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LM_BLK("lm_5", LM_5, 0x49000, PINGPONG_3, LM_2),
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_0, LM_1),
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LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_1, LM_0),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_2, LM_5),
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LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_MAX, 0),
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LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_MAX, 0),
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LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_3, LM_2),
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};
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/* SC7180 */
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static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
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.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.maxblendstages = 7, /* excluding base layer */
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.blendstage_base = { /* offsets relative to mixer base */
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0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
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},
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};
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static const struct dpu_lm_cfg sc7180_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
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&sc7180_lm_sblk, PINGPONG_0, LM_1),
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LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
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&sc7180_lm_sblk, PINGPONG_1, LM_0),
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};
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/*************************************************************
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@ -271,6 +362,11 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
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};
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static struct dpu_pingpong_cfg sc7180_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
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};
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/*************************************************************
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* INTF sub blocks config
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*************************************************************/
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@ -290,6 +386,11 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
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INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
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};
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static const struct dpu_intf_cfg sc7180_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
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};
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/*************************************************************
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* VBIF sub blocks config
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*************************************************************/
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@ -340,6 +441,10 @@ static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
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{.fl = 0, .lut = 0x11222222223357}
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};
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static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
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{.fl = 0, .lut = 0x0011222222335777},
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};
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static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
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{.fl = 10, .lut = 0x344556677},
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{.fl = 11, .lut = 0x3344556677},
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@ -349,10 +454,18 @@ static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
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{.fl = 0, .lut = 0x112233344556677},
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};
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static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
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{.fl = 0, .lut = 0x0011223344556677},
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};
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static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
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{.fl = 0, .lut = 0x0},
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};
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static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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{.fl = 0, .lut = 0x0},
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};
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static const struct dpu_perf_cfg sdm845_perf_data = {
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.max_bw_low = 6800000,
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.max_bw_high = 6800000,
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@ -392,6 +505,30 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
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},
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};
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static const struct dpu_perf_cfg sc7180_perf_data = {
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.max_bw_low = 3900000,
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.max_bw_high = 5500000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xff, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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};
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/*************************************************************
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* Hardware catalog init
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*************************************************************/
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@ -425,9 +562,39 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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};
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}
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/*
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* sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
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* and instance counts.
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*/
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static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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{
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*dpu_cfg = (struct dpu_mdss_cfg){
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.caps = &sc7180_dpu_caps,
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.mdp_count = ARRAY_SIZE(sc7180_mdp),
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.mdp = sc7180_mdp,
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.ctl_count = ARRAY_SIZE(sc7180_ctl),
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.ctl = sc7180_ctl,
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.sspp_count = ARRAY_SIZE(sc7180_sspp),
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.sspp = sc7180_sspp,
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.mixer_count = ARRAY_SIZE(sc7180_lm),
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.mixer = sc7180_lm,
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.pingpong_count = ARRAY_SIZE(sc7180_pp),
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.pingpong = sc7180_pp,
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.intf_count = ARRAY_SIZE(sc7180_intf),
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.intf = sc7180_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = sdm845_regdma,
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.perf = sc7180_perf_data,
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.mdss_irqs = 0x3f,
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};
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}
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static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
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};
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void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)
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@ -38,6 +38,7 @@
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#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
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#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
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#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
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#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
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#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
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@ -45,6 +46,7 @@
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#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
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#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
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#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
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#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
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#define DPU_HW_BLK_NAME_LEN 16
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@ -110,6 +112,7 @@ enum {
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DPU_SSPP_SRC = 0x1,
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DPU_SSPP_SCALER_QSEED2,
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DPU_SSPP_SCALER_QSEED3,
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DPU_SSPP_SCALER_QSEED4,
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DPU_SSPP_SCALER_RGB,
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DPU_SSPP_CSC,
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DPU_SSPP_CSC_10BIT,
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@ -166,6 +169,7 @@ enum {
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*/
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enum {
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DPU_CTL_SPLIT_DISPLAY = 0x1,
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DPU_CTL_ACTIVE_CFG,
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DPU_CTL_MAX
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};
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@ -152,7 +152,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
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unsigned long features)
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{
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ops->setup_mixer_out = dpu_hw_lm_setup_out;
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if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion))
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if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)
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|| IS_SC7180_TARGET(m->hwversion))
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ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845;
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else
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ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
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@ -1059,6 +1059,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
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static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,sdm845-dpu", },
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{ .compatible = "qcom,sc7180-dpu", },
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{}
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};
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MODULE_DEVICE_TABLE(of, dpu_dt_match);
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@ -1192,7 +1192,8 @@ static int add_display_components(struct device *dev,
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* the interfaces to our components list.
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*/
|
||||
if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
|
||||
of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
|
||||
of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
|
||||
of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
|
||||
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to populate children devices\n");
|
||||
@ -1317,6 +1318,7 @@ static const struct of_device_id dt_match[] = {
|
||||
{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
|
||||
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
|
||||
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
|
||||
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dt_match);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user