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Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6

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This commit is contained in:
Linus Torvalds 2005-09-08 15:55:23 -07:00
commit 7bbedd5213
61 changed files with 1302 additions and 12085 deletions
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9
Documentation/feature-removal-schedule.txt
View File

@ -25,15 +25,6 @@ Who: Pavel Machek <pavel@suse.cz>
---------------------------
What: PCI Name Database (CONFIG_PCI_NAMES)
When: July 2005
Why: It bloats the kernel unnecessarily, and is handled by userspace better
(pciutils supports it.) Will eliminate the need to try to keep the
pci.ids file in sync with the sf.net database all of the time.
Who: Greg Kroah-Hartman <gregkh@suse.de>
---------------------------
What: io_remap_page_range() (macro or function)
When: September 2005
Why: Replaced by io_remap_pfn_range() which allows more memory space

7
MAINTAINERS
View File

@ -1813,13 +1813,6 @@ M: hch@infradead.org
L: linux-abi-devel@lists.sourceforge.net
S: Maintained
PCI ID DATABASE
P: Martin Mares
M: mj@ucw.cz
L: pciids-devel@lists.sourceforge.net
W: http://pciids.sourceforge.net/
S: Maintained
PCI SOUND DRIVERS (ES1370, ES1371 and SONICVIBES)
P: Thomas Sailer
M: sailer@ife.ee.ethz.ch

5
arch/alpha/kernel/sys_marvel.c
View File

@ -373,12 +373,11 @@ marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
irq += 0x80; /* offset for lsi */
#if 1
printk("PCI:%d:%d:%d (hose %d) [%s] is using MSI\n",
printk("PCI:%d:%d:%d (hose %d) is using MSI\n",
dev->bus->number,
PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn),
hose->index,
pci_pretty_name (dev));
hose->index);
printk(" %d message(s) from 0x%04x\n",
1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
msg_dat);

6
arch/i386/pci/i386.c
View File

@ -283,9 +283,9 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
/* Write-combine setting is ignored, it is changed via the mtrr
* interfaces on this platform.
*/
if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
vma->vm_end - vma->vm_start,
vma->vm_page_prot))
if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
vma->vm_end - vma->vm_start,
vma->vm_page_prot))
return -EAGAIN;
return 0;

1
arch/ppc/kernel/pci.c
View File

@ -80,7 +80,6 @@ fixup_broken_pcnet32(struct pci_dev* dev)
if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
dev->vendor = PCI_VENDOR_ID_AMD;
pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
pci_name_device(dev);
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);

31
arch/ppc64/kernel/eeh.c
View File

@ -202,10 +202,9 @@ static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
while (n) {
struct pci_io_addr_range *piar;
piar = rb_entry(n, struct pci_io_addr_range, rb_node);
printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s %s\n",
printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n",
(piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev),
pci_pretty_name(piar->pcidev));
piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
cnt++;
n = rb_next(n);
}
@ -260,8 +259,8 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
dn = pci_device_to_OF_node(dev);
if (!dn) {
printk(KERN_WARNING "PCI: no pci dn found for dev=%s %s\n",
pci_name(dev), pci_pretty_name(dev));
printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n",
pci_name(dev));
return;
}
@ -269,8 +268,8 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
if (!(dn->eeh_mode & EEH_MODE_SUPPORTED) ||
dn->eeh_mode & EEH_MODE_NOCHECK) {
#ifdef DEBUG
printk(KERN_INFO "PCI: skip building address cache for=%s %s\n",
pci_name(dev), pci_pretty_name(dev));
printk(KERN_INFO "PCI: skip building address cache for=%s\n",
pci_name(dev));
#endif
return;
}
@ -447,12 +446,12 @@ static void eeh_panic(struct pci_dev *dev, int reset_state)
* in light of potential corruption, we can use it here.
*/
if (panic_on_oops)
panic("EEH: MMIO failure (%d) on device:%s %s\n", reset_state,
pci_name(dev), pci_pretty_name(dev));
panic("EEH: MMIO failure (%d) on device:%s\n", reset_state,
pci_name(dev));
else {
__get_cpu_var(ignored_failures)++;
printk(KERN_INFO "EEH: Ignored MMIO failure (%d) on device:%s %s\n",
reset_state, pci_name(dev), pci_pretty_name(dev));
printk(KERN_INFO "EEH: Ignored MMIO failure (%d) on device:%s\n",
reset_state, pci_name(dev));
}
}
@ -482,8 +481,8 @@ static void eeh_event_handler(void *dummy)
break;
printk(KERN_INFO "EEH: MMIO failure (%d), notifiying device "
"%s %s\n", event->reset_state,
pci_name(event->dev), pci_pretty_name(event->dev));
"%s\n", event->reset_state,
pci_name(event->dev));
atomic_set(&eeh_fail_count, 0);
notifier_call_chain (&eeh_notifier_chain,
@ -851,8 +850,7 @@ void eeh_add_device_late(struct pci_dev *dev)
return;
#ifdef DEBUG
printk(KERN_DEBUG "EEH: adding device %s %s\n", pci_name(dev),
pci_pretty_name(dev));
printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev));
#endif
pci_addr_cache_insert_device (dev);
@ -873,8 +871,7 @@ void eeh_remove_device(struct pci_dev *dev)
/* Unregister the device with the EEH/PCI address search system */
#ifdef DEBUG
printk(KERN_DEBUG "EEH: remove device %s %s\n", pci_name(dev),
pci_pretty_name(dev));
printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev));
#endif
pci_addr_cache_remove_device(dev);
}

5
arch/ppc64/kernel/iSeries_VpdInfo.c
View File

@ -264,8 +264,5 @@ void __init iSeries_Device_Information(struct pci_dev *PciDev, int count)
printk("%d. PCI: Bus%3d, Device%3d, Vendor %04X Frame%3d, Card %4s ",
count, bus, PCI_SLOT(PciDev->devfn), PciDev->vendor,
frame, card);
if (pci_class_name(PciDev->class >> 8) == 0)
printk("0x%04X\n", (int)(PciDev->class >> 8));
else
printk("%s\n", pci_class_name(PciDev->class >> 8));
printk("0x%04X\n", (int)(PciDev->class >> 8));
}

1
arch/ppc64/kernel/pci.c
View File

@ -84,7 +84,6 @@ static void fixup_broken_pcnet32(struct pci_dev* dev)
if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
dev->vendor = PCI_VENDOR_ID_AMD;
pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
pci_name_device(dev);
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);

127
arch/sparc64/kernel/pci.c
View File

@ -359,134 +359,17 @@ void pcibios_fixup_bus(struct pci_bus *pbus)
pbus->resource[1] = &pbm->mem_space;
}
int pci_claim_resource(struct pci_dev *pdev, int resource)
struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
{
struct pci_pbm_info *pbm = pdev->bus->sysdata;
struct resource *res = &pdev->resource[resource];
struct resource *root;
struct resource *root = NULL;
if (!pbm)
return -EINVAL;
if (res->flags & IORESOURCE_IO)
if (r->flags & IORESOURCE_IO)
root = &pbm->io_space;
else
if (r->flags & IORESOURCE_MEM)
root = &pbm->mem_space;
pbm->parent->resource_adjust(pdev, res, root);
return request_resource(root, res);
}
/*
* Given the PCI bus a device resides on, try to
* find an acceptable resource allocation for a
* specific device resource..
*/
static int pci_assign_bus_resource(const struct pci_bus *bus,
struct pci_dev *dev,
struct resource *res,
unsigned long size,
unsigned long min,
int resno)
{
unsigned int type_mask;
int i;
type_mask = IORESOURCE_IO | IORESOURCE_MEM;
for (i = 0 ; i < 4; i++) {
struct resource *r = bus->resource[i];
if (!r)
continue;
/* type_mask must match */
if ((res->flags ^ r->flags) & type_mask)
continue;
/* Ok, try it out.. */
if (allocate_resource(r, res, size, min, -1, size, NULL, NULL) < 0)
continue;
/* PCI config space updated by caller. */
return 0;
}
return -EBUSY;
}
int pci_assign_resource(struct pci_dev *pdev, int resource)
{
struct pcidev_cookie *pcp = pdev->sysdata;
struct pci_pbm_info *pbm = pcp->pbm;
struct resource *res = &pdev->resource[resource];
unsigned long min, size;
int err;
if (res->flags & IORESOURCE_IO)
min = pbm->io_space.start + 0x400UL;
else
min = pbm->mem_space.start;
size = res->end - res->start + 1;
err = pci_assign_bus_resource(pdev->bus, pdev, res, size, min, resource);
if (err < 0) {
printk("PCI: Failed to allocate resource %d for %s\n",
resource, pci_name(pdev));
} else {
/* Update PCI config space. */
pbm->parent->base_address_update(pdev, resource);
}
return err;
}
/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
int i;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
struct resource *r;
struct resource_list *list, *tmp;
unsigned long r_align;
r = &dev->resource[i];
r_align = r->end - r->start;
if (!(r->flags) || r->parent)
continue;
if (!r_align) {
printk(KERN_WARNING "PCI: Ignore bogus resource %d "
"[%lx:%lx] of %s\n",
i, r->start, r->end, pci_name(dev));
continue;
}
r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
for (list = head; ; list = list->next) {
unsigned long align = 0;
struct resource_list *ln = list->next;
int idx;
if (ln) {
idx = ln->res - &ln->dev->resource[0];
align = (idx < PCI_BRIDGE_RESOURCES) ?
ln->res->end - ln->res->start + 1 :
ln->res->start;
}
if (r_align > align) {
tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
if (!tmp)
panic("pdev_sort_resources(): "
"kmalloc() failed!\n");
tmp->next = ln;
tmp->res = r;
tmp->dev = dev;
list->next = tmp;
break;
}
}
}
return root;
}
void pcibios_update_irq(struct pci_dev *pdev, int irq)

34
arch/sparc64/kernel/pci_psycho.c
View File

@ -307,7 +307,7 @@ static unsigned char psycho_pil_table[] = {
/*0x32*/15, /* Power Management */
};
static int __init psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
static int psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
@ -344,9 +344,9 @@ static int __init psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
return ret;
}
static unsigned int __init psycho_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
struct ino_bucket *bucket;
unsigned long imap, iclr;
@ -1024,7 +1024,7 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *reg
#define PSYCHO_CE_INO 0x2f
#define PSYCHO_PCIERR_A_INO 0x30
#define PSYCHO_PCIERR_B_INO 0x31
static void __init psycho_register_error_handlers(struct pci_controller_info *p)
static void psycho_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
unsigned long base = p->pbm_A.controller_regs;
@ -1091,15 +1091,15 @@ static void __init psycho_register_error_handlers(struct pci_controller_info *p)
}
/* PSYCHO boot time probing and initialization. */
static void __init psycho_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
static void psycho_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
{
res->start += root->start;
res->end += root->start;
}
static void __init psycho_base_address_update(struct pci_dev *pdev, int resource)
static void psycho_base_address_update(struct pci_dev *pdev, int resource)
{
struct pcidev_cookie *pcp = pdev->sysdata;
struct pci_pbm_info *pbm = pcp->pbm;
@ -1144,7 +1144,7 @@ static void __init psycho_base_address_update(struct pci_dev *pdev, int resource
pci_write_config_dword(pdev, where + 4, 0);
}
static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
static void pbm_config_busmastering(struct pci_pbm_info *pbm)
{
u8 *addr;
@ -1161,8 +1161,8 @@ static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
pci_config_write8(addr, 64);
}
static void __init pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
@ -1189,7 +1189,7 @@ static void __init pbm_scan_bus(struct pci_controller_info *p,
pci_setup_busmastering(pbm, pbm->pci_bus);
}
static void __init psycho_scan_bus(struct pci_controller_info *p)
static void psycho_scan_bus(struct pci_controller_info *p)
{
pbm_config_busmastering(&p->pbm_B);
p->pbm_B.is_66mhz_capable = 0;
@ -1204,7 +1204,7 @@ static void __init psycho_scan_bus(struct pci_controller_info *p)
psycho_register_error_handlers(p);
}
static void __init psycho_iommu_init(struct pci_controller_info *p)
static void psycho_iommu_init(struct pci_controller_info *p)
{
struct pci_iommu *iommu = p->pbm_A.iommu;
unsigned long tsbbase, i;
@ -1327,8 +1327,8 @@ static void psycho_controller_hwinit(struct pci_controller_info *p)
psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
}
static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
char *name = pbm->name;
@ -1481,7 +1481,7 @@ static void psycho_pbm_init(struct pci_controller_info *p,
#define PSYCHO_CONFIGSPACE 0x001000000UL
void __init psycho_init(int node, char *model_name)
void psycho_init(int node, char *model_name)
{
struct linux_prom64_registers pr_regs[3];
struct pci_controller_info *p;

36
arch/sparc64/kernel/pci_sabre.c
View File

@ -554,7 +554,7 @@ static unsigned char sabre_pil_table[] = {
/*0x32*/15, /* Power Management */
};
static int __init sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
@ -612,9 +612,9 @@ static void sabre_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_a
sabre_read(sync_reg);
}
static unsigned int __init sabre_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
struct ino_bucket *bucket;
unsigned long imap, iclr;
@ -1009,7 +1009,7 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs
#define SABRE_UE_INO 0x2e
#define SABRE_CE_INO 0x2f
#define SABRE_PCIERR_INO 0x30
static void __init sabre_register_error_handlers(struct pci_controller_info *p)
static void sabre_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
unsigned long base = pbm->controller_regs;
@ -1056,9 +1056,9 @@ static void __init sabre_register_error_handlers(struct pci_controller_info *p)
sabre_write(base + SABRE_PCICTRL, tmp);
}
static void __init sabre_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
static void sabre_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
{
struct pci_pbm_info *pbm = pdev->bus->sysdata;
unsigned long base;
@ -1072,7 +1072,7 @@ static void __init sabre_resource_adjust(struct pci_dev *pdev,
res->end += base;
}
static void __init sabre_base_address_update(struct pci_dev *pdev, int resource)
static void sabre_base_address_update(struct pci_dev *pdev, int resource)
{
struct pcidev_cookie *pcp = pdev->sysdata;
struct pci_pbm_info *pbm = pcp->pbm;
@ -1118,7 +1118,7 @@ static void __init sabre_base_address_update(struct pci_dev *pdev, int resource)
pci_write_config_dword(pdev, where + 4, 0);
}
static void __init apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
{
struct pci_dev *pdev;
@ -1181,7 +1181,7 @@ static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
return cookie;
}
static void __init sabre_scan_bus(struct pci_controller_info *p)
static void sabre_scan_bus(struct pci_controller_info *p)
{
static int once;
struct pci_bus *sabre_bus, *pbus;
@ -1262,9 +1262,9 @@ static void __init sabre_scan_bus(struct pci_controller_info *p)
sabre_register_error_handlers(p);
}
static void __init sabre_iommu_init(struct pci_controller_info *p,
int tsbsize, unsigned long dvma_offset,
u32 dma_mask)
static void sabre_iommu_init(struct pci_controller_info *p,
int tsbsize, unsigned long dvma_offset,
u32 dma_mask)
{
struct pci_iommu *iommu = p->pbm_A.iommu;
unsigned long tsbbase, i, order;
@ -1345,8 +1345,8 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
}
}
static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
char *name = pbm->name;
unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
@ -1415,7 +1415,7 @@ static void __init pbm_register_toplevel_resources(struct pci_controller_info *p
&pbm->mem_space);
}
static void __init sabre_pbm_init(struct pci_controller_info *p, int sabre_node, u32 dma_begin)
static void sabre_pbm_init(struct pci_controller_info *p, int sabre_node, u32 dma_begin)
{
struct pci_pbm_info *pbm;
char namebuf[128];
@ -1552,7 +1552,7 @@ static void __init sabre_pbm_init(struct pci_controller_info *p, int sabre_node,
}
}
void __init sabre_init(int pnode, char *model_name)
void sabre_init(int pnode, char *model_name)
{
struct linux_prom64_registers pr_regs[2];
struct pci_controller_info *p;

48
arch/sparc64/kernel/pci_schizo.c
View File

@ -285,7 +285,7 @@ static unsigned char schizo_pil_table[] = {
/*0x3f*/0, /* Reserved for NewLink */
};
static int __init schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
@ -1221,7 +1221,7 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *
* PCI bus units of the same Tomatillo. I still have not really
* figured this out...
*/
static void __init tomatillo_register_error_handlers(struct pci_controller_info *p)
static void tomatillo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
@ -1359,7 +1359,7 @@ static void __init tomatillo_register_error_handlers(struct pci_controller_info
(SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
}
static void __init schizo_register_error_handlers(struct pci_controller_info *p)
static void schizo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
@ -1505,7 +1505,7 @@ static void __init schizo_register_error_handlers(struct pci_controller_info *p)
(SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
}
static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
static void pbm_config_busmastering(struct pci_pbm_info *pbm)
{
u8 *addr;
@ -1522,8 +1522,8 @@ static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
pci_config_write8(addr, 64);
}
static void __init pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
@ -1550,8 +1550,8 @@ static void __init pbm_scan_bus(struct pci_controller_info *p,
pci_setup_busmastering(pbm, pbm->pci_bus);
}
static void __init __schizo_scan_bus(struct pci_controller_info *p,
int chip_type)
static void __schizo_scan_bus(struct pci_controller_info *p,
int chip_type)
{
if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) {
printk("PCI: Only one PCI bus module of controller found.\n");
@ -1577,17 +1577,17 @@ static void __init __schizo_scan_bus(struct pci_controller_info *p,
schizo_register_error_handlers(p);
}
static void __init schizo_scan_bus(struct pci_controller_info *p)
static void schizo_scan_bus(struct pci_controller_info *p)
{
__schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO);
}
static void __init tomatillo_scan_bus(struct pci_controller_info *p)
static void tomatillo_scan_bus(struct pci_controller_info *p)
{
__schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO);
}
static void __init schizo_base_address_update(struct pci_dev *pdev, int resource)
static void schizo_base_address_update(struct pci_dev *pdev, int resource)
{
struct pcidev_cookie *pcp = pdev->sysdata;
struct pci_pbm_info *pbm = pcp->pbm;
@ -1632,9 +1632,9 @@ static void __init schizo_base_address_update(struct pci_dev *pdev, int resource
pci_write_config_dword(pdev, where + 4, 0);
}
static void __init schizo_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
static void schizo_resource_adjust(struct pci_dev *pdev,
struct resource *res,
struct resource *root)
{
res->start += root->start;
res->end += root->start;
@ -1702,8 +1702,8 @@ static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm)
pbm->mem_space.start);
}
static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pbm_register_toplevel_resources(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
{
pbm->io_space.name = pbm->mem_space.name = pbm->name;
@ -1932,7 +1932,7 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
static void __init schizo_pbm_hw_init(struct pci_pbm_info *pbm)
static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
{
u64 tmp;
@ -1986,9 +1986,9 @@ static void __init schizo_pbm_hw_init(struct pci_pbm_info *pbm)
}
}
static void __init schizo_pbm_init(struct pci_controller_info *p,
int prom_node, u32 portid,
int chip_type)
static void schizo_pbm_init(struct pci_controller_info *p,
int prom_node, u32 portid,
int chip_type)
{
struct linux_prom64_registers pr_regs[4];
unsigned int busrange[2];
@ -2145,7 +2145,7 @@ static inline int portid_compare(u32 x, u32 y, int chip_type)
return (x == y);
}
static void __init __schizo_init(int node, char *model_name, int chip_type)
static void __schizo_init(int node, char *model_name, int chip_type)
{
struct pci_controller_info *p;
struct pci_iommu *iommu;
@ -2213,17 +2213,17 @@ static void __init __schizo_init(int node, char *model_name, int chip_type)
schizo_pbm_init(p, node, portid, chip_type);
}
void __init schizo_init(int node, char *model_name)
void schizo_init(int node, char *model_name)
{
__schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO);
}
void __init schizo_plus_init(int node, char *model_name)
void schizo_plus_init(int node, char *model_name)
{
__schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
}
void __init tomatillo_init(int node, char *model_name)
void tomatillo_init(int node, char *model_name)
{
__schizo_init(node, model_name, PBM_CHIP_TYPE_TOMATILLO);
}

4
drivers/char/drm/drmP.h
View File

@ -1071,5 +1071,9 @@ extern void *drm_calloc(size_t nmemb, size_t size, int area);
extern unsigned long drm_core_get_map_ofs(drm_map_t *map);
extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
#ifndef pci_pretty_name
#define pci_pretty_name(dev) ""
#endif
#endif /* __KERNEL__ */
#endif

8
drivers/infiniband/hw/mthca/mthca_main.c
View File

@ -937,12 +937,12 @@ static int __devinit mthca_init_one(struct pci_dev *pdev,
++mthca_version_printed;
}
printk(KERN_INFO PFX "Initializing %s (%s)\n",
pci_pretty_name(pdev), pci_name(pdev));
printk(KERN_INFO PFX "Initializing %s\n",
pci_name(pdev));
if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
printk(KERN_ERR PFX "%s (%s) has invalid driver data %lx\n",
pci_pretty_name(pdev), pci_name(pdev), id->driver_data);
printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
pci_name(pdev), id->driver_data);
return -ENODEV;
}

8
drivers/infiniband/hw/mthca/mthca_reset.c
View File

@ -71,8 +71,8 @@ int mthca_reset(struct mthca_dev *mdev)
bridge)) != NULL) {
if (bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
bridge->subordinate == mdev->pdev->bus) {
mthca_dbg(mdev, "Found bridge: %s (%s)\n",
pci_pretty_name(bridge), pci_name(bridge));
mthca_dbg(mdev, "Found bridge: %s\n",
pci_name(bridge));
break;
}
}
@ -83,8 +83,8 @@ int mthca_reset(struct mthca_dev *mdev)
* assume we're in no-bridge mode and hope for
* the best.
*/
mthca_warn(mdev, "No bridge found for %s (%s)\n",
pci_pretty_name(mdev->pdev), pci_name(mdev->pdev));
mthca_warn(mdev, "No bridge found for %s\n",
pci_name(mdev->pdev));
}
}

6
drivers/net/irda/vlsi_ir.h
View File

@ -69,14 +69,8 @@ typedef void irqreturn_t;
#else /* 2.5 or later */
/* recent 2.5/2.6 stores pci device names at varying places ;-) */
#ifdef CONFIG_PCI_NAMES
/* human readable name */
#define PCIDEV_NAME(pdev) ((pdev)->pretty_name)
#else
/* whatever we get from the associated struct device - bus:slot:dev.fn id */
#define PCIDEV_NAME(pdev) (pci_name(pdev))
#endif
#endif

2
drivers/parport/parport_pc.c
View File

@ -3010,7 +3010,7 @@ static int __init parport_pc_init_superio (int autoirq, int autodma)
struct pci_dev *pdev = NULL;
int ret = 0;
while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
for_each_pci_dev(pdev) {
id = pci_match_id(parport_pc_pci_tbl, pdev);
if (id == NULL || id->driver_data >= last_sio)
continue;

17
drivers/pci/Kconfig
View File

@ -30,23 +30,6 @@ config PCI_LEGACY_PROC
When in doubt, say N.
config PCI_NAMES
bool "PCI device name database"
depends on PCI
---help---
By default, the kernel contains a database of all known PCI device
names to make the information in /proc/pci, /proc/ioports and
similar files comprehensible to the user.
This database increases size of the kernel image by about 80KB. This
memory is freed after the system boots up if CONFIG_HOTPLUG is not set.
Anyway, if you are building an installation floppy or kernel for an
embedded system where kernel image size really matters, you can disable
this feature and you'll get device ID numbers instead of names.
When in doubt, say Y.
config PCI_DEBUG
bool "PCI Debugging"
depends on PCI && DEBUG_KERNEL

22
drivers/pci/Makefile
View File

@ -3,14 +3,9 @@
#
obj-y += access.o bus.o probe.o remove.o pci.o quirks.o \
names.o pci-driver.o search.o pci-sysfs.o \
rom.o
pci-driver.o search.o pci-sysfs.o rom.o setup-res.o
obj-$(CONFIG_PROC_FS) += proc.o
ifndef CONFIG_SPARC64
obj-y += setup-res.o
endif
obj-$(CONFIG_HOTPLUG) += hotplug.o
# Build the PCI Hotplug drivers if we were asked to
@ -46,21 +41,6 @@ ifeq ($(CONFIG_PCI_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
hostprogs-y := gen-devlist
# Dependencies on generated files need to be listed explicitly
$(obj)/names.o: $(obj)/devlist.h $(obj)/classlist.h
$(obj)/classlist.h: $(obj)/devlist.h
# And that's how to generate them
quiet_cmd_devlist = DEVLIST $@
cmd_devlist = ( cd $(obj); ./gen-devlist ) < $<
$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
$(call cmd,devlist)
# Files generated that shall be removed upon make clean
clean-files := devlist.h classlist.h
# Build PCI Express stuff if needed
obj-$(CONFIG_PCIEPORTBUS) += pcie/

51
drivers/pci/bus.c
View File

@ -140,16 +140,65 @@ void __devinit pci_bus_add_devices(struct pci_bus *bus)
void pci_enable_bridges(struct pci_bus *bus)
{
struct pci_dev *dev;
int retval;
list_for_each_entry(dev, &bus->devices, bus_list) {
if (dev->subordinate) {
pci_enable_device(dev);
retval = pci_enable_device(dev);
pci_set_master(dev);
pci_enable_bridges(dev->subordinate);
}
}
}
/** pci_walk_bus - walk devices on/under bus, calling callback.
* @top bus whose devices should be walked
* @cb callback to be called for each device found
* @userdata arbitrary pointer to be passed to callback.
*
* Walk the given bus, including any bridged devices
* on buses under this bus. Call the provided callback
* on each device found.
*/
void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
void *userdata)
{
struct pci_dev *dev;
struct pci_bus *bus;
struct list_head *next;
bus = top;
spin_lock(&pci_bus_lock);
next = top->devices.next;
for (;;) {
if (next == &bus->devices) {
/* end of this bus, go up or finish */
if (bus == top)
break;
next = bus->self->bus_list.next;
bus = bus->self->bus;
continue;
}
dev = list_entry(next, struct pci_dev, bus_list);
pci_dev_get(dev);
if (dev->subordinate) {
/* this is a pci-pci bridge, do its devices next */
next = dev->subordinate->devices.next;
bus = dev->subordinate;
} else
next = dev->bus_list.next;
spin_unlock(&pci_bus_lock);
/* Run device routines with the bus unlocked */
cb(dev, userdata);
spin_lock(&pci_bus_lock);
pci_dev_put(dev);
}
spin_unlock(&pci_bus_lock);
}
EXPORT_SYMBOL_GPL(pci_walk_bus);
EXPORT_SYMBOL(pci_bus_alloc_resource);
EXPORT_SYMBOL_GPL(pci_bus_add_device);
EXPORT_SYMBOL(pci_bus_add_devices);

132
drivers/pci/gen-devlist.c
View File

@ -1,132 +0,0 @@
/*
* Generate devlist.h and classlist.h from the PCI ID file.
*
* (c) 1999--2002 Martin Mares <mj@ucw.cz>
*/
#include <stdio.h>
#include <string.h>
#define MAX_NAME_SIZE 200
static void
pq(FILE *f, const char *c, int len)
{
int i = 1;
while (*c && i != len) {
if (*c == '"')
fprintf(f, "\\\"");
else {
fputc(*c, f);
if (*c == '?' && c[1] == '?') {
/* Avoid trigraphs */
fprintf(f, "\" \"");
}
}
c++;
i++;
}
}
int
main(void)
{
char line[1024], *c, *bra, vend[8];
int vendors = 0;
int mode = 0;
int lino = 0;
int vendor_len = 0;
FILE *devf, *clsf;
devf = fopen("devlist.h", "w");
clsf = fopen("classlist.h", "w");
if (!devf || !clsf) {
fprintf(stderr, "Cannot create output file!\n");
return 1;
}
while (fgets(line, sizeof(line)-1, stdin)) {
lino++;
if ((c = strchr(line, '\n')))
*c = 0;
if (!line[0] || line[0] == '#')
continue;
if (line[1] == ' ') {
if (line[0] == 'C' && strlen(line) > 4 && line[4] == ' ') {
vend[0] = line[2];
vend[1] = line[3];
vend[2] = 0;
mode = 2;
} else goto err;
}
else if (line[0] == '\t') {
if (line[1] == '\t')
continue;
switch (mode) {
case 1:
if (strlen(line) > 5 && line[5] == ' ') {
c = line + 5;
while (*c == ' ')
*c++ = 0;
if (vendor_len + strlen(c) + 1 > MAX_NAME_SIZE) {
/* Too long, try cutting off long description */
bra = strchr(c, '[');
if (bra && bra > c && bra[-1] == ' ')
bra[-1] = 0;
if (vendor_len + strlen(c) + 1 > MAX_NAME_SIZE) {
fprintf(stderr, "Line %d: Device name too long. Name truncated.\n", lino);
fprintf(stderr, "%s\n", c);
/*return 1;*/
}
}
fprintf(devf, "\tDEVICE(%s,%s,\"", vend, line+1);
pq(devf, c, MAX_NAME_SIZE - vendor_len - 1);
fputs("\")\n", devf);
} else goto err;
break;
case 2:
if (strlen(line) > 3 && line[3] == ' ') {
c = line + 3;
while (*c == ' ')
*c++ = 0;
fprintf(clsf, "CLASS(%s%s, \"%s\")\n", vend, line+1, c);
} else goto err;
break;
default:
goto err;
}
} else if (strlen(line) > 4 && line[4] == ' ') {
c = line + 4;
while (*c == ' ')
*c++ = 0;
if (vendors)
fputs("ENDVENDOR()\n\n", devf);
vendors++;
strcpy(vend, line);
vendor_len = strlen(c);
if (vendor_len + 24 > MAX_NAME_SIZE) {
fprintf(stderr, "Line %d: Vendor name too long\n", lino);
return 1;
}
fprintf(devf, "VENDOR(%s,\"", vend);
pq(devf, c, 0);
fputs("\")\n", devf);
mode = 1;
} else {
err:
fprintf(stderr, "Line %d: Syntax error in mode %d: %s\n", lino, mode, line);
return 1;
}
}
fputs("ENDVENDOR()\n\
\n\
#undef VENDOR\n\
#undef DEVICE\n\
#undef ENDVENDOR\n", devf);
fputs("\n#undef CLASS\n", clsf);
fclose(devf);
fclose(clsf);
return 0;
}

3
drivers/pci/hotplug/Makefile
View File

@ -41,8 +41,7 @@ acpiphp-objs := acpiphp_core.o \
rpaphp-objs := rpaphp_core.o \
rpaphp_pci.o \
rpaphp_slot.o \
rpaphp_vio.o
rpaphp_slot.o
rpadlpar_io-objs := rpadlpar_core.o \
rpadlpar_sysfs.o

2
drivers/pci/hotplug/pciehp.h
View File

@ -302,7 +302,7 @@ static inline void return_resource(struct pci_resource **head, struct pci_resour
static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
{
snprintf(buffer, buffer_size, "%d", slot->number);
snprintf(buffer, buffer_size, "%04d_%04d", slot->bus, slot->number);
}
enum php_ctlr_type {

293
drivers/pci/hotplug/rpadlpar_core.c
View File

@ -19,33 +19,36 @@
#include <asm/pci-bridge.h>
#include <asm/semaphore.h>
#include <asm/rtas.h>
#include <asm/vio.h>
#include "../pci.h"
#include "rpaphp.h"
#include "rpadlpar.h"
static DECLARE_MUTEX(rpadlpar_sem);
#define DLPAR_MODULE_NAME "rpadlpar_io"
#define NODE_TYPE_VIO 1
#define NODE_TYPE_SLOT 2
#define NODE_TYPE_PHB 3
static struct device_node *find_php_slot_vio_node(char *drc_name)
static struct device_node *find_vio_slot_node(char *drc_name)
{
struct device_node *child;
struct device_node *parent = of_find_node_by_name(NULL, "vdevice");
char *loc_code;
struct device_node *dn = NULL;
char *name;
int rc;
if (!parent)
return NULL;
for (child = of_get_next_child(parent, NULL);
child; child = of_get_next_child(parent, child)) {
loc_code = get_property(child, "ibm,loc-code", NULL);
if (loc_code && !strncmp(loc_code, drc_name, strlen(drc_name)))
return child;
while ((dn = of_get_next_child(parent, dn))) {
rc = rpaphp_get_drc_props(dn, NULL, &name, NULL, NULL);
if ((rc == 0) && (!strcmp(drc_name, name)))
break;
}
return NULL;
return dn;
}
/* Find dlpar-capable pci node that contains the specified name and type */
@ -67,7 +70,7 @@ static struct device_node *find_php_slot_pci_node(char *drc_name,
return np;
}
static struct device_node *find_newly_added_node(char *drc_name, int *node_type)
static struct device_node *find_dlpar_node(char *drc_name, int *node_type)
{
struct device_node *dn;
@ -83,7 +86,7 @@ static struct device_node *find_newly_added_node(char *drc_name, int *node_type)
return dn;
}
dn = find_php_slot_vio_node(drc_name);
dn = find_vio_slot_node(drc_name);
if (dn) {
*node_type = NODE_TYPE_VIO;
return dn;
@ -92,14 +95,14 @@ static struct device_node *find_newly_added_node(char *drc_name, int *node_type)
return NULL;
}
static struct slot *find_slot(char *drc_name)
static struct slot *find_slot(struct device_node *dn)
{
struct list_head *tmp, *n;
struct slot *slot;
list_for_each_safe(tmp, n, &rpaphp_slot_head) {
slot = list_entry(tmp, struct slot, rpaphp_slot_list);
if (strcmp(slot->location, drc_name) == 0)
if (slot->dn == dn)
return slot;
}
@ -164,6 +167,20 @@ static int pci_add_secondary_bus(struct device_node *dn,
return 0;
}
static struct pci_dev *dlpar_find_new_dev(struct pci_bus *parent,
struct device_node *dev_dn)
{
struct pci_dev *tmp = NULL;
struct device_node *child_dn;
list_for_each_entry(tmp, &parent->devices, bus_list) {
child_dn = pci_device_to_OF_node(tmp);
if (child_dn == dev_dn)
return tmp;
}
return NULL;
}
static struct pci_dev *dlpar_pci_add_bus(struct device_node *dn)
{
struct pci_controller *hose = dn->phb;
@ -179,49 +196,28 @@ static struct pci_dev *dlpar_pci_add_bus(struct device_node *dn)
pci_bus_add_devices(hose->bus);
/* Confirm new bridge dev was created */
dev = rpaphp_find_pci_dev(dn);
if (!dev) {
printk(KERN_ERR "%s: failed to add pci device\n", __FUNCTION__);
return NULL;
}
dev = dlpar_find_new_dev(hose->bus, dn);
if (dev) {
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
printk(KERN_ERR "%s: unexpected header type %d\n",
__FUNCTION__, dev->hdr_type);
return NULL;
}
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
printk(KERN_ERR "%s: unexpected header type %d\n",
__FUNCTION__, dev->hdr_type);
return NULL;
if (pci_add_secondary_bus(dn, dev))
return NULL;
}
if (pci_add_secondary_bus(dn, dev))
return NULL;
return dev;
}
static int dlpar_pci_remove_bus(struct pci_dev *bridge_dev)
{
struct pci_bus *secondary_bus;
if (!bridge_dev) {
printk(KERN_ERR "%s: unexpected null device\n",
__FUNCTION__);
return -EINVAL;
}
secondary_bus = bridge_dev->subordinate;
if (unmap_bus_range(secondary_bus)) {
printk(KERN_ERR "%s: failed to unmap bus range\n",
__FUNCTION__);
return -ERANGE;
}
pci_remove_bus_device(bridge_dev);
return 0;
}
static inline int dlpar_add_pci_slot(char *drc_name, struct device_node *dn)
static int dlpar_add_pci_slot(char *drc_name, struct device_node *dn)
{
struct pci_dev *dev;
int rc;
if (rpaphp_find_pci_bus(dn))
return -EINVAL;
/* Add pci bus */
dev = dlpar_pci_add_bus(dn);
@ -231,6 +227,21 @@ static inline int dlpar_add_pci_slot(char *drc_name, struct device_node *dn)
return -EIO;
}
if (dn->child) {
rc = rpaphp_config_pci_adapter(dev->subordinate);
if (rc < 0) {
printk(KERN_ERR "%s: unable to enable slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
}
/* Add hotplug slot */
if (rpaphp_add_slot(dn)) {
printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
return 0;
}
@ -255,47 +266,67 @@ static int dlpar_remove_root_bus(struct pci_controller *phb)
return 0;
}
static int dlpar_remove_phb(struct slot *slot)
static int dlpar_remove_phb(char *drc_name, struct device_node *dn)
{
struct pci_controller *phb;
struct device_node *dn;
struct slot *slot;
int rc = 0;
dn = slot->dn;
if (!dn) {
printk(KERN_ERR "%s: unexpected NULL slot device node\n",
__FUNCTION__);
return -EIO;
if (!rpaphp_find_pci_bus(dn))
return -EINVAL;
slot = find_slot(dn);
if (slot) {
/* Remove hotplug slot */
if (rpaphp_remove_slot(slot)) {
printk(KERN_ERR
"%s: unable to remove hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
}
phb = dn->phb;
if (!phb) {
printk(KERN_ERR "%s: unexpected NULL phb pointer\n",
__FUNCTION__);
return -EIO;
}
if (rpaphp_remove_slot(slot)) {
printk(KERN_ERR "%s: unable to remove hotplug slot %s\n",
__FUNCTION__, slot->location);
return -EIO;
}
rc = dlpar_remove_root_bus(phb);
BUG_ON(!dn->phb);
rc = dlpar_remove_root_bus(dn->phb);
if (rc < 0)
return rc;
dn->phb = NULL;
return 0;
}
static int dlpar_add_phb(struct device_node *dn)
static int dlpar_add_phb(char *drc_name, struct device_node *dn)
{
struct pci_controller *phb;
if (dn->phb) {
/* PHB already exists */
return -EINVAL;
}
phb = init_phb_dynamic(dn);
if (!phb)
return -EIO;
if (rpaphp_add_slot(dn)) {
printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
return 0;
}
static int dlpar_add_vio_slot(char *drc_name, struct device_node *dn)
{
if (vio_find_node(dn))
return -EINVAL;
if (!vio_register_device_node(dn)) {
printk(KERN_ERR
"%s: failed to register vio node %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
return 0;
}
@ -316,18 +347,13 @@ int dlpar_add_slot(char *drc_name)
{
struct device_node *dn = NULL;
int node_type;
int rc = 0;
int rc = -EIO;
if (down_interruptible(&rpadlpar_sem))
return -ERESTARTSYS;
/* Check for existing hotplug slot */
if (find_slot(drc_name)) {
rc = -EINVAL;
goto exit;
}
dn = find_newly_added_node(drc_name, &node_type);
/* Find newly added node */
dn = find_dlpar_node(drc_name, &node_type);
if (!dn) {
rc = -ENODEV;
goto exit;
@ -335,24 +361,17 @@ int dlpar_add_slot(char *drc_name)
switch (node_type) {
case NODE_TYPE_VIO:
/* Just add hotplug slot */
rc = dlpar_add_vio_slot(drc_name, dn);
break;
case NODE_TYPE_SLOT:
rc = dlpar_add_pci_slot(drc_name, dn);
break;
case NODE_TYPE_PHB:
rc = dlpar_add_phb(dn);
rc = dlpar_add_phb(drc_name, dn);
break;
default:
printk("%s: unexpected node type\n", __FUNCTION__);
return -EIO;
}
if (!rc && rpaphp_add_slot(dn)) {
printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
__FUNCTION__, drc_name);
rc = -EIO;
}
printk(KERN_INFO "%s: slot %s added\n", DLPAR_MODULE_NAME, drc_name);
exit:
up(&rpadlpar_sem);
return rc;
@ -366,17 +385,17 @@ exit:
* of an I/O Slot.
* Return Codes:
* 0 Success
* -EIO Internal Error
* -EINVAL Vio dev doesn't exist
*/
int dlpar_remove_vio_slot(struct slot *slot, char *drc_name)
static int dlpar_remove_vio_slot(char *drc_name, struct device_node *dn)
{
/* Remove hotplug slot */
struct vio_dev *vio_dev;
if (rpaphp_remove_slot(slot)) {
printk(KERN_ERR "%s: unable to remove hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
vio_dev = vio_find_node(dn);
if (!vio_dev)
return -EINVAL;
vio_unregister_device(vio_dev);
return 0;
}
@ -391,31 +410,34 @@ int dlpar_remove_vio_slot(struct slot *slot, char *drc_name)
* -ENODEV Not a valid drc_name
* -EIO Internal PCI Error
*/
int dlpar_remove_pci_slot(struct slot *slot, char *drc_name)
int dlpar_remove_pci_slot(char *drc_name, struct device_node *dn)
{
struct pci_dev *bridge_dev;
struct pci_bus *bus;
struct slot *slot;
bridge_dev = slot->bridge;
if (!bridge_dev) {
printk(KERN_ERR "%s: unexpected null bridge device\n",
bus = rpaphp_find_pci_bus(dn);
if (!bus)
return -EINVAL;
slot = find_slot(dn);
if (slot) {
/* Remove hotplug slot */
if (rpaphp_remove_slot(slot)) {
printk(KERN_ERR
"%s: unable to remove hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
}
if (unmap_bus_range(bus)) {
printk(KERN_ERR "%s: failed to unmap bus range\n",
__FUNCTION__);
return -EIO;
return -ERANGE;
}
/* Remove hotplug slot */
if (rpaphp_remove_slot(slot)) {
printk(KERN_ERR "%s: unable to remove hotplug slot %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
/* Remove pci bus */
if (dlpar_pci_remove_bus(bridge_dev)) {
printk(KERN_ERR "%s: unable to remove pci bus %s\n",
__FUNCTION__, drc_name);
return -EIO;
}
BUG_ON(!bus->self);
pci_remove_bus_device(bus->self);
return 0;
}
@ -434,38 +456,31 @@ int dlpar_remove_pci_slot(struct slot *slot, char *drc_name)
*/
int dlpar_remove_slot(char *drc_name)
{
struct slot *slot;
struct device_node *dn;
int node_type;
int rc = 0;
if (down_interruptible(&rpadlpar_sem))
return -ERESTARTSYS;
if (!find_php_slot_vio_node(drc_name) &&
!find_php_slot_pci_node(drc_name, "SLOT") &&
!find_php_slot_pci_node(drc_name, "PHB")) {
dn = find_dlpar_node(drc_name, &node_type);
if (!dn) {
rc = -ENODEV;
goto exit;
}
slot = find_slot(drc_name);
if (!slot) {
rc = -EINVAL;
goto exit;
}
if (slot->type == PHB) {
rc = dlpar_remove_phb(slot);
} else {
switch (slot->dev_type) {
case PCI_DEV:
rc = dlpar_remove_pci_slot(slot, drc_name);
break;
case VIO_DEV:
rc = dlpar_remove_vio_slot(slot, drc_name);
break;
}
switch (node_type) {
case NODE_TYPE_VIO:
rc = dlpar_remove_vio_slot(drc_name, dn);
break;
case NODE_TYPE_PHB:
rc = dlpar_remove_phb(drc_name, dn);
break;
case NODE_TYPE_SLOT:
rc = dlpar_remove_pci_slot(drc_name, dn);
break;
}
printk(KERN_INFO "%s: slot %s removed\n", DLPAR_MODULE_NAME, drc_name);
exit:
up(&rpadlpar_sem);
return rc;

35
drivers/pci/hotplug/rpaphp.h
View File

@ -30,10 +30,6 @@
#include <linux/pci.h>
#include "pci_hotplug.h"
#define PHB 2
#define HOTPLUG 1
#define EMBEDDED 0
#define DR_INDICATOR 9002
#define DR_ENTITY_SENSE 9003
@ -61,10 +57,6 @@ extern int debug;
#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
/* slot types */
#define VIO_DEV 1
#define PCI_DEV 2
/* slot states */
#define NOT_VALID 3
@ -72,11 +64,6 @@ extern int debug;
#define CONFIGURED 1
#define EMPTY 0
struct rpaphp_pci_func {
struct pci_dev *pci_dev;
struct list_head sibling;
};
/*
* struct slot - slot information for each *physical* slot
*/
@ -88,15 +75,9 @@ struct slot {
u32 power_domain;
char *name;
char *location;
u8 removable;
u8 dev_type; /* VIO or PCI */
struct device_node *dn; /* slot's device_node in OFDT */
/* dn has phb info */
struct pci_dev *bridge; /* slot's pci_dev in pci_devices */
union {
struct list_head *pci_devs; /* pci_devs in PCI slot */
struct vio_dev *vio_dev; /* vio_dev in VIO slot */
} dev;
struct device_node *dn;
struct pci_bus *bus;
struct list_head *pci_devs;
struct hotplug_slot *hotplug_slot;
};
@ -107,13 +88,13 @@ extern int num_slots;
/* function prototypes */
/* rpaphp_pci.c */
extern struct pci_dev *rpaphp_find_pci_dev(struct device_node *dn);
extern struct pci_bus *rpaphp_find_pci_bus(struct device_node *dn);
extern int rpaphp_claim_resource(struct pci_dev *dev, int resource);
extern int rpaphp_enable_pci_slot(struct slot *slot);
extern int register_pci_slot(struct slot *slot);
extern int rpaphp_unconfig_pci_adapter(struct slot *slot);
extern int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value);
extern struct hotplug_slot *rpaphp_find_hotplug_slot(struct pci_dev *dev);
extern int rpaphp_config_pci_adapter(struct pci_bus *bus);
/* rpaphp_core.c */
extern int rpaphp_add_slot(struct device_node *dn);
@ -121,12 +102,6 @@ extern int rpaphp_remove_slot(struct slot *slot);
extern int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
char **drc_name, char **drc_type, int *drc_power_domain);
/* rpaphp_vio.c */
extern int rpaphp_get_vio_adapter_status(struct slot *slot, int is_init, u8 * value);
extern int rpaphp_unconfig_vio_adapter(struct slot *slot);
extern int register_vio_slot(struct device_node *dn);
extern int rpaphp_enable_vio_slot(struct slot *slot);
/* rpaphp_slot.c */
extern void dealloc_slot_struct(struct slot *slot);
extern struct slot *alloc_slot_struct(struct device_node *dn, int drc_index, char *drc_name, int power_domain);

146
drivers/pci/hotplug/rpaphp_core.c
View File

@ -152,17 +152,7 @@ static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 * value)
int retval = 0;
down(&rpaphp_sem);
/* have to go through this */
switch (slot->dev_type) {
case PCI_DEV:
retval = rpaphp_get_pci_adapter_status(slot, 0, value);
break;
case VIO_DEV:
retval = rpaphp_get_vio_adapter_status(slot, 0, value);
break;
default:
retval = -EINVAL;
}
retval = rpaphp_get_pci_adapter_status(slot, 0, value);
up(&rpaphp_sem);
return retval;
}
@ -317,34 +307,6 @@ static int is_php_dn(struct device_node *dn, int **indexes, int **names,
return 0;
}
static int is_dr_dn(struct device_node *dn, int **indexes, int **names,
int **types, int **power_domains, int **my_drc_index)
{
int rc;
*my_drc_index = (int *) get_property(dn, "ibm,my-drc-index", NULL);
if(!*my_drc_index)
return (0);
if (!dn->parent)
return (0);
rc = get_children_props(dn->parent, indexes, names, types,
power_domains);
return (rc >= 0);
}
static inline int is_vdevice_root(struct device_node *dn)
{
return !strcmp(dn->name, "vdevice");
}
int is_dlpar_type(const char *type_str)
{
/* Only register DLPAR-capable nodes of drc-type PHB or SLOT */
return (!strcmp(type_str, "PHB") || !strcmp(type_str, "SLOT"));
}
/****************************************************************
* rpaphp not only registers PCI hotplug slots(HOTPLUG),
* but also logical DR slots(EMBEDDED).
@ -356,54 +318,33 @@ int rpaphp_add_slot(struct device_node *dn)
{
struct slot *slot;
int retval = 0;
int i, *my_drc_index, slot_type;
int i;
int *indexes, *names, *types, *power_domains;
char *name, *type;
dbg("Entry %s: dn->full_name=%s\n", __FUNCTION__, dn->full_name);
if (dn->parent && is_vdevice_root(dn->parent)) {
/* register a VIO device */
retval = register_vio_slot(dn);
goto exit;
}
/* register PCI devices */
if (dn->name != 0 && strcmp(dn->name, "pci") == 0) {
if (is_php_dn(dn, &indexes, &names, &types, &power_domains))
slot_type = HOTPLUG;
else if (is_dr_dn(dn, &indexes, &names, &types, &power_domains, &my_drc_index))
slot_type = EMBEDDED;
else goto exit;
if (!is_php_dn(dn, &indexes, &names, &types, &power_domains))
goto exit;
name = (char *) &names[1];
type = (char *) &types[1];
for (i = 0; i < indexes[0]; i++,
name += (strlen(name) + 1), type += (strlen(type) + 1)) {
name += (strlen(name) + 1), type += (strlen(type) + 1)) {
if (slot_type == HOTPLUG ||
(slot_type == EMBEDDED &&
indexes[i + 1] == my_drc_index[0] &&
is_dlpar_type(type))) {
if (!(slot = alloc_slot_struct(dn, indexes[i + 1], name,
power_domains[i + 1]))) {
retval = -ENOMEM;
goto exit;
}
if (!strcmp(type, "PHB"))
slot->type = PHB;
else if (slot_type == EMBEDDED)
slot->type = EMBEDDED;
else
slot->type = simple_strtoul(type, NULL, 10);
if (!(slot = alloc_slot_struct(dn, indexes[i + 1], name,
power_domains[i + 1]))) {
retval = -ENOMEM;
goto exit;
}
slot->type = simple_strtoul(type, NULL, 10);
dbg(" Found drc-index:0x%x drc-name:%s drc-type:%s\n",
dbg("Found drc-index:0x%x drc-name:%s drc-type:%s\n",
indexes[i + 1], name, type);
retval = register_pci_slot(slot);
if (slot_type == EMBEDDED)
goto exit;
}
retval = register_pci_slot(slot);
}
}
exit:
@ -412,31 +353,6 @@ exit:
return retval;
}
/*
* init_slots - initialize 'struct slot' structures for each slot
*
*/
static void init_slots(void)
{
struct device_node *dn;
for (dn = find_all_nodes(); dn; dn = dn->next)
rpaphp_add_slot(dn);
}
static int __init init_rpa(void)
{
init_MUTEX(&rpaphp_sem);
/* initialize internal data structure etc. */
init_slots();
if (!num_slots)
return -ENODEV;
return 0;
}
static void __exit cleanup_slots(void)
{
struct list_head *tmp, *n;
@ -458,10 +374,18 @@ static void __exit cleanup_slots(void)
static int __init rpaphp_init(void)
{
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
struct device_node *dn = NULL;
/* read all the PRA info from the system */
return init_rpa();
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
init_MUTEX(&rpaphp_sem);
while ((dn = of_find_node_by_type(dn, "pci")))
rpaphp_add_slot(dn);
if (!num_slots)
return -ENODEV;
return 0;
}
static void __exit rpaphp_exit(void)
@ -481,16 +405,7 @@ static int enable_slot(struct hotplug_slot *hotplug_slot)
dbg("ENABLING SLOT %s\n", slot->name);
down(&rpaphp_sem);
switch (slot->dev_type) {
case PCI_DEV:
retval = rpaphp_enable_pci_slot(slot);
break;
case VIO_DEV:
retval = rpaphp_enable_vio_slot(slot);
break;
default:
retval = -EINVAL;
}
retval = rpaphp_enable_pci_slot(slot);
up(&rpaphp_sem);
exit:
dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);
@ -511,16 +426,7 @@ static int disable_slot(struct hotplug_slot *hotplug_slot)
dbg("DISABLING SLOT %s\n", slot->name);
down(&rpaphp_sem);
switch (slot->dev_type) {
case PCI_DEV:
retval = rpaphp_unconfig_pci_adapter(slot);
break;
case VIO_DEV:
retval = rpaphp_unconfig_vio_adapter(slot);
break;
default:
retval = -ENODEV;
}
retval = rpaphp_unconfig_pci_adapter(slot);
up(&rpaphp_sem);
exit:
dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);

297
drivers/pci/hotplug/rpaphp_pci.c
View File

@ -30,22 +30,33 @@
#include "rpaphp.h"
struct pci_dev *rpaphp_find_pci_dev(struct device_node *dn)
static struct pci_bus *find_bus_among_children(struct pci_bus *bus,
struct device_node *dn)
{
struct pci_dev *dev = NULL;
char bus_id[BUS_ID_SIZE];
struct pci_bus *child = NULL;
struct list_head *tmp;
struct device_node *busdn;
sprintf(bus_id, "%04x:%02x:%02x.%d", dn->phb->global_number,
dn->busno, PCI_SLOT(dn->devfn), PCI_FUNC(dn->devfn));
for_each_pci_dev(dev) {
if (!strcmp(pci_name(dev), bus_id)) {
busdn = pci_bus_to_OF_node(bus);
if (busdn == dn)
return bus;
list_for_each(tmp, &bus->children) {
child = find_bus_among_children(pci_bus_b(tmp), dn);
if (child)
break;
}
}
return dev;
return child;
}
EXPORT_SYMBOL_GPL(rpaphp_find_pci_dev);
struct pci_bus *rpaphp_find_pci_bus(struct device_node *dn)
{
if (!dn->phb || !dn->phb->bus)
return NULL;
return find_bus_among_children(dn->phb->bus, dn);
}
EXPORT_SYMBOL_GPL(rpaphp_find_pci_bus);
int rpaphp_claim_resource(struct pci_dev *dev, int resource)
{
@ -69,11 +80,6 @@ int rpaphp_claim_resource(struct pci_dev *dev, int resource)
EXPORT_SYMBOL_GPL(rpaphp_claim_resource);
static struct pci_dev *rpaphp_find_bridge_pdev(struct slot *slot)
{
return rpaphp_find_pci_dev(slot->dn);
}
static int rpaphp_get_sensor_state(struct slot *slot, int *state)
{
int rc;
@ -116,39 +122,27 @@ static int rpaphp_get_sensor_state(struct slot *slot, int *state)
*/
int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value)
{
struct pci_bus *bus;
int state, rc;
struct device_node *child_dn;
struct pci_dev *child_dev = NULL;
*value = NOT_VALID;
rc = rpaphp_get_sensor_state(slot, &state);
if (rc)
goto exit;
if ((state == EMPTY) || (slot->type == PHB)) {
dbg("slot is empty\n");
if (state == EMPTY)
*value = EMPTY;
}
else if (state == PRESENT) {
if (!is_init) {
/* at run-time slot->state can be changed by */
/* config/unconfig adapter */
*value = slot->state;
} else {
child_dn = slot->dn->child;
if (child_dn)
child_dev = rpaphp_find_pci_dev(child_dn);
if (child_dev)
*value = CONFIGURED;
else if (!child_dn)
dbg("%s: %s is not valid OFDT node\n",
__FUNCTION__, slot->dn->full_name);
else {
err("%s: can't find pdev of adapter in slot[%s]\n",
__FUNCTION__, slot->dn->full_name);
bus = rpaphp_find_pci_bus(slot->dn);
if (bus && !list_empty(&bus->devices))
*value = CONFIGURED;
else
*value = NOT_CONFIGURED;
}
}
}
exit:
@ -186,39 +180,6 @@ rpaphp_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
}
}
static int rpaphp_pci_config_bridge(struct pci_dev *dev);
/*****************************************************************************
rpaphp_pci_config_slot() will configure all devices under the
given slot->dn and return the the first pci_dev.
*****************************************************************************/
static struct pci_dev *
rpaphp_pci_config_slot(struct device_node *dn, struct pci_bus *bus)
{
struct device_node *eads_first_child = dn->child;
struct pci_dev *dev = NULL;
int num;
dbg("Enter %s: dn=%s bus=%s\n", __FUNCTION__, dn->full_name, bus->name);
if (eads_first_child) {
/* pci_scan_slot should find all children of EADs */
num = pci_scan_slot(bus, PCI_DEVFN(PCI_SLOT(eads_first_child->devfn), 0));
if (num) {
rpaphp_fixup_new_pci_devices(bus, 1);
pci_bus_add_devices(bus);
}
dev = rpaphp_find_pci_dev(eads_first_child);
if (!dev) {
err("No new device found\n");
return NULL;
}
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
rpaphp_pci_config_bridge(dev);
}
return dev;
}
static int rpaphp_pci_config_bridge(struct pci_dev *dev)
{
u8 sec_busno;
@ -252,6 +213,42 @@ static int rpaphp_pci_config_bridge(struct pci_dev *dev)
return 0;
}
/*****************************************************************************
rpaphp_pci_config_slot() will configure all devices under the
given slot->dn and return the the first pci_dev.
*****************************************************************************/
static struct pci_dev *
rpaphp_pci_config_slot(struct pci_bus *bus)
{
struct device_node *dn = pci_bus_to_OF_node(bus);
struct pci_dev *dev = NULL;
int slotno;
int num;
dbg("Enter %s: dn=%s bus=%s\n", __FUNCTION__, dn->full_name, bus->name);
if (!dn || !dn->child)
return NULL;
slotno = PCI_SLOT(dn->child->devfn);
/* pci_scan_slot should find all children */
num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
if (num) {
rpaphp_fixup_new_pci_devices(bus, 1);
pci_bus_add_devices(bus);
}
if (list_empty(&bus->devices)) {
err("%s: No new device found\n", __FUNCTION__);
return NULL;
}
list_for_each_entry(dev, &bus->devices, bus_list) {
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
rpaphp_pci_config_bridge(dev);
}
return dev;
}
static void enable_eeh(struct device_node *dn)
{
struct device_node *sib;
@ -263,49 +260,44 @@ static void enable_eeh(struct device_node *dn)
}
static void print_slot_pci_funcs(struct slot *slot)
static void print_slot_pci_funcs(struct pci_bus *bus)
{
struct device_node *dn;
struct pci_dev *dev;
if (slot->dev_type == PCI_DEV) {
dbg("%s: pci_devs of slot[%s]\n", __FUNCTION__, slot->name);
list_for_each_entry (dev, slot->dev.pci_devs, bus_list)
dbg("\t%s\n", pci_name(dev));
}
dn = pci_bus_to_OF_node(bus);
if (!dn)
return;
dbg("%s: pci_devs of slot[%s]\n", __FUNCTION__, dn->full_name);
list_for_each_entry (dev, &bus->devices, bus_list)
dbg("\t%s\n", pci_name(dev));
return;
}
static int rpaphp_config_pci_adapter(struct slot *slot)
int rpaphp_config_pci_adapter(struct pci_bus *bus)
{
struct pci_bus *pci_bus;
struct device_node *dn = pci_bus_to_OF_node(bus);
struct pci_dev *dev;
int rc = -ENODEV;
dbg("Entry %s: slot[%s]\n", __FUNCTION__, slot->name);
dbg("Entry %s: slot[%s]\n", __FUNCTION__, dn->full_name);
if (!dn)
goto exit;
if (slot->bridge) {
pci_bus = slot->bridge->subordinate;
if (!pci_bus) {
err("%s: can't find bus structure\n", __FUNCTION__);
goto exit;
}
enable_eeh(slot->dn);
dev = rpaphp_pci_config_slot(slot->dn, pci_bus);
if (!dev) {
err("%s: can't find any devices.\n", __FUNCTION__);
goto exit;
}
print_slot_pci_funcs(slot);
rc = 0;
} else {
/* slot is not enabled */
err("slot doesn't have pci_dev structure\n");
enable_eeh(dn);
dev = rpaphp_pci_config_slot(bus);
if (!dev) {
err("%s: can't find any devices.\n", __FUNCTION__);
goto exit;
}
print_slot_pci_funcs(bus);
rc = 0;
exit:
dbg("Exit %s: rc=%d\n", __FUNCTION__, rc);
return rc;
}
EXPORT_SYMBOL_GPL(rpaphp_config_pci_adapter);
static void rpaphp_eeh_remove_bus_device(struct pci_dev *dev)
{
@ -327,13 +319,14 @@ static void rpaphp_eeh_remove_bus_device(struct pci_dev *dev)
int rpaphp_unconfig_pci_adapter(struct slot *slot)
{
struct pci_dev *dev;
struct pci_dev *dev, *tmp;
int retval = 0;
list_for_each_entry(dev, slot->dev.pci_devs, bus_list)
list_for_each_entry_safe(dev, tmp, slot->pci_devs, bus_list) {
rpaphp_eeh_remove_bus_device(dev);
pci_remove_bus_device(dev);
}
pci_remove_behind_bridge(slot->bridge);
slot->state = NOT_CONFIGURED;
info("%s: devices in slot[%s] unconfigured.\n", __FUNCTION__,
slot->name);
@ -356,66 +349,41 @@ static int setup_pci_hotplug_slot_info(struct slot *slot)
return 0;
}
static int set_phb_slot_name(struct slot *slot)
static void set_slot_name(struct slot *slot)
{
struct device_node *dn;
struct pci_controller *phb;
struct pci_bus *bus;
struct pci_bus *bus = slot->bus;
struct pci_dev *bridge;
dn = slot->dn;
if (!dn) {
return -EINVAL;
}
phb = dn->phb;
if (!phb) {
return -EINVAL;
}
bus = phb->bus;
if (!bus) {
return -EINVAL;
}
sprintf(slot->name, "%04x:%02x:%02x.%x", pci_domain_nr(bus),
bus->number, 0, 0);
return 0;
bridge = bus->self;
if (bridge)
strcpy(slot->name, pci_name(bridge));
else
sprintf(slot->name, "%04x:%02x:00.0", pci_domain_nr(bus),
bus->number);
}
static int setup_pci_slot(struct slot *slot)
{
struct device_node *dn = slot->dn;
struct pci_bus *bus;
int rc;
if (slot->type == PHB) {
rc = set_phb_slot_name(slot);
if (rc < 0) {
err("%s: failed to set phb slot name\n", __FUNCTION__);
goto exit_rc;
}
} else {
slot->bridge = rpaphp_find_bridge_pdev(slot);
if (!slot->bridge) {
/* slot being added doesn't have pci_dev yet */
err("%s: no pci_dev for bridge dn %s\n",
__FUNCTION__, slot->name);
goto exit_rc;
}
bus = slot->bridge->subordinate;
if (!bus)
goto exit_rc;
slot->dev.pci_devs = &bus->devices;
dbg("%s set slot->name to %s\n", __FUNCTION__,
pci_name(slot->bridge));
strcpy(slot->name, pci_name(slot->bridge));
BUG_ON(!dn);
bus = rpaphp_find_pci_bus(dn);
if (!bus) {
err("%s: no pci_bus for dn %s\n", __FUNCTION__, dn->full_name);
goto exit_rc;
}
slot->bus = bus;
slot->pci_devs = &bus->devices;
set_slot_name(slot);
/* find slot's pci_dev if it's not empty */
if (slot->hotplug_slot->info->adapter_status == EMPTY) {
slot->state = EMPTY; /* slot is empty */
} else {
/* slot is occupied */
if (!(slot->dn->child)) {
if (!dn->child) {
/* non-empty slot has to have child */
err("%s: slot[%s]'s device_node doesn't have child for adapter\n",
__FUNCTION__, slot->name);
@ -425,7 +393,7 @@ static int setup_pci_slot(struct slot *slot)
if (slot->hotplug_slot->info->adapter_status == NOT_CONFIGURED) {
dbg("%s CONFIGURING pci adapter in slot[%s]\n",
__FUNCTION__, slot->name);
if (rpaphp_config_pci_adapter(slot)) {
if (rpaphp_config_pci_adapter(slot->bus)) {
err("%s: CONFIG pci adapter failed\n", __FUNCTION__);
goto exit_rc;
}
@ -435,8 +403,8 @@ static int setup_pci_slot(struct slot *slot)
__FUNCTION__, slot->name);
goto exit_rc;
}
print_slot_pci_funcs(slot);
if (!list_empty(slot->dev.pci_devs)) {
print_slot_pci_funcs(slot->bus);
if (!list_empty(slot->pci_devs)) {
slot->state = CONFIGURED;
} else {
/* DLPAR add as opposed to
@ -454,11 +422,6 @@ int register_pci_slot(struct slot *slot)
{
int rc = -EINVAL;
slot->dev_type = PCI_DEV;
if ((slot->type == EMBEDDED) || (slot->type == PHB))
slot->removable = 0;
else
slot->removable = 1;
if (setup_pci_hotplug_slot_info(slot))
goto exit_rc;
if (setup_pci_slot(slot))
@ -479,7 +442,7 @@ int rpaphp_enable_pci_slot(struct slot *slot)
/* if slot is not empty, enable the adapter */
if (state == PRESENT) {
dbg("%s : slot[%s] is occupied.\n", __FUNCTION__, slot->name);
retval = rpaphp_config_pci_adapter(slot);
retval = rpaphp_config_pci_adapter(slot->bus);
if (!retval) {
slot->state = CONFIGURED;
dbg("%s: PCI devices in slot[%s] has been configured\n",
@ -502,37 +465,3 @@ exit:
dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);
return retval;
}
struct hotplug_slot *rpaphp_find_hotplug_slot(struct pci_dev *dev)
{
struct list_head *tmp, *n;
struct slot *slot;
list_for_each_safe(tmp, n, &rpaphp_slot_head) {
struct pci_bus *bus;
struct list_head *ln;
slot = list_entry(tmp, struct slot, rpaphp_slot_list);
if (slot->bridge == NULL) {
if (slot->dev_type == PCI_DEV) {
printk(KERN_WARNING "PCI slot missing bridge %s %s \n",
slot->name, slot->location);
}
continue;
}
bus = slot->bridge->subordinate;
if (!bus) {
continue; /* should never happen? */
}
for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
struct pci_dev *pdev = pci_dev_b(ln);
if (pdev == dev)
return slot->hotplug_slot;
}
}
return NULL;
}
EXPORT_SYMBOL_GPL(rpaphp_find_hotplug_slot);

66
drivers/pci/hotplug/rpaphp_slot.c
View File

@ -30,35 +30,6 @@
#include <asm/rtas.h>
#include "rpaphp.h"
static ssize_t removable_read_file (struct hotplug_slot *php_slot, char *buf)
{
u8 value;
int retval = -ENOENT;
struct slot *slot = (struct slot *)php_slot->private;
if (!slot)
return retval;
value = slot->removable;
retval = sprintf (buf, "%d\n", value);
return retval;
}
static struct hotplug_slot_attribute hotplug_slot_attr_removable = {
.attr = {.name = "phy_removable", .mode = S_IFREG | S_IRUGO},
.show = removable_read_file,
};
static void rpaphp_sysfs_add_attr_removable (struct hotplug_slot *slot)
{
sysfs_create_file(&slot->kobj, &hotplug_slot_attr_removable.attr);
}
static void rpaphp_sysfs_remove_attr_removable (struct hotplug_slot *slot)
{
sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_removable.attr);
}
static ssize_t location_read_file (struct hotplug_slot *php_slot, char *buf)
{
char *value;
@ -176,9 +147,6 @@ int deregister_slot(struct slot *slot)
/* remove "phy_location" file */
rpaphp_sysfs_remove_attr_location(php_slot);
/* remove "phy_removable" file */
rpaphp_sysfs_remove_attr_removable(php_slot);
retval = pci_hp_deregister(php_slot);
if (retval)
err("Problem unregistering a slot %s\n", slot->name);
@ -212,21 +180,13 @@ int register_slot(struct slot *slot)
/* create "phy_locatoin" file */
rpaphp_sysfs_add_attr_location(slot->hotplug_slot);
/* create "phy_removable" file */
rpaphp_sysfs_add_attr_removable(slot->hotplug_slot);
/* add slot to our internal list */
dbg("%s adding slot[%s] to rpaphp_slot_list\n",
__FUNCTION__, slot->name);
list_add(&slot->rpaphp_slot_list, &rpaphp_slot_head);
if (slot->dev_type == VIO_DEV)
info("Slot [%s](VIO location=%s) registered\n",
slot->name, slot->location);
else
info("Slot [%s](PCI location=%s) registered\n",
slot->name, slot->location);
info("Slot [%s](PCI location=%s) registered\n", slot->name,
slot->location);
num_slots++;
return 0;
}
@ -235,21 +195,17 @@ int rpaphp_get_power_status(struct slot *slot, u8 * value)
{
int rc = 0, level;
if (slot->type == HOTPLUG) {
rc = rtas_get_power_level(slot->power_domain, &level);
if (!rc) {
dbg("%s the power level of slot %s(pwd-domain:0x%x) is %d\n",
__FUNCTION__, slot->name, slot->power_domain, level);
*value = level;
} else
err("failed to get power-level for slot(%s), rc=0x%x\n",
slot->location, rc);
} else {
dbg("%s report POWER_ON for EMBEDDED or PHB slot %s\n",
__FUNCTION__, slot->location);
*value = (u8) POWER_ON;
rc = rtas_get_power_level(slot->power_domain, &level);
if (rc < 0) {
err("failed to get power-level for slot(%s), rc=0x%x\n",
slot->location, rc);
return rc;
}
dbg("%s the power level of slot %s(pwd-domain:0x%x) is %d\n",
__FUNCTION__, slot->name, slot->power_domain, level);
*value = level;
return rc;
}

129
drivers/pci/hotplug/rpaphp_vio.c
View File

@ -1,129 +0,0 @@
/*
* RPA Hot Plug Virtual I/O device functions
* Copyright (C) 2004 Linda Xie <lxie@us.ibm.com>
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Send feedback to <lxie@us.ibm.com>
*
*/
#include <asm/vio.h>
#include "rpaphp.h"
/*
* get_vio_adapter_status - get the status of a slot
*
* status:
*
* 1-- adapter is configured
* 2-- adapter is not configured
* 3-- not valid
*/
inline int rpaphp_get_vio_adapter_status(struct slot *slot, int is_init, u8 *value)
{
*value = slot->state;
return 0;
}
int rpaphp_unconfig_vio_adapter(struct slot *slot)
{
int retval = 0;
dbg("Entry %s: slot[%s]\n", __FUNCTION__, slot->name);
if (!slot->dev.vio_dev) {
info("%s: no VIOA in slot[%s]\n", __FUNCTION__, slot->name);
retval = -EINVAL;
goto exit;
}
/* remove the device from the vio core */
vio_unregister_device(slot->dev.vio_dev);
slot->state = NOT_CONFIGURED;
info("%s: adapter in slot[%s] unconfigured.\n", __FUNCTION__, slot->name);
exit:
dbg("Exit %s, rc=0x%x\n", __FUNCTION__, retval);
return retval;
}
static int setup_vio_hotplug_slot_info(struct slot *slot)
{
slot->hotplug_slot->info->power_status = 1;
rpaphp_get_vio_adapter_status(slot, 1,
&slot->hotplug_slot->info->adapter_status);
return 0;
}
int register_vio_slot(struct device_node *dn)
{
u32 *index;
char *name;
int rc = -EINVAL;
struct slot *slot = NULL;
rc = rpaphp_get_drc_props(dn, NULL, &name, NULL, NULL);
if (rc < 0)
goto exit_rc;
index = (u32 *) get_property(dn, "ibm,my-drc-index", NULL);
if (!index)
goto exit_rc;
if (!(slot = alloc_slot_struct(dn, *index, name, 0))) {
rc = -ENOMEM;
goto exit_rc;
}
slot->dev_type = VIO_DEV;
slot->dev.vio_dev = vio_find_node(dn);
if (slot->dev.vio_dev) {
/*
* rpaphp is the only owner of vio devices and
* does not need extra reference taken by
* vio_find_node
*/
put_device(&slot->dev.vio_dev->dev);
} else
slot->dev.vio_dev = vio_register_device_node(dn);
if (slot->dev.vio_dev)
slot->state = CONFIGURED;
else
slot->state = NOT_CONFIGURED;
if (setup_vio_hotplug_slot_info(slot))
goto exit_rc;
strcpy(slot->name, slot->dev.vio_dev->dev.bus_id);
info("%s: registered VIO device[name=%s vio_dev=%p]\n",
__FUNCTION__, slot->name, slot->dev.vio_dev);
rc = register_slot(slot);
exit_rc:
if (rc && slot)
dealloc_slot_struct(slot);
return (rc);
}
int rpaphp_enable_vio_slot(struct slot *slot)
{
int retval = 0;
if ((slot->dev.vio_dev = vio_register_device_node(slot->dn))) {
info("%s: VIO adapter %s in slot[%s] has been configured\n",
__FUNCTION__, slot->dn->name, slot->name);
slot->state = CONFIGURED;
} else {
info("%s: no vio_dev struct for adapter in slot[%s]\n",
__FUNCTION__, slot->name);
slot->state = NOT_CONFIGURED;
}
return retval;
}

195
drivers/pci/hotplug/sgi_hotplug.c
View File

@ -32,14 +32,15 @@ MODULE_LICENSE("GPL");
MODULE_AUTHOR("SGI (prarit@sgi.com, dickie@sgi.com, habeck@sgi.com)");
MODULE_DESCRIPTION("SGI Altix Hot Plug PCI Controller Driver");
#define PCIIO_ASIC_TYPE_TIOCA 4
#define PCI_SLOT_ALREADY_UP 2 /* slot already up */
#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */
#define PCI_L1_ERR 7 /* L1 console command error */
#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */
#define PCI_L1_QSIZE 128 /* our L1 message buffer size */
#define SN_MAX_HP_SLOTS 32 /* max number of hotplug slots */
#define SGI_HOTPLUG_PROM_REV 0x0420 /* Min. required PROM version */
#define PCIIO_ASIC_TYPE_TIOCA 4
#define PCI_SLOT_ALREADY_UP 2 /* slot already up */
#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */
#define PCI_L1_ERR 7 /* L1 console command error */
#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */
#define PCI_L1_QSIZE 128 /* our L1 message buffer size */
#define SN_MAX_HP_SLOTS 32 /* max hotplug slots */
#define SGI_HOTPLUG_PROM_REV 0x0430 /* Min. required PROM version */
#define SN_SLOT_NAME_SIZE 33 /* size of name string */
/* internal list head */
static struct list_head sn_hp_list;
@ -51,6 +52,7 @@ struct slot {
/* this struct for glue internal only */
struct hotplug_slot *hotplug_slot;
struct list_head hp_list;
char physical_path[SN_SLOT_NAME_SIZE];
};
struct pcibr_slot_enable_resp {
@ -70,7 +72,7 @@ enum sn_pci_req_e {
static int enable_slot(struct hotplug_slot *slot);
static int disable_slot(struct hotplug_slot *slot);
static int get_power_status(struct hotplug_slot *slot, u8 *value);
static inline int get_power_status(struct hotplug_slot *slot, u8 *value);
static struct hotplug_slot_ops sn_hotplug_slot_ops = {
.owner = THIS_MODULE,
@ -81,6 +83,21 @@ static struct hotplug_slot_ops sn_hotplug_slot_ops = {
static DECLARE_MUTEX(sn_hotplug_sem);
static ssize_t path_show (struct hotplug_slot *bss_hotplug_slot,
char *buf)
{
int retval = -ENOENT;
struct slot *slot = bss_hotplug_slot->private;
if (!slot)
return retval;
retval = sprintf (buf, "%s\n", slot->physical_path);
return retval;
}
static struct hotplug_slot_attribute sn_slot_path_attr = __ATTR_RO(path);
static int sn_pci_slot_valid(struct pci_bus *pci_bus, int device)
{
struct pcibus_info *pcibus_info;
@ -120,15 +137,15 @@ static int sn_pci_bus_valid(struct pci_bus *pci_bus)
/* Only register slots in I/O Bricks that support hotplug */
bricktype = MODULE_GET_BTYPE(pcibus_info->pbi_moduleid);
switch (bricktype) {
case L1_BRICKTYPE_IX:
case L1_BRICKTYPE_PX:
case L1_BRICKTYPE_IA:
case L1_BRICKTYPE_PA:
return 1;
break;
default:
return -EPERM;
break;
case L1_BRICKTYPE_IX:
case L1_BRICKTYPE_PX:
case L1_BRICKTYPE_IA:
case L1_BRICKTYPE_PA:
return 1;
break;
default:
return -EPERM;
break;
}
return -EIO;
@ -142,13 +159,12 @@ static int sn_hp_slot_private_alloc(struct hotplug_slot *bss_hotplug_slot,
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(pci_bus);
bss_hotplug_slot->private = kcalloc(1, sizeof(struct slot),
GFP_KERNEL);
if (!bss_hotplug_slot->private)
slot = kcalloc(1, sizeof(*slot), GFP_KERNEL);
if (!slot)
return -ENOMEM;
slot = (struct slot *)bss_hotplug_slot->private;
bss_hotplug_slot->private = slot;
bss_hotplug_slot->name = kmalloc(33, GFP_KERNEL);
bss_hotplug_slot->name = kmalloc(SN_SLOT_NAME_SIZE, GFP_KERNEL);
if (!bss_hotplug_slot->name) {
kfree(bss_hotplug_slot->private);
return -ENOMEM;
@ -156,16 +172,16 @@ static int sn_hp_slot_private_alloc(struct hotplug_slot *bss_hotplug_slot,
slot->device_num = device;
slot->pci_bus = pci_bus;
sprintf(bss_hotplug_slot->name, "module_%c%c%c%c%.2d_b_%d_s_%d",
sprintf(bss_hotplug_slot->name, "%04x:%02x:%02x",
pci_domain_nr(pci_bus),
((int)pcibus_info->pbi_buscommon.bs_persist_busnum) & 0xf,
device + 1);
sprintf(slot->physical_path, "module_%c%c%c%c%.2d",
'0'+RACK_GET_CLASS(MODULE_GET_RACK(pcibus_info->pbi_moduleid)),
'0'+RACK_GET_GROUP(MODULE_GET_RACK(pcibus_info->pbi_moduleid)),
'0'+RACK_GET_NUM(MODULE_GET_RACK(pcibus_info->pbi_moduleid)),
MODULE_GET_BTCHAR(pcibus_info->pbi_moduleid),
MODULE_GET_BPOS(pcibus_info->pbi_moduleid),
((int)pcibus_info->pbi_buscommon.bs_persist_busnum) & 0xf,
device + 1);
MODULE_GET_BPOS(pcibus_info->pbi_moduleid));
slot->hotplug_slot = bss_hotplug_slot;
list_add(&slot->hp_list, &sn_hp_list);
@ -175,14 +191,14 @@ static int sn_hp_slot_private_alloc(struct hotplug_slot *bss_hotplug_slot,
static struct hotplug_slot * sn_hp_destroy(void)
{
struct slot *slot;
struct list_head *list;
struct hotplug_slot *bss_hotplug_slot = NULL;
list_for_each(list, &sn_hp_list) {
slot = list_entry(list, struct slot, hp_list);
list_for_each_entry(slot, &sn_hp_list, hp_list) {
bss_hotplug_slot = slot->hotplug_slot;
list_del(&((struct slot *)bss_hotplug_slot->private)->
hp_list);
sysfs_remove_file(&bss_hotplug_slot->kobj,
&sn_slot_path_attr.attr);
break;
}
return bss_hotplug_slot;
@ -190,7 +206,6 @@ static struct hotplug_slot * sn_hp_destroy(void)
static void sn_bus_alloc_data(struct pci_dev *dev)
{
struct list_head *node;
struct pci_bus *subordinate_bus;
struct pci_dev *child;
@ -199,66 +214,29 @@ static void sn_bus_alloc_data(struct pci_dev *dev)
/* Recursively sets up the sn_irq_info structs */
if (dev->subordinate) {
subordinate_bus = dev->subordinate;
list_for_each(node, &subordinate_bus->devices) {
child = list_entry(node, struct pci_dev, bus_list);
list_for_each_entry(child, &subordinate_bus->devices, bus_list)
sn_bus_alloc_data(child);
}
}
}
static void sn_bus_free_data(struct pci_dev *dev)
{
struct list_head *node;
struct pci_bus *subordinate_bus;
struct pci_dev *child;
/* Recursively clean up sn_irq_info structs */
if (dev->subordinate) {
subordinate_bus = dev->subordinate;
list_for_each(node, &subordinate_bus->devices) {
child = list_entry(node, struct pci_dev, bus_list);
list_for_each_entry(child, &subordinate_bus->devices, bus_list)
sn_bus_free_data(child);
}
}
sn_pci_unfixup_slot(dev);
}
static u8 sn_power_status_get(struct hotplug_slot *bss_hotplug_slot)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
u8 retval;
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
retval = pcibus_info->pbi_enabled_devices & (1 << slot->device_num);
return retval ? 1 : 0;
}
static void sn_slot_mark_enable(struct hotplug_slot *bss_hotplug_slot,
int device_num)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
pcibus_info->pbi_enabled_devices |= (1 << device_num);
}
static void sn_slot_mark_disable(struct hotplug_slot *bss_hotplug_slot,
int device_num)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
pcibus_info->pbi_enabled_devices &= ~(1 << device_num);
}
static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
int device_num)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct slot *slot = bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
struct pcibr_slot_enable_resp resp;
int rc;
@ -273,7 +251,7 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
if (rc == PCI_SLOT_ALREADY_UP) {
dev_dbg(slot->pci_bus->self, "is already active\n");
return -EPERM;
return 1; /* return 1 to user */
}
if (rc == PCI_L1_ERR) {
@ -290,7 +268,8 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
return -EIO;
}
sn_slot_mark_enable(bss_hotplug_slot, device_num);
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
pcibus_info->pbi_enabled_devices |= (1 << device_num);
return 0;
}
@ -298,7 +277,7 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
int device_num, int action)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct slot *slot = bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
struct pcibr_slot_disable_resp resp;
int rc;
@ -307,43 +286,44 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
rc = sal_pcibr_slot_disable(pcibus_info, device_num, action, &resp);
if (action == PCI_REQ_SLOT_ELIGIBLE && rc == PCI_SLOT_ALREADY_DOWN) {
if ((action == PCI_REQ_SLOT_ELIGIBLE) &&
(rc == PCI_SLOT_ALREADY_DOWN)) {
dev_dbg(slot->pci_bus->self, "Slot %s already inactive\n");
return -ENODEV;
return 1; /* return 1 to user */
}
if (action == PCI_REQ_SLOT_ELIGIBLE && rc == PCI_EMPTY_33MHZ) {
if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_EMPTY_33MHZ)) {
dev_dbg(slot->pci_bus->self,
"Cannot remove last 33MHz card\n");
return -EPERM;
}
if (action == PCI_REQ_SLOT_ELIGIBLE && rc == PCI_L1_ERR) {
if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_L1_ERR)) {
dev_dbg(slot->pci_bus->self,
"L1 failure %d with message \n%s\n",
resp.resp_sub_errno, resp.resp_l1_msg);
return -EPERM;
}
if (action == PCI_REQ_SLOT_ELIGIBLE && rc) {
if ((action == PCI_REQ_SLOT_ELIGIBLE) && rc) {
dev_dbg(slot->pci_bus->self,
"remove failed with error %d sub-error %d\n",
rc, resp.resp_sub_errno);
return -EIO;
}
if (action == PCI_REQ_SLOT_ELIGIBLE && !rc)
if ((action == PCI_REQ_SLOT_ELIGIBLE) && !rc)
return 0;
if (action == PCI_REQ_SLOT_DISABLE && !rc) {
sn_slot_mark_disable(bss_hotplug_slot, device_num);
if ((action == PCI_REQ_SLOT_DISABLE) && !rc) {
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
pcibus_info->pbi_enabled_devices &= ~(1 << device_num);
dev_dbg(slot->pci_bus->self, "remove successful\n");
return 0;
}
if (action == PCI_REQ_SLOT_DISABLE && rc) {
if ((action == PCI_REQ_SLOT_DISABLE) && rc) {
dev_dbg(slot->pci_bus->self,"remove failed rc = %d\n", rc);
return rc;
}
return rc;
@ -351,7 +331,7 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct slot *slot = bss_hotplug_slot->private;
struct pci_bus *new_bus = NULL;
struct pci_dev *dev;
int func, num_funcs;
@ -371,8 +351,8 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
return rc;
}
num_funcs = pci_scan_slot(slot->pci_bus, PCI_DEVFN(slot->device_num+1,
PCI_FUNC(0)));
num_funcs = pci_scan_slot(slot->pci_bus,
PCI_DEVFN(slot->device_num + 1, 0));
if (!num_funcs) {
dev_dbg(slot->pci_bus->self, "no device in slot\n");
up(&sn_hotplug_sem);
@ -391,8 +371,6 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
dev = pci_get_slot(slot->pci_bus,
PCI_DEVFN(slot->device_num + 1,
PCI_FUNC(func)));
if (dev) {
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
unsigned char sec_bus;
@ -431,7 +409,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
static int disable_slot(struct hotplug_slot *bss_hotplug_slot)
{
struct slot *slot = (struct slot *)bss_hotplug_slot->private;
struct slot *slot = bss_hotplug_slot->private;
struct pci_dev *dev;
int func;
int rc;
@ -448,7 +426,7 @@ static int disable_slot(struct hotplug_slot *bss_hotplug_slot)
/* Free the SN resources assigned to the Linux device.*/
for (func = 0; func < 8; func++) {
dev = pci_get_slot(slot->pci_bus,
PCI_DEVFN(slot->device_num+1,
PCI_DEVFN(slot->device_num + 1,
PCI_FUNC(func)));
if (dev) {
/*
@ -477,10 +455,15 @@ static int disable_slot(struct hotplug_slot *bss_hotplug_slot)
return rc;
}
static int get_power_status(struct hotplug_slot *bss_hotplug_slot, u8 *value)
static inline int get_power_status(struct hotplug_slot *bss_hotplug_slot,
u8 *value)
{
struct slot *slot = bss_hotplug_slot->private;
struct pcibus_info *pcibus_info;
pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
down(&sn_hotplug_sem);
*value = sn_power_status_get(bss_hotplug_slot);
*value = pcibus_info->pbi_enabled_devices & (1 << slot->device_num);
up(&sn_hotplug_sem);
return 0;
}
@ -508,7 +491,7 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus)
if (sn_pci_slot_valid(pci_bus, device) != 1)
continue;
bss_hotplug_slot = kcalloc(1,sizeof(struct hotplug_slot),
bss_hotplug_slot = kcalloc(1, sizeof(*bss_hotplug_slot),
GFP_KERNEL);
if (!bss_hotplug_slot) {
rc = -ENOMEM;
@ -516,7 +499,7 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus)
}
bss_hotplug_slot->info =
kcalloc(1,sizeof(struct hotplug_slot_info),
kcalloc(1, sizeof(struct hotplug_slot_info),
GFP_KERNEL);
if (!bss_hotplug_slot->info) {
rc = -ENOMEM;
@ -535,6 +518,11 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus)
rc = pci_hp_register(bss_hotplug_slot);
if (rc)
goto register_err;
rc = sysfs_create_file(&bss_hotplug_slot->kobj,
&sn_slot_path_attr.attr);
if (rc)
goto register_err;
}
dev_dbg(pci_bus->self, "Registered bus with hotplug\n");
return rc;
@ -564,14 +552,14 @@ static int sn_pci_hotplug_init(void)
int rc;
int registered = 0;
INIT_LIST_HEAD(&sn_hp_list);
if (sn_sal_rev() < SGI_HOTPLUG_PROM_REV) {
printk(KERN_ERR "%s: PROM version must be greater than 4.05\n",
printk(KERN_ERR "%s: PROM version must be greater than 4.30\n",
__FUNCTION__);
return -EPERM;
}
INIT_LIST_HEAD(&sn_hp_list);
while ((pci_bus = pci_find_next_bus(pci_bus))) {
if (!pci_bus->sysdata)
continue;
@ -584,9 +572,9 @@ static int sn_pci_hotplug_init(void)
dev_dbg(pci_bus->self, "valid hotplug bus\n");
rc = sn_hotplug_slot_register(pci_bus);
if (!rc)
if (!rc) {
registered = 1;
else {
} else {
registered = 0;
break;
}
@ -599,9 +587,8 @@ static void sn_pci_hotplug_exit(void)
{
struct hotplug_slot *bss_hotplug_slot;
while ((bss_hotplug_slot = sn_hp_destroy())) {
while ((bss_hotplug_slot = sn_hp_destroy()))
pci_hp_deregister(bss_hotplug_slot);
}
if (!list_empty(&sn_hp_list))
printk(KERN_ERR "%s: internal list is not empty\n", __FILE__);

2
drivers/pci/hotplug/shpchp.h
View File

@ -411,7 +411,7 @@ static inline void return_resource(struct pci_resource **head, struct pci_resour
static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
{
snprintf(buffer, buffer_size, "%d", slot->number);
snprintf(buffer, buffer_size, "%04d_%04d", slot->bus, slot->number);
}
enum php_ctlr_type {

10
drivers/pci/msi.c
View File

@ -439,10 +439,7 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
}
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */
u16 cmd;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(dev, PCI_COMMAND, cmd);
pci_intx(dev, 0); /* disable intx */
}
}
@ -461,10 +458,7 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type)
}
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */
u16 cmd;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd &= ~PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(dev, PCI_COMMAND, cmd);
pci_intx(dev, 1); /* enable intx */
}
}

137
drivers/pci/names.c
View File

@ -1,137 +0,0 @@
/*
* PCI Class and Device Name Tables
*
* Copyright 1993--1999 Drew Eckhardt, Frederic Potter,
* David Mosberger-Tang, Martin Mares
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#ifdef CONFIG_PCI_NAMES
struct pci_device_info {
unsigned short device;
unsigned short seen;
const char *name;
};
struct pci_vendor_info {
unsigned short vendor;
unsigned short nr;
const char *name;
struct pci_device_info *devices;
};
/*
* This is ridiculous, but we want the strings in
* the .init section so that they don't take up
* real memory.. Parse the same file multiple times
* to get all the info.
*/
#define VENDOR( vendor, name ) static char __vendorstr_##vendor[] __devinitdata = name;
#define ENDVENDOR()
#define DEVICE( vendor, device, name ) static char __devicestr_##vendor##device[] __devinitdata = name;
#include "devlist.h"
#define VENDOR( vendor, name ) static struct pci_device_info __devices_##vendor[] __devinitdata = {
#define ENDVENDOR() };
#define DEVICE( vendor, device, name ) { 0x##device, 0, __devicestr_##vendor##device },
#include "devlist.h"
static struct pci_vendor_info __devinitdata pci_vendor_list[] = {
#define VENDOR( vendor, name ) { 0x##vendor, sizeof(__devices_##vendor) / sizeof(struct pci_device_info), __vendorstr_##vendor, __devices_##vendor },
#define ENDVENDOR()
#define DEVICE( vendor, device, name )
#include "devlist.h"
};
#define VENDORS (sizeof(pci_vendor_list)/sizeof(struct pci_vendor_info))
void __devinit pci_name_device(struct pci_dev *dev)
{
const struct pci_vendor_info *vendor_p = pci_vendor_list;
int i = VENDORS;
char *name = dev->pretty_name;
do {
if (vendor_p->vendor == dev->vendor)
goto match_vendor;
vendor_p++;
} while (--i);
/* Couldn't find either the vendor nor the device */
sprintf(name, "PCI device %04x:%04x", dev->vendor, dev->device);
return;
match_vendor: {
struct pci_device_info *device_p = vendor_p->devices;
int i = vendor_p->nr;
while (i > 0) {
if (device_p->device == dev->device)
goto match_device;
device_p++;
i--;
}
/* Ok, found the vendor, but unknown device */
sprintf(name, "PCI device %04x:%04x (%." PCI_NAME_HALF "s)",
dev->vendor, dev->device, vendor_p->name);
return;
/* Full match */
match_device: {
char *n = name + sprintf(name, "%s %s",
vendor_p->name, device_p->name);
int nr = device_p->seen + 1;
device_p->seen = nr;
if (nr > 1)
sprintf(n, " (#%d)", nr);
}
}
}
/*
* Class names. Not in .init section as they are needed in runtime.
*/
static u16 pci_class_numbers[] = {
#define CLASS(x,y) 0x##x,
#include "classlist.h"
};
static char *pci_class_names[] = {
#define CLASS(x,y) y,
#include "classlist.h"
};
char *
pci_class_name(u32 class)
{
int i;
for(i=0; i<sizeof(pci_class_numbers)/sizeof(pci_class_numbers[0]); i++)
if (pci_class_numbers[i] == class)
return pci_class_names[i];
return NULL;
}
#else
void __devinit pci_name_device(struct pci_dev *dev)
{
}
char *
pci_class_name(u32 class)
{
return NULL;
}
#endif /* CONFIG_PCI_NAMES */

37
drivers/pci/pci-driver.c
View File

@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mempolicy.h>
#include "pci.h"
/*
@ -163,6 +164,34 @@ const struct pci_device_id *pci_match_device(struct pci_driver *drv,
return NULL;
}
static int pci_call_probe(struct pci_driver *drv, struct pci_dev *dev,
const struct pci_device_id *id)
{
int error;
#ifdef CONFIG_NUMA
/* Execute driver initialization on node where the
device's bus is attached to. This way the driver likely
allocates its local memory on the right node without
any need to change it. */
struct mempolicy *oldpol;
cpumask_t oldmask = current->cpus_allowed;
int node = pcibus_to_node(dev->bus);
if (node >= 0 && node_online(node))
set_cpus_allowed(current, node_to_cpumask(node));
/* And set default memory allocation policy */
oldpol = current->mempolicy;
current->mempolicy = &default_policy;
mpol_get(current->mempolicy);
#endif
error = drv->probe(dev, id);
#ifdef CONFIG_NUMA
set_cpus_allowed(current, oldmask);
mpol_free(current->mempolicy);
current->mempolicy = oldpol;
#endif
return error;
}
/**
* __pci_device_probe()
*
@ -180,7 +209,7 @@ __pci_device_probe(struct pci_driver *drv, struct pci_dev *pci_dev)
id = pci_match_device(drv, pci_dev);
if (id)
error = drv->probe(pci_dev, id);
error = pci_call_probe(drv, pci_dev, id);
if (error >= 0) {
pci_dev->driver = drv;
error = 0;
@ -243,17 +272,19 @@ static int pci_device_suspend(struct device * dev, pm_message_t state)
}
/*
/*
* Default resume method for devices that have no driver provided resume,
* or not even a driver at all.
*/
static void pci_default_resume(struct pci_dev *pci_dev)
{
int retval;
/* restore the PCI config space */
pci_restore_state(pci_dev);
/* if the device was enabled before suspend, reenable */
if (pci_dev->is_enabled)
pci_enable_device(pci_dev);
retval = pci_enable_device(pci_dev);
/* if the device was busmaster before the suspend, make it busmaster again */
if (pci_dev->is_busmaster)
pci_set_master(pci_dev);

104
drivers/pci/pci.c
View File

@ -221,6 +221,37 @@ pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
return best;
}
/**
* pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
* @dev: PCI device to have its BARs restored
*
* Restore the BAR values for a given device, so as to make it
* accessible by its driver.
*/
void
pci_restore_bars(struct pci_dev *dev)
{
int i, numres;
switch (dev->hdr_type) {
case PCI_HEADER_TYPE_NORMAL:
numres = 6;
break;
case PCI_HEADER_TYPE_BRIDGE:
numres = 2;
break;
case PCI_HEADER_TYPE_CARDBUS:
numres = 1;
break;
default:
/* Should never get here, but just in case... */
return;
}
for (i = 0; i < numres; i ++)
pci_update_resource(dev, &dev->resource[i], i);
}
/**
* pci_set_power_state - Set the power state of a PCI device
* @dev: PCI device to be suspended
@ -239,7 +270,7 @@ int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
int
pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
int pm;
int pm, need_restore = 0;
u16 pmcsr, pmc;
/* bound the state we're entering */
@ -263,7 +294,7 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
return -EIO;
pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
printk(KERN_DEBUG
"PCI: %s has unsupported PM cap regs version (%u)\n",
pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
@ -271,21 +302,22 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
}
/* check if this device supports the desired state */
if (state == PCI_D1 || state == PCI_D2) {
if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
return -EIO;
else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
return -EIO;
}
if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
return -EIO;
else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
return -EIO;
pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
/* If we're in D3, force entire word to 0.
* This doesn't affect PME_Status, disables PME_En, and
* sets PowerState to 0.
*/
if (dev->current_state >= PCI_D3hot)
if (dev->current_state >= PCI_D3hot) {
if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
need_restore = 1;
pmcsr = 0;
else {
pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
} else {
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
pmcsr |= state;
}
@ -308,6 +340,22 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
platform_pci_set_power_state(dev, state);
dev->current_state = state;
/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
* from D3hot to D0 _may_ perform an internal reset, thereby
* going to "D0 Uninitialized" rather than "D0 Initialized".
* For example, at least some versions of the 3c905B and the
* 3c556B exhibit this behaviour.
*
* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
* devices in a D3hot state at boot. Consequently, we need to
* restore at least the BARs so that the device will be
* accessible to its driver.
*/
if (need_restore)
pci_restore_bars(dev);
return 0;
}
@ -394,8 +442,11 @@ pci_enable_device_bars(struct pci_dev *dev, int bars)
{
int err;
pci_set_power_state(dev, PCI_D0);
if ((err = pcibios_enable_device(dev, bars)) < 0)
err = pci_set_power_state(dev, PCI_D0);
if (err < 0 && err != -EIO)
return err;
err = pcibios_enable_device(dev, bars);
if (err < 0)
return err;
return 0;
}
@ -747,6 +798,31 @@ pci_clear_mwi(struct pci_dev *dev)
}
}
/**
* pci_intx - enables/disables PCI INTx for device dev
* @dev: the PCI device to operate on
* @enable: boolean
*
* Enables/disables PCI INTx for device dev
*/
void
pci_intx(struct pci_dev *pdev, int enable)
{
u16 pci_command, new;
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if (enable) {
new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
} else {
new = pci_command | PCI_COMMAND_INTX_DISABLE;
}
if (new != pci_command) {
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
}
}
#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
/*
* These can be overridden by arch-specific implementations
@ -809,6 +885,7 @@ struct pci_dev *isa_bridge;
EXPORT_SYMBOL(isa_bridge);
#endif
EXPORT_SYMBOL_GPL(pci_restore_bars);
EXPORT_SYMBOL(pci_enable_device_bars);
EXPORT_SYMBOL(pci_enable_device);
EXPORT_SYMBOL(pci_disable_device);
@ -823,6 +900,7 @@ EXPORT_SYMBOL(pci_request_region);
EXPORT_SYMBOL(pci_set_master);
EXPORT_SYMBOL(pci_set_mwi);
EXPORT_SYMBOL(pci_clear_mwi);
EXPORT_SYMBOL_GPL(pci_intx);
EXPORT_SYMBOL(pci_set_dma_mask);
EXPORT_SYMBOL(pci_set_consistent_dma_mask);
EXPORT_SYMBOL(pci_assign_resource);

10180
drivers/pci/pci.ids
View File

File diff suppressed because it is too large Load Diff

8
drivers/pci/pcie/portdrv_pci.c
View File

@ -90,15 +90,19 @@ static void pcie_portdrv_save_config(struct pci_dev *dev)
pci_save_msi_state(dev);
}
static void pcie_portdrv_restore_config(struct pci_dev *dev)
static int pcie_portdrv_restore_config(struct pci_dev *dev)
{
struct pcie_port_device_ext *p_ext = pci_get_drvdata(dev);
int retval;
pci_restore_state(dev);
if (p_ext->interrupt_mode == PCIE_PORT_MSI_MODE)
pci_restore_msi_state(dev);
pci_enable_device(dev);
retval = pci_enable_device(dev);
if (retval)
return retval;
pci_set_master(dev);
return 0;
}
/*

4
drivers/pci/probe.c
View File

@ -584,7 +584,7 @@ static int pci_setup_device(struct pci_dev * dev)
dev->vendor, dev->device, class, dev->hdr_type);
/* "Unknown power state" */
dev->current_state = 4;
dev->current_state = PCI_UNKNOWN;
/* Early fixups, before probing the BARs */
pci_fixup_device(pci_fixup_early, dev);
@ -757,8 +757,6 @@ pci_scan_device(struct pci_bus *bus, int devfn)
dev->dev.release = pci_release_dev;
pci_dev_get(dev);
pci_name_device(dev);
dev->dev.dma_mask = &dev->dma_mask;
dev->dev.coherent_dma_mask = 0xffffffffull;

12
drivers/pci/proc.c
View File

@ -474,7 +474,7 @@ static int show_dev_config(struct seq_file *m, void *v)
struct pci_dev *first_dev;
struct pci_driver *drv;
u32 class_rev;
unsigned char latency, min_gnt, max_lat, *class;
unsigned char latency, min_gnt, max_lat;
int reg;
first_dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
@ -490,16 +490,8 @@ static int show_dev_config(struct seq_file *m, void *v)
pci_read_config_byte (dev, PCI_MAX_LAT, &max_lat);
seq_printf(m, " Bus %2d, device %3d, function %2d:\n",
dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
class = pci_class_name(class_rev >> 16);
if (class)
seq_printf(m, " %s", class);
else
seq_printf(m, " Class %04x", class_rev >> 16);
#ifdef CONFIG_PCI_NAMES
seq_printf(m, ": %s", dev->pretty_name);
#else
seq_printf(m, " Class %04x", class_rev >> 16);
seq_printf(m, ": PCI device %04x:%04x", dev->vendor, dev->device);
#endif
seq_printf(m, " (rev %d).\n", class_rev & 0xff);
if (dev->irq)

7
drivers/pci/quirks.c
View File

@ -245,12 +245,19 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsi
{
region &= ~(size-1);
if (region) {
struct pci_bus_region bus_region;
struct resource *res = dev->resource + nr;
res->name = pci_name(dev);
res->start = region;
res->end = region + size - 1;
res->flags = IORESOURCE_IO;
/* Convert from PCI bus to resource space. */
bus_region.start = res->start;
bus_region.end = res->end;
pcibios_bus_to_resource(dev, res, &bus_region);
pci_claim_resource(dev, nr);
}
}

7
drivers/pci/setup-res.c
View File

@ -26,7 +26,7 @@
#include "pci.h"
static void
void
pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
{
struct pci_bus_region region;
@ -97,10 +97,7 @@ pci_claim_resource(struct pci_dev *dev, int resource)
char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
int err;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
root = pcibios_select_root(dev, res);
err = -EINVAL;
if (root != NULL)

16
drivers/scsi/ahci.c
View File

@ -865,22 +865,6 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent)
return 0;
}
/* move to PCI layer, integrate w/ MSI stuff */
static void pci_intx(struct pci_dev *pdev, int enable)
{
u16 pci_command, new;
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if (enable)
new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
else
new = pci_command | PCI_COMMAND_INTX_DISABLE;
if (new != pci_command)
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
}
static void ahci_print_info(struct ata_probe_ent *probe_ent)
{
struct ahci_host_priv *hpriv = probe_ent->private_data;

14
drivers/scsi/ata_piix.c
View File

@ -568,18 +568,6 @@ static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
}
}
/* move to PCI layer, integrate w/ MSI stuff */
static void pci_enable_intx(struct pci_dev *pdev)
{
u16 pci_command;
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_INTX_DISABLE) {
pci_command &= ~PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
}
}
#define AHCI_PCI_BAR 5
#define AHCI_GLOBAL_CTL 0x04
#define AHCI_ENABLE (1 << 31)
@ -677,7 +665,7 @@ static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
* message-signalled interrupts currently).
*/
if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
pci_enable_intx(pdev);
pci_intx(pdev, 1);
if (combined) {
port_info[sata_chan] = &piix_port_info[ent->driver_data];

14
drivers/scsi/sata_sis.c
View File

@ -233,18 +233,6 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
}
}
/* move to PCI layer, integrate w/ MSI stuff */
static void pci_enable_intx(struct pci_dev *pdev)
{
u16 pci_command;
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_INTX_DISABLE) {
pci_command &= ~PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
}
}
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct ata_probe_ent *probe_ent = NULL;
@ -319,7 +307,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
}
pci_set_master(pdev);
pci_enable_intx(pdev);
pci_intx(pdev, 1);
/* FIXME: check ata_device_add return value */
ata_device_add(probe_ent);

14
drivers/scsi/sata_uli.c
View File

@ -176,18 +176,6 @@ static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
uli_scr_cfg_write(ap, sc_reg, val);
}
/* move to PCI layer, integrate w/ MSI stuff */
static void pci_enable_intx(struct pci_dev *pdev)
{
u16 pci_command;
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_INTX_DISABLE) {
pci_command &= ~PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
}
}
static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct ata_probe_ent *probe_ent;
@ -260,7 +248,7 @@ static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
}
pci_set_master(pdev);
pci_enable_intx(pdev);
pci_intx(pdev, 1);
/* FIXME: check ata_device_add return value */
ata_device_add(probe_ent);

28
drivers/usb/core/hcd-pci.c
View File

@ -121,10 +121,6 @@ int usb_hcd_pci_probe (struct pci_dev *dev, const struct pci_device_id *id)
}
}
#ifdef CONFIG_PCI_NAMES
hcd->product_desc = dev->pretty_name;
#endif
pci_set_master (dev);
retval = usb_add_hcd (hcd, dev->irq, SA_SHIRQ);
@ -264,8 +260,10 @@ int usb_hcd_pci_suspend (struct pci_dev *dev, pm_message_t message)
retval = pci_set_power_state (dev, PCI_D3hot);
if (retval == 0) {
dev_dbg (hcd->self.controller, "--> PCI D3\n");
pci_enable_wake (dev, PCI_D3hot, hcd->remote_wakeup);
pci_enable_wake (dev, PCI_D3cold, hcd->remote_wakeup);
retval = pci_enable_wake (dev, PCI_D3hot, hcd->remote_wakeup);
if (retval)
break;
retval = pci_enable_wake (dev, PCI_D3cold, hcd->remote_wakeup);
} else if (retval < 0) {
dev_dbg (&dev->dev, "PCI D3 suspend fail, %d\n",
retval);
@ -339,8 +337,20 @@ int usb_hcd_pci_resume (struct pci_dev *dev)
dev->current_state);
}
#endif
pci_enable_wake (dev, dev->current_state, 0);
pci_enable_wake (dev, PCI_D3cold, 0);
retval = pci_enable_wake (dev, dev->current_state, 0);
if (retval) {
dev_err(hcd->self.controller,
"can't enable_wake to %d, %d!\n",
dev->current_state, retval);
return retval;
}
retval = pci_enable_wake (dev, PCI_D3cold, 0);
if (retval) {
dev_err(hcd->self.controller,
"can't enable_wake to %d, %d!\n",
PCI_D3cold, retval);
return retval;
}
} else {
/* Same basic cases: clean (powered/not), dirty */
dev_dbg(hcd->self.controller, "PCI legacy resume\n");
@ -380,7 +390,7 @@ int usb_hcd_pci_resume (struct pci_dev *dev)
usb_hc_died (hcd);
}
pci_enable_device(dev);
retval = pci_enable_device(dev);
return retval;
}
EXPORT_SYMBOL (usb_hcd_pci_resume);

4
drivers/usb/host/ehci-hcd.c
View File

@ -549,7 +549,9 @@ static int ehci_start (struct usb_hcd *hcd)
hcd->can_wakeup = (port_wake & 1) != 0;
/* help hc dma work well with cachelines */
pci_set_mwi (pdev);
retval = pci_set_mwi(pdev);
if (retval)
ehci_dbg(ehci, "unable to enable MWI - not fatal.\n");
}
#endif

4
drivers/video/nvidia/nvidia.c
View File

@ -1473,10 +1473,6 @@ static int __devinit nvidiafb_probe(struct pci_dev *pd,
par->Chipset = (pd->vendor << 16) | pd->device;
printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
#ifdef CONFIG_PCI_NAMES
printk(KERN_INFO PFX "%s\n", pd->pretty_name);
#endif
if (par->Architecture == 0) {
printk(KERN_ERR PFX "unknown NV_ARCH\n");
goto err_out_free_base0;

4
drivers/video/riva/fbdev.c
View File

@ -1936,10 +1936,6 @@ static int __devinit rivafb_probe(struct pci_dev *pd,
default_par->Chipset = (pd->vendor << 16) | pd->device;
printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
#ifdef CONFIG_PCI_NAMES
printk(KERN_INFO PFX "%s\n", pd->pretty_name);
#endif
if(default_par->riva.Architecture == 0) {
printk(KERN_ERR PFX "unknown NV_ARCH\n");
ret=-ENODEV;

13
include/asm-alpha/pci.h
View File

@ -254,6 +254,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
static inline int pci_proc_domain(struct pci_bus *bus)

13
include/asm-arm/pci.h
View File

@ -64,6 +64,19 @@ extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
{
}

13
include/asm-generic/pci.h
View File

@ -30,6 +30,19 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
res->end = region->end;
}
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
#define pcibios_scan_all_fns(a, b) 0
#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ

13
include/asm-ia64/pci.h
View File

@ -156,6 +156,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
extern void pcibios_bus_to_resource(struct pci_dev *dev,
struct resource *res, struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
#define pcibios_scan_all_fns(a, b) 0
#endif /* _ASM_IA64_PCI_H */

13
include/asm-parisc/pci.h
View File

@ -257,6 +257,19 @@ extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
{
}

13
include/asm-ppc/pci.h
View File

@ -109,6 +109,19 @@ extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
extern void pcibios_add_platform_entries(struct pci_dev *dev);
struct file;

13
include/asm-ppc64/pci.h
View File

@ -138,6 +138,19 @@ extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
struct resource *root = NULL;
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
if (res->flags & IORESOURCE_MEM)
root = &iomem_resource;
return root;
}
extern int
unmap_bus_range(struct pci_bus *bus);

2
include/asm-sparc64/pci.h
View File

@ -269,6 +269,8 @@ extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
{
}

1
include/linux/mempolicy.h
View File

@ -155,6 +155,7 @@ struct mempolicy *get_vma_policy(struct task_struct *task,
extern void numa_default_policy(void);
extern void numa_policy_init(void);
extern struct mempolicy default_policy;
#else

511
include/linux/pci.h
View File

@ -19,436 +19,10 @@
#include <linux/mod_devicetable.h>
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK (~0x0fUL)
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK (~0x0fUL)
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK (~0x03UL)
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_PMC 2 /* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2 /* BCD version number */
#define PCI_AGP_RFU 3 /* Rest of capability flags */
#define PCI_AGP_STATUS 4 /* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8 /* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
#define PCI_AGP_SIZEOF 12
/* Vital Product Data */
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
#define PCI_MSI_RFU 3 /* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
#define PCI_CHSWP_PI 0x30 /* Programming Interface */
#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
/* PCI-X registers */
#define PCI_X_CMD 2 /* Modes & Features */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
#define PCI_X_STATUS 4 /* PCI-X capabilities */
#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
/* PCI Express capability registers */
#define PCI_EXP_FLAGS 2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCTL 16 /* Link Control */
#define PCI_EXP_LNKSTA 18 /* Link Status */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
#define PCI_EXP_RTCTL 28 /* Root Control */
#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTSTA 32 /* Root Status */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
#define PCI_EXT_CAP_ID_ERR 1
#define PCI_EXT_CAP_ID_VC 2
#define PCI_EXT_CAP_ID_DSN 3
#define PCI_EXT_CAP_ID_PWR 4
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
#define PCI_ERR_ROOT_STATUS 48
#define PCI_ERR_ROOT_COR_SRC 52
#define PCI_ERR_ROOT_SRC 54
/* Virtual Channel */
#define PCI_VC_PORT_REG1 4
#define PCI_VC_PORT_REG2 8
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_STATUS 14
#define PCI_VC_RES_CAP 16
#define PCI_VC_RES_CTRL 20
#define PCI_VC_RES_STATUS 26
/* Power Budgeting */
#define PCI_PWR_DSR 4 /* Data Select Register */
#define PCI_PWR_DATA 8 /* Data Register */
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
/* Include the pci register defines */
#include <linux/pci_regs.h>
/* Include the ID list */
#include <linux/pci_ids.h>
/*
@ -496,11 +70,12 @@ enum pci_mmap_state {
typedef int __bitwise pci_power_t;
#define PCI_D0 ((pci_power_t __force) 0)
#define PCI_D1 ((pci_power_t __force) 1)
#define PCI_D2 ((pci_power_t __force) 2)
#define PCI_D0 ((pci_power_t __force) 0)
#define PCI_D1 ((pci_power_t __force) 1)
#define PCI_D2 ((pci_power_t __force) 2)
#define PCI_D3hot ((pci_power_t __force) 3)
#define PCI_D3cold ((pci_power_t __force) 4)
#define PCI_UNKNOWN ((pci_power_t __force) 5)
#define PCI_POWER_ERROR ((pci_power_t __force) -1)
/*
@ -562,11 +137,6 @@ struct pci_dev {
struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
int rom_attr_enabled; /* has display of the rom attribute been enabled? */
struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
#ifdef CONFIG_PCI_NAMES
#define PCI_NAME_SIZE 255
#define PCI_NAME_HALF __stringify(43) /* less than half to handle slop */
char pretty_name[PCI_NAME_SIZE]; /* pretty name for users to see */
#endif
};
#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
@ -582,15 +152,15 @@ struct pci_dev {
* 7-10 bridges: address space assigned to buses behind the bridge
*/
#define PCI_ROM_RESOURCE 6
#define PCI_BRIDGE_RESOURCES 7
#define PCI_NUM_RESOURCES 11
#define PCI_ROM_RESOURCE 6
#define PCI_BRIDGE_RESOURCES 7
#define PCI_NUM_RESOURCES 11
#ifndef PCI_BUS_NUM_RESOURCES
#define PCI_BUS_NUM_RESOURCES 8
#define PCI_BUS_NUM_RESOURCES 8
#endif
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
struct pci_bus {
struct list_head node; /* node in list of buses */
@ -699,7 +269,7 @@ struct pci_driver {
* @dev_class_mask: the class mask for this device
*
* This macro is used to create a struct pci_device_id that matches a
* specific PCI class. The vendor, device, subvendor, and subdevice
* specific PCI class. The vendor, device, subvendor, and subdevice
* fields will be set to PCI_ANY_ID.
*/
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
@ -707,7 +277,7 @@ struct pci_driver {
.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
/*
/*
* pci_module_init is obsolete, this stays here till we fix up all usages of it
* in the tree.
*/
@ -749,8 +319,6 @@ int pci_scan_slot(struct pci_bus *bus, int devfn);
struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
unsigned int pci_scan_child_bus(struct pci_bus *bus);
void pci_bus_add_device(struct pci_dev *dev);
void pci_name_device(struct pci_dev *dev);
char *pci_class_name(u32 class);
void pci_read_bridge_bases(struct pci_bus *child);
struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
@ -815,9 +383,12 @@ void pci_set_master(struct pci_dev *dev);
#define HAVE_PCI_SET_MWI
int pci_set_mwi(struct pci_dev *dev);
void pci_clear_mwi(struct pci_dev *dev);
void pci_intx(struct pci_dev *dev, int enable);
int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
int pci_assign_resource(struct pci_dev *dev, int i);
void pci_restore_bars(struct pci_dev *dev);
/* ROM control related routines */
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
@ -865,6 +436,9 @@ const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_
const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
void *userdata);
/* kmem_cache style wrapper around pci_alloc_consistent() */
#include <linux/dmapool.h>
@ -912,18 +486,26 @@ extern void pci_disable_msix(struct pci_dev *dev);
extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
#endif
#endif /* CONFIG_PCI */
/*
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
* a PCI domain is defined to be a set of PCI busses which share
* configuration space.
*/
#ifndef CONFIG_PCI_DOMAINS
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline int pci_proc_domain(struct pci_bus *bus)
{
return 0;
}
#endif
/* Include architecture-dependent settings and functions */
#include <asm/pci.h>
#else /* CONFIG_PCI is not enabled */
/*
* If the system does not have PCI, clearly these return errors. Define
* these as simple inline functions to avoid hair in drivers.
*/
#ifndef CONFIG_PCI
#define _PCI_NOP(o,s,t) \
static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
@ -974,21 +556,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
#else
#endif /* CONFIG_PCI */
/*
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
* a PCI domain is defined to be a set of PCI busses which share
* configuration space.
*/
#ifndef CONFIG_PCI_DOMAINS
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline int pci_proc_domain(struct pci_bus *bus)
{
return 0;
}
#endif
#endif /* !CONFIG_PCI */
/* Include architecture-dependent settings and functions */
#include <asm/pci.h>
/* these helpers provide future and backwards compatibility
* for accessing popular PCI BAR info */
@ -1025,13 +597,6 @@ static inline char *pci_name(struct pci_dev *pdev)
return pdev->dev.bus_id;
}
/* Some archs want to see the pretty pci name, so use this macro */
#ifdef CONFIG_PCI_NAMES
#define pci_pretty_name(dev) ((dev)->pretty_name)
#else
#define pci_pretty_name(dev) ""
#endif
/* Some archs don't want to expose struct resource to userland as-is
* in sysfs and /proc
@ -1067,7 +632,7 @@ enum pci_fixup_pass {
/* Anonymous variables would be nice... */
#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
static struct pci_fixup __pci_fixup_##name __attribute_used__ \
static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
__attribute__((__section__(#section))) = { vendor, device, hook };
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \

448
include/linux/pci_regs.h Normal file
View File

@ -0,0 +1,448 @@
/*
* pci_regs.h
*
* PCI standard defines
* Copyright 1994, Drew Eckhardt
* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
*
* For more information, please consult the following manuals (look at
* http://www.pcisig.com/ for how to get them):
*
* PCI BIOS Specification
* PCI Local Bus Specification
* PCI to PCI Bridge Specification
* PCI System Design Guide
*/
#ifndef LINUX_PCI_REGS_H
#define LINUX_PCI_REGS_H
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK (~0x0fUL)
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK (~0x0fUL)
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK (~0x03UL)
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_PMC 2 /* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2 /* BCD version number */
#define PCI_AGP_RFU 3 /* Rest of capability flags */
#define PCI_AGP_STATUS 4 /* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8 /* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
#define PCI_AGP_SIZEOF 12
/* Vital Product Data */
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
#define PCI_MSI_RFU 3 /* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
#define PCI_CHSWP_PI 0x30 /* Programming Interface */
#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
/* PCI-X registers */
#define PCI_X_CMD 2 /* Modes & Features */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
#define PCI_X_STATUS 4 /* PCI-X capabilities */
#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
/* PCI Express capability registers */
#define PCI_EXP_FLAGS 2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCTL 16 /* Link Control */
#define PCI_EXP_LNKSTA 18 /* Link Status */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
#define PCI_EXP_RTCTL 28 /* Root Control */
#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTSTA 32 /* Root Status */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
#define PCI_EXT_CAP_ID_ERR 1
#define PCI_EXT_CAP_ID_VC 2
#define PCI_EXT_CAP_ID_DSN 3
#define PCI_EXT_CAP_ID_PWR 4
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
#define PCI_ERR_ROOT_STATUS 48
#define PCI_ERR_ROOT_COR_SRC 52
#define PCI_ERR_ROOT_SRC 54
/* Virtual Channel */
#define PCI_VC_PORT_REG1 4
#define PCI_VC_PORT_REG2 8
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_STATUS 14
#define PCI_VC_RES_CAP 16
#define PCI_VC_RES_CTRL 20
#define PCI_VC_RES_STATUS 26
/* Power Budgeting */
#define PCI_PWR_DSR 4 /* Data Select Register */
#define PCI_PWR_DATA 8 /* Data Register */
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
#endif /* LINUX_PCI_REGS_H */

2
mm/mempolicy.c
View File

@ -88,7 +88,7 @@ static kmem_cache_t *sn_cache;
policied. */
static int policy_zone;
static struct mempolicy default_policy = {
struct mempolicy default_policy = {
.refcnt = ATOMIC_INIT(1), /* never free it */
.policy = MPOL_DEFAULT,
};