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perf_counter: fix crash on perfmon v1 systems
Impact: fix boot crash on Intel Perfmon Version 1 systems Intel Perfmon v1 does not support the global MSRs, nor does it offer the generalized MSR ranges. So support v2 and later CPUs only. Also mark pmc_ops as read-mostly - to avoid false cacheline sharing. Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -57,12 +57,14 @@ struct pmc_x86_ops {
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int max_events;
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};
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static struct pmc_x86_ops *pmc_ops;
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static struct pmc_x86_ops *pmc_ops __read_mostly;
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static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
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.enabled = 1,
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};
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static __read_mostly int intel_perfmon_version;
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/*
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* Intel PerfMon v3. Used on Core2 and later.
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*/
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@ -613,7 +615,7 @@ void perf_counter_print_debug(void)
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cpu = smp_processor_id();
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cpuc = &per_cpu(cpu_hw_counters, cpu);
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
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if (intel_perfmon_version >= 2) {
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rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
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rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
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@ -930,10 +932,10 @@ static struct pmc_x86_ops pmc_amd_ops = {
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static struct pmc_x86_ops *pmc_intel_init(void)
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{
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union cpuid10_eax eax;
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unsigned int ebx;
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unsigned int unused;
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union cpuid10_edx edx;
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union cpuid10_eax eax;
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unsigned int unused;
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unsigned int ebx;
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/*
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* Check whether the Architectural PerfMon supports
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@ -943,8 +945,12 @@ static struct pmc_x86_ops *pmc_intel_init(void)
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if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
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return NULL;
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intel_perfmon_version = eax.split.version_id;
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if (intel_perfmon_version < 2)
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return NULL;
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pr_info("Intel Performance Monitoring support detected.\n");
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pr_info("... version: %d\n", eax.split.version_id);
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pr_info("... version: %d\n", intel_perfmon_version);
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pr_info("... bit width: %d\n", eax.split.bit_width);
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pr_info("... mask length: %d\n", eax.split.mask_length);
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