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https://github.com/torvalds/linux.git
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ARM: shmobile: r8a73a4 dtsi: Add PM domain support
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Add a minimal device node for the Coresight-ETM hardware block, and hook it up to the D4 PM domain, so the R-Mobile System Controller driver can keep the domain powered, until the new Coresight code handles runtime PM. The System Controller is also used by the R-Mobile Reset driver, which can now restart the system. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
Simon Horman
parent
12920b02c0
commit
7b9ad9a0ab
@ -28,9 +28,15 @@
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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power-domains = <&pd_a2sl>;
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};
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};
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ptm {
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compatible = "arm,coresight-etm3x";
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power-domains = <&pd_d4>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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@ -42,11 +48,13 @@
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dbsc1: memory-controller@e6790000 {
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compatible = "renesas,dbsc-r8a73a4";
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reg = <0 0xe6790000 0 0x10000>;
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power-domains = <&pd_a3bc>;
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};
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dbsc2: memory-controller@e67a0000 {
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compatible = "renesas,dbsc-r8a73a4";
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reg = <0 0xe67a0000 0 0x10000>;
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power-domains = <&pd_a3bc>;
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};
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dmac: dma-multiplexer {
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@ -89,6 +97,7 @@
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19";
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clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
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power-domains = <&pd_a3sp>;
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};
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};
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@ -99,6 +108,7 @@
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reg = <0 0xe60b0000 0 0x428>;
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interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -109,6 +119,7 @@
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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renesas,channels-mask = <0xff>;
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@ -152,6 +163,7 @@
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<0 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 31 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_c4>;
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};
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irqc1: interrupt-controller@e61c0200 {
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@ -185,6 +197,7 @@
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<0 55 IRQ_TYPE_LEVEL_HIGH>,
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<0 56 IRQ_TYPE_LEVEL_HIGH>,
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<0 57 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_c4>;
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};
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pfc: pfc@e6050000 {
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@ -208,6 +221,7 @@
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<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
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<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
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<&irqc1 24 0>, <&irqc1 25 0>;
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power-domains = <&pd_c5>;
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};
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thermal@e61f0000 {
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@ -216,6 +230,7 @@
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<0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
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power-domains = <&pd_c5>;
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};
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i2c0: i2c@e6500000 {
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@ -225,6 +240,7 @@
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reg = <0 0xe6500000 0 0x428>;
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interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -235,6 +251,7 @@
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reg = <0 0xe6510000 0 0x428>;
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interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -245,6 +262,7 @@
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reg = <0 0xe6520000 0 0x428>;
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interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -255,6 +273,7 @@
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reg = <0 0xe6530000 0 0x428>;
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interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -265,6 +284,7 @@
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reg = <0 0xe6540000 0 0x428>;
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interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -275,6 +295,7 @@
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reg = <0 0xe6550000 0 0x428>;
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interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -285,6 +306,7 @@
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reg = <0 0xe6560000 0 0x428>;
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interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -295,6 +317,7 @@
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reg = <0 0xe6570000 0 0x428>;
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interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -304,6 +327,7 @@
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interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -313,6 +337,7 @@
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -322,6 +347,7 @@
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -331,6 +357,7 @@
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -340,6 +367,7 @@
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interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -349,6 +377,7 @@
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interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
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clock-names = "sci_ick";
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power-domains = <&pd_c4>;
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status = "disabled";
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};
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@ -357,6 +386,7 @@
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reg = <0 0xee100000 0 0x100>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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status = "disabled";
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};
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@ -366,6 +396,7 @@
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reg = <0 0xee120000 0 0x100>;
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interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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status = "disabled";
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};
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@ -375,6 +406,7 @@
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reg = <0 0xee140000 0 0x100>;
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interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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status = "disabled";
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};
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@ -384,6 +416,7 @@
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reg = <0 0xee200000 0 0x80>;
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interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
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power-domains = <&pd_a3sp>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -393,6 +426,7 @@
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reg = <0 0xee220000 0 0x80>;
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interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
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power-domains = <&pd_a3sp>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -417,6 +451,7 @@
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ranges = <0 0 0 0x20000000>;
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reg = <0 0xfec10000 0 0x400>;
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clocks = <&zb_clk>;
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power-domains = <&pd_c4>;
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};
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clocks {
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@ -711,4 +746,146 @@
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"thermal", "iic8";
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};
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
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reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
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pm-domains {
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pd_c5: c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_c4: c4@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3sg: a3sg@16 {
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reg = <16>;
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#power-domain-cells = <0>;
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};
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pd_a3ex: a3ex@17 {
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reg = <17>;
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#power-domain-cells = <0>;
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};
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pd_a3sp: a3sp@18 {
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reg = <18>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2us: a2us@19 {
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reg = <19>;
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#power-domain-cells = <0>;
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};
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};
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pd_a3sm: a3sm@20 {
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reg = <20>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2sl: a2sl@21 {
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reg = <21>;
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#power-domain-cells = <0>;
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};
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};
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pd_a3km: a3km@22 {
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reg = <22>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2kl: a2kl@23 {
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reg = <23>;
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#power-domain-cells = <0>;
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};
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};
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};
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pd_c4ma: c4ma@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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};
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pd_c4cl: c4cl@2 {
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reg = <2>;
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#power-domain-cells = <0>;
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};
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pd_d4: d4@3 {
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reg = <3>;
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#power-domain-cells = <0>;
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};
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pd_a4bc: a4bc@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3bc: a3bc@5 {
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reg = <5>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4l: a4l@6 {
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reg = <6>;
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#power-domain-cells = <0>;
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};
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pd_a4lc: a4lc@7 {
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reg = <7>;
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#power-domain-cells = <0>;
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};
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pd_a4mp: a4mp@8 {
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reg = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3mp: a3mp@9 {
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reg = <9>;
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#power-domain-cells = <0>;
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};
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pd_a3vc: a3vc@10 {
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reg = <10>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4sf: a4sf@11 {
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reg = <11>;
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#power-domain-cells = <0>;
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};
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pd_a3r: a3r@12 {
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reg = <12>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a2rv: a2rv@13 {
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reg = <13>;
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#power-domain-cells = <0>;
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};
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pd_a2is: a2is@14 {
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reg = <14>;
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#power-domain-cells = <0>;
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};
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};
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};
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};
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};
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};
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