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media: imx: imx7_mipi_csis: Rename register macros to match datasheet
Rename several register macros to match the names from the documentation. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rui Miguel Silva <rmfrfs@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
547e9437b0
commit
7b437a246a
@ -63,61 +63,61 @@
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#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
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/* CSIS Interrupt mask */
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#define MIPI_CSIS_INTMSK 0x10
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#define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INTMSK_FRAME_START BIT(24)
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#define MIPI_CSIS_INTMSK_FRAME_END BIT(20)
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#define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INTMSK_ERR_OVER BIT(4)
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#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INTMSK_ERR_ECC BIT(2)
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#define MIPI_CSIS_INTMSK_ERR_CRC BIT(1)
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#define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0)
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#define MIPI_CSIS_INT_MSK 0x10
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#define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INT_MSK_FRAME_START BIT(24)
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#define MIPI_CSIS_INT_MSK_FRAME_END BIT(20)
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#define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4)
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#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
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#define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
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#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
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/* CSIS Interrupt source */
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#define MIPI_CSIS_INTSRC 0x14
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#define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INTSRC_EVEN BIT(30)
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#define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INTSRC_ODD (0x3 << 28)
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#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
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#define MIPI_CSIS_INTSRC_FRAME_START BIT(24)
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#define MIPI_CSIS_INTSRC_FRAME_END BIT(20)
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#define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INTSRC_ERR_OVER BIT(4)
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#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INTSRC_ERR_ECC BIT(2)
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#define MIPI_CSIS_INTSRC_ERR_CRC BIT(1)
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#define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0)
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#define MIPI_CSIS_INTSRC_ERRORS 0xfffff
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#define MIPI_CSIS_INT_SRC 0x14
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#define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INT_SRC_EVEN BIT(30)
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#define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INT_SRC_ODD (0x3 << 28)
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#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28)
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#define MIPI_CSIS_INT_SRC_FRAME_START BIT(24)
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#define MIPI_CSIS_INT_SRC_FRAME_END BIT(20)
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#define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4)
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#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
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#define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
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#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
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#define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
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/* D-PHY status control */
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#define MIPI_CSIS_DPHYSTATUS 0x20
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#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8)
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#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4)
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#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1)
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#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0)
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#define MIPI_CSIS_DPHY_STATUS 0x20
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#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8)
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#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4)
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#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1)
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#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0)
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/* D-PHY common control */
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#define MIPI_CSIS_DPHYCTRL 0x24
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#define MIPI_CSIS_DPHYCTRL_HSSETTLE(n) ((n) << 24)
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#define MIPI_CSIS_DPHYCTRL_HSSETTLE_MASK GENMASK(31, 24)
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#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22)
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#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22
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#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6)
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#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5)
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#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1)
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#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0)
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#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0)
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#define MIPI_CSIS_DPHY_CMN_CTRL 0x24
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#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24)
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#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
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#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
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#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
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#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
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#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
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#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
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#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
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#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
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/* D-PHY Master and Slave Control register Low */
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#define MIPI_CSIS_DPHY_BCTRL_L 0x30
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@ -163,7 +163,7 @@
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#define MIPI_CSIS_DPHY_SCTRL_H 0x3c
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/* ISP Configuration register */
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#define MIPI_CSIS_ISPCONFIG_CH(n) (0x40 + (n) * 0x10)
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#define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10)
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#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
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#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
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#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12)
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@ -178,15 +178,15 @@
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#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
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/* ISP Image Resolution register */
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#define MIPI_CSIS_ISPRESOL_CH(n) (0x44 + (n) * 0x10)
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#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
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#define CSIS_MAX_PIX_WIDTH 0xffff
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#define CSIS_MAX_PIX_HEIGHT 0xffff
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/* ISP SYNC register */
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#define MIPI_CSIS_ISPSYNC_CH(n) (0x48 + (n) * 0x10)
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#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18
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#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12
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#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0
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#define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
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#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
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#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
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#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
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/* Non-image packet data buffers */
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#define MIPI_CSIS_PKTDATA_ODD 0x2000
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@ -209,22 +209,22 @@ struct mipi_csis_event {
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static const struct mipi_csis_event mipi_csis_events[] = {
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/* Errors */
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{ MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
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{ MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
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{ MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
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{ MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
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{ MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
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{ MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error" },
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{ MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error" },
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{ MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
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{ MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" },
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{ MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" },
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{ MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" },
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{ MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" },
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{ MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
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{ MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
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{ MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
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{ MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
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/* Non-image data receive events */
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{ MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
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{ MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
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{ MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
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{ MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
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{ MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" },
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{ MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" },
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{ MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" },
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{ MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" },
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/* Frame start/end */
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{ MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" },
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{ MIPI_CSIS_INTSRC_FRAME_END, "Frame End" },
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{ MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" },
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{ MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" },
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};
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#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
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@ -444,7 +444,7 @@ static const struct csis_pix_format *find_csis_format(u32 code)
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static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
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{
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mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
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mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
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}
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static void mipi_csis_sw_reset(struct csi_state *state)
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@ -486,13 +486,13 @@ static void mipi_csis_system_enable(struct csi_state *state, int on)
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val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
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mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
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val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
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val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
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val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL);
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val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
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if (on) {
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mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
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val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
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val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
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}
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mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
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mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val);
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}
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/* Called with the state.lock mutex held */
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@ -502,14 +502,14 @@ static void __mipi_csis_set_format(struct csi_state *state)
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u32 val;
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/* Color format */
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val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH(0));
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val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0));
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val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
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val |= state->csis_fmt->fmt_reg;
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mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH(0), val);
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mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val);
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/* Pixel resolution */
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val = mf->width | (mf->height << 16);
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mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH(0), val);
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mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val);
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}
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static int mipi_csis_calculate_params(struct csi_state *state)
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@ -558,13 +558,13 @@ static void mipi_csis_set_params(struct csi_state *state)
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__mipi_csis_set_format(state);
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mipi_csis_write(state, MIPI_CSIS_DPHYCTRL,
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MIPI_CSIS_DPHYCTRL_HSSETTLE(state->hs_settle));
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mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
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MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle));
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val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
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(0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
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(0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
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mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH(0), val);
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val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
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| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
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| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
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mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val);
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val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
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val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
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@ -955,12 +955,12 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
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unsigned int i;
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u32 status;
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status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
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status = mipi_csis_read(state, MIPI_CSIS_INT_SRC);
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spin_lock_irqsave(&state->slock, flags);
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/* Update the event/error counters */
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if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
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if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug) {
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for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
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if (!(status & state->events[i].mask))
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continue;
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@ -969,7 +969,7 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
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}
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spin_unlock_irqrestore(&state->slock, flags);
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mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
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mipi_csis_write(state, MIPI_CSIS_INT_SRC, status);
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return IRQ_HANDLED;
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}
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