mirror of
https://github.com/torvalds/linux.git
synced 2024-11-22 12:11:40 +00:00
soc: devicetree updates for 6.12
New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the last
one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to
many new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both
on the consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very
low number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom
and renesas chips.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmboLzkACgkQYKtH/8kJ
Uid+1g/+J8rQQxIjLxxbx+TkhECt5X1u5mQZTZBIeCZmJQz2rNvmo3bm89ZAR32Z
FnjSN0fXw7eZqnxImwNAIU7g7RBhj5zs1gKXsB2lb0vv7722KyQ1xz2Fh1NQWQ09
OMCVjI1+19zBZYCB0C1Y2WTsFRUl5ISE3H3Wx8MJT1GWDDao/D2ULkEda0uTSu3i
CBYBNwCtBJU7TsGe5a04P7rGKvOlDdVj+2VvMKaX6bFa+MDxoMtlABWLZRJCwOy8
04+Oz9AO0r6HpsrAKOgxxNod7Jkw13UUG22PoTS4+B2Bc7/9oXTcJM8e+44BEe4J
nyJButDCAf7IsqOuB0S/4J0YxtcDGnzJXNQrUg11owwVXC+uzVvkUExOneRBXqUc
179OlY5tCXaaRtmoeUTOH9C4rk5x6o5jHCLs2DJNf9TsOwD2VjzUvUWp5WBhDDG4
qxIUvflGm2pXhF9OeK+7fPllTc1pUmA2/LZ9LXc/13Zn3eZKGn/Kql1SNFC0CIi0
8kQnIcV0dOh7E+zPcYENR+NGuTUU2GH3iQM9frHIaPc+KcaXPRVJDqREe/RNYRqN
qDY7yIGkeqmH9mKhdV+WQGBjJ6z3ElOMYVST6Kq3JBDiF12UaCPEhG2t8inmvEsA
t7nL84iWpeC1Gh+AT8UJBlRSFzQoafIrVav26pqwCvOrK7UHMZk=
=r07W
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the
last one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to many
new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both on the
consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very low
number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom and renesas
chips"
* tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (672 commits)
arm64: dts: allwinner: h5: NanoPi NEO Plus2: Use regulators for pio
arm64: dts: mediatek: add audio support for mt8365-evk
arm64: dts: mediatek: add afe support for mt8365 SoC
arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface
arm64: dts: mediatek: mt8186: Add svs node
arm64: dts: mediatek: mt8186: Add power domain for DPI
arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
arm64: dts: mt8183: add dpi node to mt8183
arm64: dts: allwinner: h5: NanoPi Neo Plus2: Fix regulators
arm64: dts: rockchip: add CAN0 and CAN1 interfaces to mecsbc board
arm64: dts: rockchip: add CAN-FD controller nodes to rk3568
arm64: dts: nuvoton: ma35d1: Add uart pinctrl settings
arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes
arm64: dts: nuvoton: Add syscon to the system-management node
ARM: dts: Fix undocumented LM75 compatible nodes
arm64: dts: toshiba: Fix pl011 and pl022 clocks
ARM: dts: stm32: Use SAI to generate bit and frame clock on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Switch bitclock/frame-master to flag on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Add MECIO1 and MECT1S board variants
...
This commit is contained in:
Linus Torvalds
commit
7b17f5ebd5
@ -79,6 +79,7 @@ properties:
|
||||
- aspeed,ast2600-evb-a1
|
||||
- asus,x4tf-bmc
|
||||
- facebook,bletchley-bmc
|
||||
- facebook,catalina-bmc
|
||||
- facebook,cloudripper-bmc
|
||||
- facebook,elbert-bmc
|
||||
- facebook,fuji-bmc
|
||||
@ -86,7 +87,9 @@ properties:
|
||||
- facebook,harma-bmc
|
||||
- facebook,minerva-cmc
|
||||
- facebook,yosemite4-bmc
|
||||
- ibm,blueridge-bmc
|
||||
- ibm,everest-bmc
|
||||
- ibm,fuji-bmc
|
||||
- ibm,rainier-bmc
|
||||
- ibm,system1-bmc
|
||||
- ibm,tacoma-bmc
|
||||
|
||||
@ -809,19 +809,19 @@ properties:
|
||||
- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
|
||||
- description: TQ-Systems TQMa6ULLx SoM on MBa6ULx board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2-mba6ulx
|
||||
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
|
||||
- tq,imx6ull-tqma6ull2-mba6ulx # TQMa6ULL socketable SoM with MCIMX6Y2 on MBa6ULx EVK
|
||||
- const: tq,imx6ull-tqma6ull2 # TQMa6ULL socketable SoM with MCIMX6Y2
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
|
||||
- description: TQ-Systems TQMa6ULLxL SoM on MBa6ULx[L] board
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulxl
|
||||
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulx # TQMa6ULLxL LGA SoM with socketable Adapter on MBa6ULx EVK
|
||||
- tq,imx6ull-tqma6ull2l-mba6ulxl # TQMa6ULLxL LGA SoM on MBa6ULxL gateway board
|
||||
- const: tq,imx6ull-tqma6ull2l # TQMa6ULLxL LGA SoM with MCIMX6Y2
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Seeed Stuido i.MX6ULL SoM on dev boards
|
||||
@ -939,8 +939,8 @@ properties:
|
||||
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
|
||||
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
|
||||
- gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
|
||||
- gateworks,imx8mm-gw7904
|
||||
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
|
||||
@ -953,7 +953,6 @@ properties:
|
||||
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
|
||||
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
|
||||
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
|
||||
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
|
||||
- const: fsl,imx8mm
|
||||
|
||||
@ -1082,7 +1081,7 @@ properties:
|
||||
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
|
||||
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
|
||||
@ -1168,6 +1167,12 @@ properties:
|
||||
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Variscite VAR-SOM-MX8M Plus based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx8mp-symphony
|
||||
- const: variscite,var-som-mx8mp
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -1293,6 +1298,7 @@ properties:
|
||||
- enum:
|
||||
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
|
||||
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
|
||||
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: i.MX95 based Boards
|
||||
@ -1344,6 +1350,12 @@ properties:
|
||||
- const: variscite,var-som-mx93
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: Kontron OSM-S i.MX93 SoM based boards
|
||||
items:
|
||||
- const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board
|
||||
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
@ -1523,6 +1535,12 @@ properties:
|
||||
- fsl,ls2080a-rdb
|
||||
- const: fsl,ls2080a
|
||||
|
||||
- description: LS2081A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2081a-rdb
|
||||
- const: fsl,ls2081a
|
||||
|
||||
- description: LS2088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -155,6 +155,11 @@ properties:
|
||||
- const: qcom,msm8926
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- wingtech,wt82918hd
|
||||
- const: qcom,msm8929
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- huawei,kiwi
|
||||
@ -162,6 +167,8 @@ properties:
|
||||
- samsung,a7
|
||||
- sony,kanuti-tulip
|
||||
- square,apq8039-t2
|
||||
- wingtech,wt82918
|
||||
- wingtech,wt82918hdhw39
|
||||
- const: qcom,msm8939
|
||||
|
||||
- items:
|
||||
@ -228,12 +235,15 @@ properties:
|
||||
- samsung,grandprimelte
|
||||
- samsung,gt510
|
||||
- samsung,gt58
|
||||
- samsung,j3ltetw
|
||||
- samsung,j5
|
||||
- samsung,j5x
|
||||
- samsung,rossa
|
||||
- samsung,serranove
|
||||
- thwc,uf896
|
||||
- thwc,ufi001c
|
||||
- wingtech,wt86518
|
||||
- wingtech,wt86528
|
||||
- wingtech,wt88047
|
||||
- yiming,uz801-v3
|
||||
- const: qcom,msm8916
|
||||
@ -250,6 +260,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- lg,bullhead
|
||||
- lg,h815
|
||||
- microsoft,talkman
|
||||
- xiaomi,libra
|
||||
- const: qcom,msm8992
|
||||
@ -1038,10 +1049,18 @@ properties:
|
||||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-t14s
|
||||
- const: qcom,x1e78100
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
- microsoft,romulus15
|
||||
- qcom,x1e80100-crd
|
||||
- qcom,x1e80100-qcp
|
||||
- const: qcom,x1e80100
|
||||
|
||||
@ -96,6 +96,13 @@ properties:
|
||||
- const: coolpi,pi-cm5
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Cool Pi CM5 GenBook
|
||||
items:
|
||||
- enum:
|
||||
- coolpi,pi-cm5-genbook
|
||||
- const: coolpi,pi-cm5
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Cool Pi 4 Model B
|
||||
items:
|
||||
- const: coolpi,pi-4b
|
||||
@ -148,6 +155,12 @@ properties:
|
||||
- const: engicam,px30-core
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
|
||||
items:
|
||||
- const: firefly,px30-jd4-core-mb
|
||||
- const: firefly,px30-jd4-core
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Firefly Firefly-RK3288
|
||||
items:
|
||||
- enum:
|
||||
@ -216,6 +229,7 @@ properties:
|
||||
- friendlyarm,nanopi-r2c
|
||||
- friendlyarm,nanopi-r2c-plus
|
||||
- friendlyarm,nanopi-r2s
|
||||
- friendlyarm,nanopi-r2s-plus
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
@ -243,9 +257,11 @@ properties:
|
||||
- friendlyarm,nanopi-r6s
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: FriendlyElec NanoPC T6
|
||||
- description: FriendlyElec NanoPC T6 series boards
|
||||
items:
|
||||
- const: friendlyarm,nanopc-t6
|
||||
- enum:
|
||||
- friendlyarm,nanopc-t6
|
||||
- friendlyarm,nanopc-t6-lts
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: FriendlyElec CM3588-based boards
|
||||
@ -255,6 +271,11 @@ properties:
|
||||
- const: friendlyarm,cm3588
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: GameForce Ace
|
||||
items:
|
||||
- const: gameforce,ace
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: GameForce Chi
|
||||
items:
|
||||
- const: gameforce,chi
|
||||
@ -581,9 +602,19 @@ properties:
|
||||
|
||||
- description: Hardkernel Odroid M1
|
||||
items:
|
||||
- const: rockchip,rk3568-odroid-m1
|
||||
- const: hardkernel,odroid-m1
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Hardkernel Odroid M1S
|
||||
items:
|
||||
- const: hardkernel,odroid-m1s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Hardkernel Odroid M2
|
||||
items:
|
||||
- const: hardkernel,odroid-m2
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Hugsun X99 TV Box
|
||||
items:
|
||||
- const: hugsun,x99
|
||||
@ -622,6 +653,11 @@ properties:
|
||||
- const: leez,p710
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: LCKFB Taishan Pi RK3566
|
||||
items:
|
||||
- const: lckfb,tspi-rk3566
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Lunzn FastRhino R66S / R68S
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -54,6 +54,8 @@ properties:
|
||||
- description: ST STM32MP151 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,mecio1r0 # Protonic MECIO1r0
|
||||
- prt,mect1s # Protonic MECT1S
|
||||
- prt,prtt1a # Protonic PRTT1A
|
||||
- prt,prtt1c # Protonic PRTT1C
|
||||
- prt,prtt1s # Protonic PRTT1S
|
||||
@ -71,6 +73,12 @@ properties:
|
||||
- const: dh,stm32mp151a-dhcor-som
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: ST STM32MP153 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- prt,mecio1r1 # Protonic MECIO1r1
|
||||
- const: st,stm32mp153
|
||||
|
||||
- description: DH STM32MP153 DHCOM SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp153c-dhcom-drc02
|
||||
|
||||
@ -61,14 +61,19 @@ properties:
|
||||
- const: anbernic,rg35xx-2024
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX H
|
||||
items:
|
||||
- const: anbernic,rg35xx-h
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX Plus
|
||||
items:
|
||||
- const: anbernic,rg35xx-plus
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Anbernic RG35XX H
|
||||
- description: Anbernic RG35XX SP
|
||||
items:
|
||||
- const: anbernic,rg35xx-h
|
||||
- const: anbernic,rg35xx-sp
|
||||
- const: allwinner,sun50i-h700
|
||||
|
||||
- description: Amarula A64 Relic
|
||||
|
||||
@ -127,6 +127,48 @@ properties:
|
||||
- nvidia,norrin
|
||||
- const: nvidia,tegra132
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-blaze-rev10
|
||||
- const: google,nyan-blaze-rev9
|
||||
- const: google,nyan-blaze-rev8
|
||||
- const: google,nyan-blaze-rev7
|
||||
- const: google,nyan-blaze-rev6
|
||||
- const: google,nyan-blaze-rev5
|
||||
- const: google,nyan-blaze-rev4
|
||||
- const: google,nyan-blaze-rev3
|
||||
- const: google,nyan-blaze-rev2
|
||||
- const: google,nyan-blaze-rev1
|
||||
- const: google,nyan-blaze-rev0
|
||||
- const: google,nyan-blaze
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-big-rev10
|
||||
- const: google,nyan-big-rev9
|
||||
- const: google,nyan-big-rev8
|
||||
- const: google,nyan-big-rev7
|
||||
- const: google,nyan-big-rev6
|
||||
- const: google,nyan-big-rev5
|
||||
- const: google,nyan-big-rev4
|
||||
- const: google,nyan-big-rev3
|
||||
- const: google,nyan-big-rev2
|
||||
- const: google,nyan-big-rev1
|
||||
- const: google,nyan-big-rev0
|
||||
- const: google,nyan-big
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-big-rev7
|
||||
- const: google,nyan-big-rev6
|
||||
- const: google,nyan-big-rev5
|
||||
- const: google,nyan-big-rev4
|
||||
- const: google,nyan-big-rev3
|
||||
- const: google,nyan-big-rev2
|
||||
- const: google,nyan-big-rev1
|
||||
- const: google,nyan-big-rev0
|
||||
- const: google,nyan-big
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,darcy
|
||||
|
||||
@ -140,6 +140,7 @@ properties:
|
||||
- description: K3 J722S SoC and Boards
|
||||
items:
|
||||
- enum:
|
||||
- beagle,am67a-beagley-ai
|
||||
- ti,j722s-evm
|
||||
- const: ti,j722s
|
||||
|
||||
|
||||
@ -24,11 +24,13 @@ properties:
|
||||
items:
|
||||
- description: input top pll
|
||||
- description: input mclk pll
|
||||
- description: input fix pll
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: top
|
||||
- const: mclk
|
||||
- const: fix
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
@ -52,8 +54,9 @@ examples:
|
||||
compatible = "amlogic,c3-pll-clkc";
|
||||
reg = <0x0 0x8000 0x0 0x1a4>;
|
||||
clocks = <&scmi_clk 2>,
|
||||
<&scmi_clk 5>;
|
||||
clock-names = "top", "mclk";
|
||||
<&scmi_clk 5>,
|
||||
<&scmi_clk 12>;
|
||||
clock-names = "top", "mclk", "fix";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -31,6 +31,8 @@ properties:
|
||||
- description: USB PCIE wrapper pipe clock source
|
||||
|
||||
'#power-domain-cells': false
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM4450
|
||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock source from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,sm4450-camcc";
|
||||
reg = <0x0ade0000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SM4450
|
||||
|
||||
maintainers:
|
||||
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM4450
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm4450-dispcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Display AHB clock source from GCC
|
||||
- description: sleep clock source
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm4450-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy_pll_out_byteclk>,
|
||||
<&dsi0_phy_pll_out_dsiclk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM8150
|
||||
|
||||
maintainers:
|
||||
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and
|
||||
power domains on SM8150.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Camera AHB clock from GCC
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8150-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -14,6 +14,7 @@ description: |
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm4450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
@ -23,6 +24,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm4450-gpucc
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
|
||||
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
|
||||
and control of clock signals for the IP modules, generation and control of resets,
|
||||
and control over booting, low power consumption and power supply domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a09g057-cpg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AUDIO_EXTAL clock input
|
||||
- description: RTXIN clock input
|
||||
- description: QEXTAL clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio_extal
|
||||
- const: rtxin
|
||||
- const: qextal
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number. The module number is calculated as the CLKON register
|
||||
offset index multiplied by 16, plus the actual bit in the register
|
||||
used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
|
||||
calculation is (1 * 16 + 3) = 0x13.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the reset number. The reset number
|
||||
is calculated as the reset register offset index multiplied by 16, plus the
|
||||
actual bit in the register used to reset the specific IP block. For example,
|
||||
for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@10420000 {
|
||||
compatible = "renesas,r9a09g057-cpg";
|
||||
reg = <0x10420000 0x10000>;
|
||||
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
|
||||
clock-names = "audio_extal", "rtxin", "qextal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -35,6 +35,7 @@ properties:
|
||||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-dpum
|
||||
- samsung,exynosautov9-cmu-fsys0
|
||||
- samsung,exynosautov9-cmu-fsys1
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
@ -109,6 +110,24 @@ allOf:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-dpum
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: DPU Main bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -0,0 +1,162 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung ExynosAuto v920 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
|
||||
description: |
|
||||
ExynosAuto v920 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-top
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
- samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-peric0
|
||||
- samsung,exynosautov920-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_PERICn NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov920-cmu-misc
|
||||
- samsung,exynosautov920-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov920-cmu-hsi1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (38.4 MHz)
|
||||
- description: CMU_HSI1 NOC clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: usbdrd
|
||||
- const: mmc_card
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_PERIC0
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov920.h>
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
||||
reg = <0x10800000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
|
||||
clock-names = "oscclk",
|
||||
"noc",
|
||||
"ip";
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,37 +0,0 @@
|
||||
BCM2836 per-CPU interrupt controller
|
||||
|
||||
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
|
||||
events, and SMP IPIs. One of the CPUs may receive interrupts for the
|
||||
peripheral (GPU) events, which chain to the BCM2835-style interrupt
|
||||
controller.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "brcm,bcm2836-l1-intc"
|
||||
- reg: Specifies base physical address and size of the
|
||||
registers
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 2
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
|
||||
0: CNTPSIRQ
|
||||
1: CNTPNSIRQ
|
||||
2: CNTHPIRQ
|
||||
3: CNTVIRQ
|
||||
8: GPU_FAST
|
||||
9: PMU_FAST
|
||||
|
||||
Example:
|
||||
|
||||
local_intc: local_intc {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x40000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&local_intc>;
|
||||
};
|
||||
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: BCM2836 per-CPU interrupt controller
|
||||
|
||||
maintainers:
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
|
||||
|
||||
description:
|
||||
The BCM2836 has a per-cpu interrupt controller for the timer, PMU
|
||||
events, and SMP IPIs. One of the CPUs may receive interrupts for the
|
||||
peripheral (GPU) events, which chain to the BCM2835-style interrupt
|
||||
controller.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2836-l1-intc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
local_intc: interrupt-controller@40000000 {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x40000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&local_intc>;
|
||||
};
|
||||
...
|
||||
@ -67,6 +67,7 @@ properties:
|
||||
- allwinner,sun20i-d1-plic
|
||||
- sophgo,cv1800b-plic
|
||||
- sophgo,cv1812h-plic
|
||||
- sophgo,sg2002-plic
|
||||
- sophgo,sg2042-plic
|
||||
- thead,th1520-plic
|
||||
- const: thead,c900-plic
|
||||
|
||||
@ -1,178 +0,0 @@
|
||||
* Atmel AT91 Pinmux Controller
|
||||
|
||||
The AT91 Pinmux Controller, enables the IC
|
||||
to share one PAD to several functional blocks. The sharing is done by
|
||||
multiplexing the PAD input/output signals. For each PAD there are up to
|
||||
8 muxing options (called periph modes). Since different modules require
|
||||
different PAD settings (like pull up, keeper, etc) the controller controls
|
||||
also the PAD settings parameters.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Atmel AT91 pin configuration node is a node of a group of pins which can be
|
||||
used for a specific device or function. This node represents both mux and config
|
||||
of the pins in that group. The 'pins' selects the function mode(also named pin
|
||||
mode) this pin can work on and the 'config' configures various pad settings
|
||||
such as pull-up, multi drive, etc.
|
||||
|
||||
Required properties for iomux controller:
|
||||
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
|
||||
or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
|
||||
or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
|
||||
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
|
||||
configured in this periph mode. All the periph and bank need to be describe.
|
||||
|
||||
How to create such array:
|
||||
|
||||
Each column will represent the possible peripheral of the pinctrl
|
||||
Each line will represent a pio bank
|
||||
|
||||
Take an example on the 9260
|
||||
Peripheral: 2 ( A and B)
|
||||
Bank: 3 (A, B and C)
|
||||
=>
|
||||
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
|
||||
0xffffffff 0x7fff3ccf /* pioB */
|
||||
0xffffffff 0x007fffff /* pioC */
|
||||
|
||||
For each peripheral/bank we will describe in a u32 if a pin can be
|
||||
configured in it by putting 1 to the pin bit (1 << pin)
|
||||
|
||||
Let's take the pioA on peripheral B
|
||||
From the datasheet Table 10-2.
|
||||
Peripheral B
|
||||
PA0 MCDB0
|
||||
PA1 MCCDB
|
||||
PA2
|
||||
PA3 MCDB3
|
||||
PA4 MCDB2
|
||||
PA5 MCDB1
|
||||
PA6
|
||||
PA7
|
||||
PA8
|
||||
PA9
|
||||
PA10 ETX2
|
||||
PA11 ETX3
|
||||
PA12
|
||||
PA13
|
||||
PA14
|
||||
PA15
|
||||
PA16
|
||||
PA17
|
||||
PA18
|
||||
PA19
|
||||
PA20
|
||||
PA21
|
||||
PA22 ETXER
|
||||
PA23 ETX2
|
||||
PA24 ETX3
|
||||
PA25 ERX2
|
||||
PA26 ERX3
|
||||
PA27 ERXCK
|
||||
PA28 ECRS
|
||||
PA29 ECOL
|
||||
PA30 RXD4
|
||||
PA31 TXD4
|
||||
|
||||
=> 0xffc00c3b
|
||||
|
||||
Required properties for pin configuration node:
|
||||
- atmel,pins: 4 integers array, represents a group of pins mux and config
|
||||
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
|
||||
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
|
||||
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
|
||||
|
||||
Bits used for CONFIG:
|
||||
PULL_UP (1 << 0): indicate this pin needs a pull up.
|
||||
MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
|
||||
Multi-drive is equivalent to open-drain type output.
|
||||
DEGLITCH (1 << 2): indicate this pin needs deglitch.
|
||||
PULL_DOWN (1 << 3): indicate this pin needs a pull down.
|
||||
DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
|
||||
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
|
||||
following values:
|
||||
00 - No change (reset state value kept)
|
||||
01 - Low
|
||||
10 - Medium
|
||||
11 - High
|
||||
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
|
||||
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
|
||||
SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
|
||||
DEBOUNCE (1 << 16): indicate this pin needs debounce.
|
||||
DEBOUNCE_VAL (0x3fff << 17): debounce value.
|
||||
|
||||
NOTE:
|
||||
Some requirements for using atmel,at91rm9200-pinctrl binding:
|
||||
1. We have pin function node defined under at91 controller node to represent
|
||||
what pinmux functions this SoC supports.
|
||||
2. The driver can use the function node's name and pin configuration node's
|
||||
name describe the pin function and group hierarchy.
|
||||
For example, Linux at91 pinctrl driver takes the function node's name
|
||||
as the function name and pin configuration node's name as group name to
|
||||
create the map table.
|
||||
3. Each pin configuration node should have a phandle, devices can set pins
|
||||
configurations by referring to the phandle of that pin configuration node.
|
||||
4. The gpio controller must be describe in the pinctrl simple-bus.
|
||||
|
||||
For each bank the required properties are:
|
||||
- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
|
||||
"microchip,sam9x60-gpio"
|
||||
or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- interrupts: interrupt outputs from the controller
|
||||
- interrupt-controller: marks the device node as an interrupt controller
|
||||
- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
|
||||
for more details.
|
||||
- gpio-controller
|
||||
- #gpio-cells: should be 2; the first cell is the GPIO number and the second
|
||||
cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
|
||||
- clocks: bank clock
|
||||
|
||||
Examples:
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
reg = <0xfffff400 0x600>;
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
|
||||
};
|
||||
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
|
||||
0xffffffff 0x7fff3ccf /* pioB */
|
||||
0xffffffff 0x007fffff /* pioC */
|
||||
>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<1 14 0x1 0x0 /* PB14 periph A */
|
||||
1 15 0x1 0x1>; /* PB15 periph A with pullup */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
};
|
||||
@ -0,0 +1,184 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PIO3 Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Manikandan Muralidharan <manikandan.m@microchip.com>
|
||||
|
||||
description:
|
||||
The AT91 Pinmux Controller, enables the IC to share one PAD to several
|
||||
functional blocks. The sharing is done by multiplexing the PAD input/output
|
||||
signals. For each PAD there are up to 8 muxing options (called periph modes).
|
||||
Since different modules require different PAD settings (like pull up, keeper,
|
||||
etc) the controller controls also the PAD settings parameters.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91rm9200-pinctrl
|
||||
- atmel,at91sam9x5-pinctrl
|
||||
- atmel,sama5d3-pinctrl
|
||||
- microchip,sam9x60-pinctrl
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x7-pinctrl
|
||||
- const: microchip,sam9x60-pinctrl
|
||||
- const: simple-mfd
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
atmel,mux-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Array of mask (periph per bank) to describe if a pin can be
|
||||
configured in this periph mode. All the periph and bank need to
|
||||
be described.
|
||||
|
||||
#How to create such array:
|
||||
|
||||
Each column will represent the possible peripheral of the pinctrl
|
||||
Each line will represent a pio bank
|
||||
|
||||
#Example:
|
||||
|
||||
In at91sam9260.dtsi,
|
||||
Peripheral: 2 ( A and B)
|
||||
Bank: 3 (A, B and C)
|
||||
|
||||
# A B
|
||||
0xffffffff 0xffc00c3b # pioA
|
||||
0xffffffff 0x7fff3ccf # pioB
|
||||
0xffffffff 0x007fffff # pioC
|
||||
|
||||
For each peripheral/bank we will describe in a u32 if a pin can be
|
||||
configured in it by putting 1 to the pin bit (1 << pin)
|
||||
|
||||
Let's take the pioA on peripheral B whose value is 0xffc00c3b
|
||||
From the datasheet Table 10-2.
|
||||
Peripheral B
|
||||
PA0 MCDB0
|
||||
PA1 MCCDB
|
||||
PA2
|
||||
PA3 MCDB3
|
||||
PA4 MCDB2
|
||||
PA5 MCDB1
|
||||
PA6
|
||||
PA7
|
||||
PA8
|
||||
PA9
|
||||
PA10 ETX2
|
||||
PA11 ETX3
|
||||
PA12
|
||||
PA13
|
||||
PA14
|
||||
PA15
|
||||
PA16
|
||||
PA17
|
||||
PA18
|
||||
PA19
|
||||
PA20
|
||||
PA21
|
||||
PA22 ETXER
|
||||
PA23 ETX2
|
||||
PA24 ETX3
|
||||
PA25 ERX2
|
||||
PA26 ERX3
|
||||
PA27 ERXCK
|
||||
PA28 ECRS
|
||||
PA29 ECOL
|
||||
PA30 RXD4
|
||||
PA31 TXD4
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ranges
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- atmel,mux-mask
|
||||
|
||||
patternProperties:
|
||||
'gpio@[0-9a-f]+$':
|
||||
$ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
|
||||
unevaluatedProperties: false
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
additionalProperties:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
atmel,pins:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Each entry consists of 4 integers and represents the pins
|
||||
mux and config setting.The format is
|
||||
atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
|
||||
Supported pin number and mux varies for different SoCs, and
|
||||
are defined in <include/dt-bindings/pinctrl/at91.h>.
|
||||
items:
|
||||
items:
|
||||
- description:
|
||||
Pin bank
|
||||
- description:
|
||||
Pin bank index
|
||||
- description:
|
||||
Peripheral function
|
||||
- description:
|
||||
Pad configuration
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x600>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
|
||||
0xffffffff 0x7fff3ccf /* pioB */
|
||||
0xffffffff 0x007fffff /* pioC */
|
||||
>;
|
||||
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
- renesas,r8a7745-sysc # RZ/G1E
|
||||
- renesas,r8a77470-sysc # RZ/G1C
|
||||
- renesas,r8a774a1-sysc # RZ/G2M
|
||||
- renesas,r8a774a3-sysc # RZ/G2M v3.0
|
||||
- renesas,r8a774b1-sysc # RZ/G2N
|
||||
- renesas,r8a774c0-sysc # RZ/G2E
|
||||
- renesas,r8a774e1-sysc # RZ/G2H
|
||||
|
||||
@ -29,6 +29,7 @@ properties:
|
||||
- renesas,r8a7745-rst # RZ/G1E
|
||||
- renesas,r8a77470-rst # RZ/G1C
|
||||
- renesas,r8a774a1-rst # RZ/G2M
|
||||
- renesas,r8a774a3-rst # RZ/G2M v3.0
|
||||
- renesas,r8a774b1-rst # RZ/G2N
|
||||
- renesas,r8a774c0-rst # RZ/G2E
|
||||
- renesas,r8a774e1-rst # RZ/G2H
|
||||
|
||||
@ -26,6 +26,11 @@ properties:
|
||||
- enum:
|
||||
- sophgo,huashan-pi
|
||||
- const: sophgo,cv1812h
|
||||
- items:
|
||||
- enum:
|
||||
- sipeed,licheerv-nano-b
|
||||
- const: sipeed,licheerv-nano
|
||||
- const: sophgo,sg2002
|
||||
- items:
|
||||
- enum:
|
||||
- milkv,pioneer
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2711-avs-monitor.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom AVS Monitor
|
||||
|
||||
maintainers:
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: brcm,bcm2711-avs-monitor
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
thermal:
|
||||
$ref: /schemas/thermal/brcm,avs-ro-thermal.yaml
|
||||
description: Broadcom AVS ring oscillator thermal
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- thermal
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
avs-monitor@7d5d2000 {
|
||||
compatible = "brcm,bcm2711-avs-monitor", "syscon", "simple-mfd";
|
||||
reg = <0x7d5d2000 0xf00>;
|
||||
|
||||
thermal: thermal {
|
||||
compatible = "brcm,bcm2711-thermal";
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -127,6 +127,18 @@ properties:
|
||||
- const: hoperun,hihope-rzg2m
|
||||
- const: renesas,r8a774a1
|
||||
|
||||
- description: RZ/G2M v3.0 (R8A774A3)
|
||||
items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform
|
||||
- const: renesas,r8a774a3
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
|
||||
- const: hoperun,hihope-rzg2m
|
||||
- const: renesas,r8a774a3
|
||||
|
||||
- description: RZ/G2N (R8A774B1)
|
||||
items:
|
||||
- enum:
|
||||
@ -515,6 +527,8 @@ properties:
|
||||
|
||||
- description: RZ/V2H(P) (R9A09G057)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,rzv2h-evk # RZ/V2H EVK
|
||||
- enum:
|
||||
- renesas,r9a09g057h41 # RZ/V2H
|
||||
- renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
|
||||
|
||||
@ -14,6 +14,7 @@ properties:
|
||||
items:
|
||||
- const: ti,am654-serdes-ctrl
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -31,7 +32,7 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
clock@4080 {
|
||||
compatible = "ti,am654-serdes-ctrl", "syscon";
|
||||
compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
|
||||
reg = <0x4080 0x4>;
|
||||
|
||||
mux-controller {
|
||||
|
||||
@ -1,22 +0,0 @@
|
||||
BCM2835 System Timer
|
||||
|
||||
The System Timer peripheral provides four 32-bit timer channels and a
|
||||
single 64-bit free running counter. Each channel has an output compare
|
||||
register, which is compared against the 32 least significant bits of the
|
||||
free running counter values, and generates an interrupt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-system-timer"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 4 interrupt sinks; one per timer channel.
|
||||
- clock-frequency : The frequency of the clock that drives the counter, in Hz.
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: BCM2835 System Timer
|
||||
|
||||
maintainers:
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
|
||||
|
||||
description:
|
||||
The System Timer peripheral provides four 32-bit timer channels and a
|
||||
single 64-bit free running counter. Each channel has an output compare
|
||||
register, which is compared against the 32 least significant bits of the
|
||||
free running counter values, and generates an interrupt.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-system-timer
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: System Timer Compare 0 match (used by VideoCore GPU)
|
||||
- description: System Timer Compare 1 match (usable for ARM core)
|
||||
- description: System Timer Compare 2 match (used by VideoCore GPU)
|
||||
- description: System Timer Compare 3 match (usable for ARM core)
|
||||
|
||||
clock-frequency: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer@7e003000 {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
...
|
||||
@ -804,6 +804,8 @@ patternProperties:
|
||||
description: Lantiq Semiconductor
|
||||
"^lattice,.*":
|
||||
description: Lattice Semiconductor
|
||||
"^lckfb,.*":
|
||||
description: Shenzhen JLC Technology Group Co., Ltd.
|
||||
"^lctech,.*":
|
||||
description: Shenzen LC Technology Co., Ltd.
|
||||
"^leadtek,.*":
|
||||
|
||||
@ -23303,9 +23303,8 @@ TQ SYSTEMS BOARD & DRIVER SUPPORT
|
||||
L: linux@ew.tq-group.com
|
||||
S: Supported
|
||||
W: https://www.tq-group.com/en/products/tq-embedded/
|
||||
F: arch/arm/boot/dts/imx*mba*.dts*
|
||||
F: arch/arm/boot/dts/imx*tqma*.dts*
|
||||
F: arch/arm/boot/dts/mba*.dtsi
|
||||
F: arch/arm/boot/dts/nxp/imx/*mba*.dts*
|
||||
F: arch/arm/boot/dts/nxp/imx/*tqma*.dts*
|
||||
F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
|
||||
F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
|
||||
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*
|
||||
|
||||
@ -34,8 +34,6 @@
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <100>;
|
||||
|
||||
pal-switch {
|
||||
|
||||
@ -103,7 +103,7 @@
|
||||
};
|
||||
|
||||
/* PMU with one IRQ line per core */
|
||||
pmu: pmu@0 {
|
||||
pmu: pmu {
|
||||
compatible = "arm,arm11mpcore-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@ -92,7 +92,7 @@
|
||||
<0x1f000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller {
|
||||
L2: cache-controller@1f002000 {
|
||||
compatible = "arm,l220-cache";
|
||||
reg = <0x1f002000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
|
||||
@ -40,7 +40,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
pmu: pmu@0 {
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -97,7 +97,7 @@
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
pmu: pmu@0 {
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-bmc-bytedance-g220a.dtb \
|
||||
aspeed-bmc-delta-ahe50dc.dtb \
|
||||
aspeed-bmc-facebook-bletchley.dtb \
|
||||
aspeed-bmc-facebook-catalina.dtb \
|
||||
aspeed-bmc-facebook-cmm.dtb \
|
||||
aspeed-bmc-facebook-elbert.dtb \
|
||||
aspeed-bmc-facebook-fuji.dtb \
|
||||
@ -32,8 +33,10 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-bmc-facebook-yamp.dtb \
|
||||
aspeed-bmc-facebook-yosemitev2.dtb \
|
||||
aspeed-bmc-facebook-yosemite4.dtb \
|
||||
aspeed-bmc-ibm-blueridge.dtb \
|
||||
aspeed-bmc-ibm-bonnell.dtb \
|
||||
aspeed-bmc-ibm-everest.dtb \
|
||||
aspeed-bmc-ibm-fuji.dtb \
|
||||
aspeed-bmc-ibm-rainier.dtb \
|
||||
aspeed-bmc-ibm-rainier-1s4u.dtb \
|
||||
aspeed-bmc-ibm-rainier-4u.dtb \
|
||||
|
||||
@ -49,6 +49,11 @@
|
||||
*/
|
||||
i2c80 = &nvme_m2_0;
|
||||
i2c81 = &nvme_m2_1;
|
||||
|
||||
/*
|
||||
* i2c bus 82 assigned to OCP slot
|
||||
*/
|
||||
i2c82 = &ocpslot;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -420,6 +425,17 @@
|
||||
reg = <0x70>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
ocpslot: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
ocpslot_temp: temperature-sensor@1f {
|
||||
compatible = "ti,tmp421";
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
nvmeslot_0_7: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -672,10 +688,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&pwm_tacho {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -15,6 +15,32 @@
|
||||
serial7 = &uart8;
|
||||
serial8 = &uart9;
|
||||
|
||||
/*
|
||||
* I2C temperature alias port
|
||||
*/
|
||||
i2c20 = &i2c4_bus70_chn0;
|
||||
i2c21 = &i2c4_bus70_chn1;
|
||||
i2c22 = &i2c4_bus70_chn2;
|
||||
i2c23 = &i2c4_bus70_chn3;
|
||||
|
||||
/*
|
||||
* i2c bus 30-31 assigned to OCP slot 0-1
|
||||
*/
|
||||
i2c30 = &ocpslot_0;
|
||||
i2c31 = &ocpslot_1;
|
||||
|
||||
/*
|
||||
* i2c bus 32-33 assigned to Riser slot 0-1
|
||||
*/
|
||||
i2c32 = &i2c_riser0;
|
||||
i2c33 = &i2c_riser1;
|
||||
|
||||
/*
|
||||
* i2c bus 38-39 assigned to FRU on Riser slot 0-1
|
||||
*/
|
||||
i2c38 = &i2c_riser0_chn_0;
|
||||
i2c39 = &i2c_riser1_chn_0;
|
||||
|
||||
/*
|
||||
* I2C NVMe alias port
|
||||
*/
|
||||
@ -87,6 +113,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
/*
|
||||
* Use gpio-leds to configure GPIOW5 (bmc-ready) pin to be reseted when
|
||||
* watchdog timeout.
|
||||
*/
|
||||
led-bmc-ready {
|
||||
gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>;
|
||||
};
|
||||
|
||||
led-sw-heartbeat {
|
||||
gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-identify {
|
||||
gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-fault {
|
||||
gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-fan-fault {
|
||||
gpios = <&gpio_expander1 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-psu-fault {
|
||||
gpios = <&gpio_expander1 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
voltage_mon_reg: voltage-mon-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ltc2497_reg";
|
||||
@ -515,6 +572,80 @@
|
||||
#size-cells = <0>;
|
||||
reg = <0x70>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
ocpslot_0: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
ocpslot_0_temp: temperature-sensor@1f {
|
||||
compatible = "ti,tmp421";
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
ocpslot_1: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1>;
|
||||
|
||||
ocpslot_1_temp: temperature-sensor@1f {
|
||||
compatible = "ti,tmp421";
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_riser0: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
i2c-mux@72 {
|
||||
compatible = "nxp,pca9546";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
i2c_riser0_chn_0: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c_riser1: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
i2c-mux@72 {
|
||||
compatible = "nxp,pca9546";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x72>;
|
||||
i2c-mux-idle-disconnect;
|
||||
|
||||
i2c_riser1_chn_0: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -790,6 +921,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c11 {
|
||||
status = "okay";
|
||||
ssif-bmc@10 {
|
||||
@ -812,6 +947,25 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c15 {
|
||||
status = "okay";
|
||||
gpio_expander1: gpio-expander@22 {
|
||||
compatible = "nxp,pca9535";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"fan-fault","psu-fault",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","";
|
||||
};
|
||||
};
|
||||
|
||||
&adc0 {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -200,10 +200,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pin_gpio_c7 {
|
||||
gpio-hog;
|
||||
|
||||
@ -110,11 +110,15 @@
|
||||
compatible = "st,24c128", "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eth0_macaddress: macaddress@3f80 {
|
||||
reg = <0x3f80 6>;
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eth0_macaddress: macaddress@3f80 {
|
||||
reg = <0x3f80 6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -254,10 +254,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&vhub {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
1110
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
Normal file
1110
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
Normal file
File diff suppressed because it is too large
Load Diff
@ -201,7 +201,7 @@
|
||||
&i2c12 {
|
||||
status = "okay";
|
||||
temperature-sensor@4f {
|
||||
compatible = "lm75";
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4f>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -20,10 +20,6 @@
|
||||
i2c21 = &imux21;
|
||||
i2c22 = &imux22;
|
||||
i2c23 = &imux23;
|
||||
i2c24 = &imux24;
|
||||
i2c25 = &imux25;
|
||||
i2c26 = &imux26;
|
||||
i2c27 = &imux27;
|
||||
i2c28 = &imux28;
|
||||
i2c29 = &imux29;
|
||||
i2c30 = &imux30;
|
||||
@ -70,19 +66,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
spi_gpio: spi-gpio {
|
||||
spi_gpio: spi {
|
||||
status = "okay";
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
|
||||
gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
|
||||
gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
|
||||
sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
|
||||
miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
|
||||
|
||||
tpmdev@0 {
|
||||
tpm@0 {
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
spi-max-frequency = <33000000>;
|
||||
reg = <0>;
|
||||
@ -137,7 +133,6 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rmii4_default>;
|
||||
use-ncsi;
|
||||
mellanox,multi-host;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
@ -198,6 +193,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
@ -224,6 +248,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
@ -276,11 +329,15 @@
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
power-monitor@22 {
|
||||
compatible = "lltc,ltc4286";
|
||||
reg = <0x22>;
|
||||
adi,vrange-low-enable;
|
||||
shunt-resistor-micro-ohms = <500>;
|
||||
power-monitor@44 {
|
||||
compatible = "lltc,ltc4287";
|
||||
reg = <0x44>;
|
||||
shunt-resistor-micro-ohms = <250>;
|
||||
};
|
||||
|
||||
power-monitor@40 {
|
||||
compatible = "infineon,xdp710";
|
||||
reg = <0x40>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -321,6 +378,14 @@
|
||||
&i2c9 {
|
||||
status = "okay";
|
||||
|
||||
mctp-controller;
|
||||
multi-master;
|
||||
|
||||
mctp@10 {
|
||||
compatible = "mctp-i2c-controller";
|
||||
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
|
||||
};
|
||||
|
||||
gpio@30 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x30>;
|
||||
@ -340,33 +405,6 @@
|
||||
"","","","";
|
||||
};
|
||||
|
||||
i2c-mux@71 {
|
||||
compatible = "nxp,pca9546";
|
||||
reg = <0x71>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
imux24: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
imux25: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
imux26: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
imux27: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
// PTTV FRU
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c64";
|
||||
@ -376,6 +414,31 @@
|
||||
|
||||
&i2c11 {
|
||||
status = "okay";
|
||||
|
||||
gpio@30 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x30>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio@31 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x31>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names =
|
||||
"","","","",
|
||||
"","","presence-cmm","",
|
||||
"","","","",
|
||||
"","","","";
|
||||
};
|
||||
|
||||
// Aegis FRU
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
@ -399,6 +462,30 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
power-monitor@61 {
|
||||
compatible = "isil,isl69260";
|
||||
reg = <0x61>;
|
||||
};
|
||||
power-monitor@62 {
|
||||
compatible = "isil,isl69260";
|
||||
reg = <0x62>;
|
||||
};
|
||||
power-monitor@63 {
|
||||
compatible = "isil,isl69260";
|
||||
reg = <0x63>;
|
||||
};
|
||||
power-monitor@64 {
|
||||
compatible = "infineon,xdpe152c4";
|
||||
reg = <0x64>;
|
||||
};
|
||||
power-monitor@66 {
|
||||
compatible = "infineon,xdpe152c4";
|
||||
reg = <0x66>;
|
||||
};
|
||||
power-monitor@68 {
|
||||
compatible = "infineon,xdpe152c4";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
imux29: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
@ -497,13 +584,14 @@
|
||||
/*O0-O7*/ "","","","","","","","",
|
||||
/*P0-P7*/ "power-button","power-host-control",
|
||||
"reset-button","","led-power","","","",
|
||||
/*Q0-Q7*/ "","","","","","","","",
|
||||
/*Q0-Q7*/ "","","","","","power-chassis-control","","",
|
||||
/*R0-R7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","","","","","",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","led-identify-gate","",
|
||||
/*V0-V7*/ "","","","",
|
||||
"rtc-battery-voltage-read-enable","","","",
|
||||
"rtc-battery-voltage-read-enable","",
|
||||
"power-chassis-good","",
|
||||
/*W0-W7*/ "","","","","","","","",
|
||||
/*X0-X7*/ "","","","","","","","",
|
||||
/*Y0-Y7*/ "","","","","","","","",
|
||||
@ -521,7 +609,6 @@
|
||||
|
||||
&sgpiom0 {
|
||||
status = "okay";
|
||||
max-ngpios = <128>;
|
||||
ngpios = <128>;
|
||||
bus-frequency = <2000000>;
|
||||
gpio-line-names =
|
||||
|
||||
@ -11,7 +11,8 @@
|
||||
compatible = "facebook,minerva-cmc", "aspeed,ast2600";
|
||||
|
||||
aliases {
|
||||
serial5 = &uart5;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
/*
|
||||
* PCA9548 (2-0077) provides 8 channels connecting to
|
||||
* 6 pcs of FCB (Fan Controller Board).
|
||||
@ -22,6 +23,8 @@
|
||||
i2c19 = &imux19;
|
||||
i2c20 = &imux20;
|
||||
i2c21 = &imux21;
|
||||
|
||||
spi1 = &spi_gpio;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -43,11 +46,54 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-fan-fault {
|
||||
label = "led-fan-fault";
|
||||
led-0 {
|
||||
label = "bmc_heartbeat_amber";
|
||||
gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
label = "fp_id_amber";
|
||||
default-state = "off";
|
||||
gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-2 {
|
||||
label = "power_blue";
|
||||
default-state = "off";
|
||||
gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-3 {
|
||||
label = "fan_status_led";
|
||||
gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
label = "fan_fault_led_n";
|
||||
gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
spi_gpio: spi {
|
||||
status = "okay";
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
|
||||
miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
|
||||
|
||||
tpm@0 {
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
spi-max-frequency = <33000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -77,6 +123,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mdio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
@ -94,10 +144,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sgpiom0 {
|
||||
status = "okay";
|
||||
ngpios = <128>;
|
||||
@ -119,14 +165,15 @@
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-monitor@67 {
|
||||
compatible = "adi,ltc2945";
|
||||
reg = <0x67>;
|
||||
power-monitor@44 {
|
||||
compatible = "lltc,ltc4287";
|
||||
reg = <0x44>;
|
||||
shunt-resistor-micro-ohms = <2000>;
|
||||
};
|
||||
|
||||
power-monitor@68 {
|
||||
compatible = "adi,ltc2945";
|
||||
reg = <0x68>;
|
||||
power-monitor@43 {
|
||||
compatible = "infineon,xdp710";
|
||||
reg = <0x43>;
|
||||
};
|
||||
|
||||
leds_gpio: gpio@19 {
|
||||
@ -145,9 +192,9 @@
|
||||
reg = <0x4b>;
|
||||
};
|
||||
|
||||
temperature-sensor@48 {
|
||||
temperature-sensor@4f {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x48>;
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
eeprom@54 {
|
||||
@ -182,6 +229,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
imux17: i2c@1 {
|
||||
@ -200,6 +276,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
imux18: i2c@2 {
|
||||
@ -218,6 +323,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
imux19: i2c@3 {
|
||||
@ -236,9 +370,38 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
imux20: i2c@4 {
|
||||
imux20: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
@ -254,9 +417,37 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
imux21: i2c@5 {
|
||||
imux21: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
@ -272,6 +463,34 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@41 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@44 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
power-sensor@45 {
|
||||
compatible = "ti,ina238";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
temperature-sensor@4b {
|
||||
compatible = "ti,tmp75";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -302,14 +521,16 @@
|
||||
|
||||
&i2c9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
};
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
&i2c11 {
|
||||
status = "okay";
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
@ -338,6 +559,11 @@
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x56>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc0 {
|
||||
@ -355,6 +581,10 @@
|
||||
pinctrl-0 = <&pinctrl_adc10_default>;
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -381,12 +611,12 @@
|
||||
/*N0-N7*/ "","","","","","","","",
|
||||
/*O0-O7*/ "","","","","","","","",
|
||||
/*P0-P7*/ "","","","","","","","",
|
||||
/*Q0-Q7*/ "","","","","","","","",
|
||||
/*Q0-Q7*/ "","","","","","power-chassis-control","","",
|
||||
/*R0-R7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","","","","","",
|
||||
/*S0-S7*/ "","","","","","","","host0-ready",
|
||||
/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
|
||||
/*V0-V7*/ "","","","","BAT_DETECT","","","",
|
||||
/*V0-V7*/ "","","","","BAT_DETECT","","power-chassis-good","",
|
||||
/*W0-W7*/ "","","","","","","","",
|
||||
/*X0-X7*/ "","","BLADE_UART_SEL3","","","","","",
|
||||
/*Y0-Y7*/ "","","","","","","","",
|
||||
@ -397,118 +627,118 @@
|
||||
gpio-line-names =
|
||||
/*"input pin","output pin"*/
|
||||
/*A0 - A7*/
|
||||
"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN",
|
||||
"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN",
|
||||
"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN",
|
||||
"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN",
|
||||
"PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN",
|
||||
"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN",
|
||||
"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN",
|
||||
"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN",
|
||||
"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
|
||||
"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
|
||||
"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
|
||||
"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
|
||||
"PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN_N",
|
||||
"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
|
||||
"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
|
||||
"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
|
||||
/*B0 - B7*/
|
||||
"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN",
|
||||
"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN",
|
||||
"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN",
|
||||
"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN",
|
||||
"PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN",
|
||||
"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN",
|
||||
"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN",
|
||||
"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN",
|
||||
"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
|
||||
"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
|
||||
"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
|
||||
"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
|
||||
"PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN_N",
|
||||
"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
|
||||
"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
|
||||
"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
|
||||
/*C0 - C7*/
|
||||
"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN",
|
||||
"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN",
|
||||
"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN",
|
||||
"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN",
|
||||
"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN",
|
||||
"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN",
|
||||
"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN",
|
||||
"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN",
|
||||
"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
|
||||
"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
|
||||
"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
|
||||
"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
|
||||
"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
|
||||
"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
|
||||
"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
|
||||
"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
|
||||
/*D0 - D7*/
|
||||
"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN",
|
||||
"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN",
|
||||
"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE4_HSC_EN",
|
||||
"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE5_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE0_PWROK_L_BUF","PWREN_MTIA_BLADE6_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE1_PWROK_L_BUF","PWREN_MTIA_BLADE7_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE2_PWROK_L_BUF","PWREN_MTIA_BLADE8_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE3_PWROK_L_BUF","PWREN_MTIA_BLADE9_HSC_EN",
|
||||
"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
|
||||
"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
|
||||
"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
|
||||
"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
|
||||
/*E0 - E7*/
|
||||
"PWRGD_MTIA_BLADE4_PWROK_L_BUF","PWREN_MTIA_BLADE10_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE5_PWROK_L_BUF","PWREN_MTIA_BLADE11_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE6_PWROK_L_BUF","PWREN_MTIA_BLADE12_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE7_PWROK_L_BUF","PWREN_MTIA_BLADE13_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE8_PWROK_L_BUF","PWREN_MTIA_BLADE14_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE9_PWROK_L_BUF","PWREN_MTIA_BLADE15_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE10_PWROK_L_BUF","PWREN_NW_BLADE0_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE11_PWROK_L_BUF","PWREN_NW_BLADE1_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
|
||||
/*F0 - F7*/
|
||||
"PWRGD_MTIA_BLADE12_PWROK_L_BUF","PWREN_NW_BLADE2_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE13_PWROK_L_BUF","PWREN_NW_BLADE3_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE14_PWROK_L_BUF","PWREN_NW_BLADE4_HSC_EN",
|
||||
"PWRGD_MTIA_BLADE15_PWROK_L_BUF","PWREN_NW_BLADE5_HSC_EN",
|
||||
"PWRGD_NW_BLADE0_PWROK_L_BUF","PWREN_FCB_TOP_L_EN",
|
||||
"PWRGD_NW_BLADE1_PWROK_L_BUF","PWREN_FCB_TOP_R_EN",
|
||||
"PWRGD_NW_BLADE2_PWROK_L_BUF","PWREN_FCB_MIDDLE_L_EN",
|
||||
"PWRGD_NW_BLADE3_PWROK_L_BUF","PWREN_FCB_MIDDLE_R_EN",
|
||||
"PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
|
||||
"PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
|
||||
"PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
|
||||
"PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
|
||||
"PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
|
||||
"PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
|
||||
/*G0 - G7*/
|
||||
"PWRGD_NW_BLADE4_PWROK_L_BUF","PWREN_FCB_BOTTOM_L_EN",
|
||||
"PWRGD_NW_BLADE5_PWROK_L_BUF","PWREN_FCB_BOTTOM_R_EN",
|
||||
"PWRGD_FCB_TOP_0_PWROK_L_BUF","FM_CMM_AC_CYCLE_N",
|
||||
"PWRGD_FCB_TOP_1_PWROK_L_BUF","MGMT_SFP_TX_DIS",
|
||||
"PWRGD_FCB_MIDDLE_0_PWROK_L_BUF","",
|
||||
"PWRGD_FCB_MIDDLE_1_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE0_1_N",
|
||||
"PWRGD_FCB_BOTTOM_0_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE2_3_N",
|
||||
"PWRGD_FCB_BOTTOM_1_PWROK_L_BUF","RST_I2CRST_MTIA_BLADE4_5_N",
|
||||
"PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
|
||||
"PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
|
||||
"PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
|
||||
"PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
|
||||
"PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
|
||||
"PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
|
||||
"PWRGD_FCB_BOTTOM_1_PWROK_N","",
|
||||
"PWRGD_FCB_BOTTOM_0_PWROK_N","",
|
||||
/*H0 - H7*/
|
||||
"LEAK_DETECT_MTIA_BLADE0_N_BUF","RST_I2CRST_MTIA_BLADE6_7_N",
|
||||
"LEAK_DETECT_MTIA_BLADE1_N_BUF","RST_I2CRST_MTIA_BLADE8_9_N",
|
||||
"LEAK_DETECT_MTIA_BLADE2_N_BUF","RST_I2CRST_MTIA_BLADE10_11_N",
|
||||
"LEAK_DETECT_MTIA_BLADE3_N_BUF","RST_I2CRST_MTIA_BLADE12_13_N",
|
||||
"LEAK_DETECT_MTIA_BLADE4_N_BUF","RST_I2CRST_MTIA_BLADE14_15_N",
|
||||
"LEAK_DETECT_MTIA_BLADE5_N_BUF","RST_I2CRST_NW_BLADE0_1_2_N",
|
||||
"LEAK_DETECT_MTIA_BLADE6_N_BUF","RST_I2CRST_NW_BLADE3_4_5_N",
|
||||
"LEAK_DETECT_MTIA_BLADE7_N_BUF","RST_I2CRST_FCB_N",
|
||||
"LEAK_DETECT_MTIA_BLADE0_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE1_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE2_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE3_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE4_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE5_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE6_N","",
|
||||
"LEAK_DETECT_MTIA_BLADE7_N","",
|
||||
/*I0 - I7*/
|
||||
"LEAK_DETECT_MTIA_BLADE8_N_BUF","RST_I2CRST_FCB_B_L_N",
|
||||
"LEAK_DETECT_MTIA_BLADE9_N_BUF","RST_I2CRST_FCB_B_R_N",
|
||||
"LEAK_DETECT_MTIA_BLADE10_N_BUF","RST_I2CRST_FCB_M_L_N",
|
||||
"LEAK_DETECT_MTIA_BLADE11_N_BUF","RST_I2CRST_FCB_M_R_N",
|
||||
"LEAK_DETECT_MTIA_BLADE12_N_BUF","RST_I2CRST_FCB_T_L_N",
|
||||
"LEAK_DETECT_MTIA_BLADE13_N_BUF","RST_I2CRST_FCB_T_R_N",
|
||||
"LEAK_DETECT_MTIA_BLADE14_N_BUF","BMC_READY",
|
||||
"LEAK_DETECT_MTIA_BLADE15_N_BUF","wFM_88E6393X_BIN_UPDATE_EN_N",
|
||||
"LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
|
||||
"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
|
||||
"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
|
||||
"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
|
||||
"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
|
||||
"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
|
||||
"LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
|
||||
"LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
|
||||
/*J0 - J7*/
|
||||
"LEAK_DETECT_NW_BLADE0_N_BUF","WATER_VALVE_CLOSED_N",
|
||||
"LEAK_DETECT_NW_BLADE1_N_BUF","",
|
||||
"LEAK_DETECT_NW_BLADE2_N_BUF","",
|
||||
"LEAK_DETECT_NW_BLADE3_N_BUF","",
|
||||
"LEAK_DETECT_NW_BLADE4_N_BUF","",
|
||||
"LEAK_DETECT_NW_BLADE5_N_BUF","",
|
||||
"MTIA_BLADE0_STATUS_LED","",
|
||||
"MTIA_BLADE1_STATUS_LED","",
|
||||
"LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
|
||||
"LEAK_DETECT_NW_BLADE1_N","",
|
||||
"LEAK_DETECT_NW_BLADE2_N","",
|
||||
"LEAK_DETECT_NW_BLADE3_N","",
|
||||
"LEAK_DETECT_NW_BLADE4_N","",
|
||||
"LEAK_DETECT_NW_BLADE5_N","",
|
||||
"PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
|
||||
/*K0 - K7*/
|
||||
"MTIA_BLADE2_STATUS_LED","",
|
||||
"MTIA_BLADE3_STATUS_LED","",
|
||||
"MTIA_BLADE4_STATUS_LED","",
|
||||
"MTIA_BLADE5_STATUS_LED","",
|
||||
"MTIA_BLADE6_STATUS_LED","",
|
||||
"MTIA_BLADE7_STATUS_LED","",
|
||||
"MTIA_BLADE8_STATUS_LED","",
|
||||
"MTIA_BLADE9_STATUS_LED","",
|
||||
"PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE6_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
|
||||
/*L0 - L7*/
|
||||
"MTIA_BLADE10_STATUS_LED","",
|
||||
"MTIA_BLADE11_STATUS_LED","",
|
||||
"MTIA_BLADE12_STATUS_LED","",
|
||||
"MTIA_BLADE13_STATUS_LED","",
|
||||
"MTIA_BLADE14_STATUS_LED","",
|
||||
"MTIA_BLADE15_STATUS_LED","",
|
||||
"NW_BLADE0_STATUS_LED","",
|
||||
"NW_BLADE1_STATUS_LED","",
|
||||
"PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
|
||||
"PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
|
||||
"PWRGD_NW_BLADE0_HSC_PWROK_N","",
|
||||
"PWRGD_NW_BLADE1_HSC_PWROK_N","",
|
||||
/*M0 - M7*/
|
||||
"NW_BLADE2_STATUS_LED","",
|
||||
"NW_BLADE3_STATUS_LED","",
|
||||
"NW_BLADE4_STATUS_LED","",
|
||||
"NW_BLADE5_STATUS_LED","",
|
||||
"PWRGD_NW_BLADE2_HSC_PWROK_N","",
|
||||
"PWRGD_NW_BLADE3_HSC_PWROK_N","",
|
||||
"PWRGD_NW_BLADE4_HSC_PWROK_N","",
|
||||
"PWRGD_NW_BLADE5_HSC_PWROK_N","",
|
||||
"RPU_READY","",
|
||||
"IT_GEAR_RPU_LINK_N","",
|
||||
"IT_GEAR_LEAK","",
|
||||
@ -516,28 +746,28 @@
|
||||
/*N0 - N7*/
|
||||
"VALVE_STS0","",
|
||||
"VALVE_STS1","",
|
||||
"VALVE_STS2","",
|
||||
"VALVE_STS3","",
|
||||
"CR_TOGGLE_BOOT_BUF_N","",
|
||||
"CMM_LC_RDY_LED_N","",
|
||||
"CMM_LC_UNRDY_LED_N","",
|
||||
"PCA9555_IRQ0_N","",
|
||||
"PCA9555_IRQ1_N","",
|
||||
"CR_TOGGLE_BOOT_N","",
|
||||
"IRQ_FCB_TOP0_N","",
|
||||
"IRQ_FCB_TOP1_N","",
|
||||
"CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
|
||||
/*O0 - O7*/
|
||||
"CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
|
||||
"BOT_BCB_CABLE_PRSNT_N","",
|
||||
"TOP_BCB_CABLE_PRSNT_N","",
|
||||
"CHASSIS0_LEAK_Q_N","",
|
||||
"CHASSIS1_LEAK_Q_N","",
|
||||
"LEAK0_DETECT","",
|
||||
"LEAK1_DETECT","",
|
||||
"MGMT_SFP_PRSNT_N","",
|
||||
"IRQ_FCB_MID0_N","",
|
||||
"IRQ_FCB_MID1_N","",
|
||||
"CHASSIS_LEAK0_DETECT_N","",
|
||||
"CHASSIS_LEAK1_DETECT_N","",
|
||||
"VALVE_RMON_A_1","",
|
||||
/*P0 - P7*/
|
||||
"MGMT_SFP_TX_FAULT","",
|
||||
"MGMT_SFP_RX_LOS","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","",
|
||||
"","";
|
||||
"VALVE_RMON_A_2","",
|
||||
"VALVE_RMON_B_1","",
|
||||
"VALVE_RMON_B_2","",
|
||||
"RPU_READY_SPARE","",
|
||||
"IT_GEAR_LEAK_SPARE","",
|
||||
"IT_GEAR_RPU_LINK_SPARE_N","",
|
||||
"IRQ_FCB_BOT0_N","",
|
||||
"IRQ_FCB_BOT0_N","";
|
||||
};
|
||||
|
||||
21
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts
Normal file
21
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// Copyright 2024 IBM Corp.
|
||||
/dts-v1/;
|
||||
|
||||
#include "aspeed-bmc-ibm-blueridge.dts"
|
||||
|
||||
/ {
|
||||
model = "Blueridge 4U";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
power-supply@6a {
|
||||
compatible = "ibm,cffps";
|
||||
reg = <0x6a>;
|
||||
};
|
||||
|
||||
power-supply@6b {
|
||||
compatible = "ibm,cffps";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
1686
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts
Normal file
1686
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts
Normal file
File diff suppressed because it is too large
Load Diff
@ -570,11 +570,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xdma {
|
||||
status = "okay";
|
||||
memory-region = <&vga_memory>;
|
||||
};
|
||||
|
||||
&kcs2 {
|
||||
status = "okay";
|
||||
aspeed,lpc-io-reg = <0xca8 0xcac>;
|
||||
|
||||
@ -2486,11 +2486,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xdma {
|
||||
status = "okay";
|
||||
memory-region = <&vga_memory>;
|
||||
};
|
||||
|
||||
&kcs2 {
|
||||
status = "okay";
|
||||
aspeed,lpc-io-reg = <0xca8 0xcac>;
|
||||
|
||||
3876
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts
Normal file
3876
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts
Normal file
File diff suppressed because it is too large
Load Diff
@ -1722,11 +1722,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xdma {
|
||||
status = "okay";
|
||||
memory-region = <&vga_memory>;
|
||||
};
|
||||
|
||||
&kcs2 {
|
||||
status = "okay";
|
||||
aspeed,lpc-io-reg = <0xca8 0xcac>;
|
||||
|
||||
@ -1138,7 +1138,7 @@
|
||||
reg = <6>;
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "ti,tmp423";
|
||||
compatible = "ti,tmp432";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
@ -1599,7 +1599,7 @@
|
||||
reg = <6>;
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "ti,tmp423";
|
||||
compatible = "ti,tmp432";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
@ -1615,7 +1615,7 @@
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "ti,tmp423";
|
||||
compatible = "ti,tmp432";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -814,10 +814,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
aspeed,reset-type = "none";
|
||||
aspeed,external-signal;
|
||||
|
||||
@ -123,10 +123,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&pwm_tacho {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -118,10 +118,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&pwm_tacho {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -263,10 +263,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pin_gpio_b0 {
|
||||
gpio-hog;
|
||||
|
||||
@ -284,10 +284,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&ibt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -289,10 +289,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&pwm_tacho {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -938,10 +938,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
aspeed,reset-type = "none";
|
||||
aspeed,external-signal;
|
||||
|
||||
@ -870,11 +870,6 @@
|
||||
<&pinctrl_lsirq_default>;
|
||||
};
|
||||
|
||||
&xdma {
|
||||
status = "okay";
|
||||
memory-region = <&vga_memory>;
|
||||
};
|
||||
|
||||
&kcs2 {
|
||||
status = "okay";
|
||||
aspeed,lpc-io-reg = <0xca8 0xcac>;
|
||||
|
||||
@ -661,10 +661,6 @@
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
aspeed,reset-type = "none";
|
||||
aspeed,external-signal;
|
||||
@ -696,9 +692,4 @@
|
||||
memory-region = <&video_engine_memory>;
|
||||
};
|
||||
|
||||
&xdma {
|
||||
status = "okay";
|
||||
memory-region = <&vga_memory>;
|
||||
};
|
||||
|
||||
#include "ibm-power9-dual.dtsi"
|
||||
|
||||
@ -466,8 +466,6 @@
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
|
||||
pinctrl_gpioh_unbiased: gpioi_unbiased {
|
||||
pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
|
||||
bias-disable;
|
||||
|
||||
@ -123,10 +123,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
};
|
||||
|
||||
&pwm_tacho {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -122,8 +122,8 @@
|
||||
reg = <0x1e6c0080 0x80>;
|
||||
};
|
||||
|
||||
cvic: copro-interrupt-controller@1e6c2000 {
|
||||
compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
|
||||
cvic: interrupt-controller@1e6c2000 {
|
||||
compatible = "aspeed,ast2400-cvic", "aspeed,cvic";
|
||||
valid-sources = <0x7fffffff>;
|
||||
reg = <0x1e6c2000 0x80>;
|
||||
};
|
||||
@ -230,6 +230,9 @@
|
||||
sram: sram@1e720000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x1e720000 0x8000>; // 32K
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
video: video@1e700000 {
|
||||
|
||||
@ -139,8 +139,8 @@
|
||||
reg = <0x1e6c0080 0x80>;
|
||||
};
|
||||
|
||||
cvic: copro-interrupt-controller@1e6c2000 {
|
||||
compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
|
||||
cvic: interrupt-controller@1e6c2000 {
|
||||
compatible = "aspeed,ast2500-cvic", "aspeed,cvic";
|
||||
valid-sources = <0xffffffff>;
|
||||
copro-sw-interrupts = <1>;
|
||||
reg = <0x1e6c2000 0x80>;
|
||||
@ -281,17 +281,6 @@
|
||||
interrupts = <0x19>;
|
||||
};
|
||||
|
||||
xdma: xdma@1e6e7000 {
|
||||
compatible = "aspeed,ast2500-xdma";
|
||||
reg = <0x1e6e7000 0x100>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
|
||||
resets = <&syscon ASPEED_RESET_XDMA>;
|
||||
interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
|
||||
aspeed,pcie-device = "bmc";
|
||||
aspeed,scu = <&syscon>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc: adc@1e6e9000 {
|
||||
compatible = "aspeed,ast2500-adc";
|
||||
reg = <0x1e6e9000 0xb0>;
|
||||
@ -314,6 +303,9 @@
|
||||
sram: sram@1e720000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x1e720000 0x9000>; // 36K
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
sdmmc: sd-controller@1e740000 {
|
||||
|
||||
@ -231,41 +231,33 @@
|
||||
resets = <&syscon ASPEED_RESET_MII>;
|
||||
};
|
||||
|
||||
mac0: ftgmac@1e660000 {
|
||||
mac0: ethernet@1e660000 {
|
||||
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
|
||||
reg = <0x1e660000 0x180>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac1: ftgmac@1e680000 {
|
||||
mac1: ethernet@1e680000 {
|
||||
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
|
||||
reg = <0x1e680000 0x180>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac2: ftgmac@1e670000 {
|
||||
mac2: ethernet@1e670000 {
|
||||
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
|
||||
reg = <0x1e670000 0x180>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac3: ftgmac@1e690000 {
|
||||
mac3: ethernet@1e690000 {
|
||||
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
|
||||
reg = <0x1e690000 0x180>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
|
||||
status = "disabled";
|
||||
@ -398,19 +390,6 @@
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
xdma: xdma@1e6e7000 {
|
||||
compatible = "aspeed,ast2600-xdma";
|
||||
reg = <0x1e6e7000 0x100>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
|
||||
resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
|
||||
reset-names = "device", "root-complex";
|
||||
interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
|
||||
aspeed,pcie-device = "bmc";
|
||||
aspeed,scu = <&syscon>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@1e6e9000 {
|
||||
compatible = "aspeed,ast2600-adc0";
|
||||
reg = <0x1e6e9000 0x100>;
|
||||
|
||||
1539
arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
Normal file
1539
arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -11,6 +11,10 @@
|
||||
model = "BCM21664 Garnet board";
|
||||
compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
|
||||
@ -1,21 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Copyright (C) 2014 Broadcom Corporation
|
||||
|
||||
#include <dt-bindings/clock/bcm21664.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "bcm2166x-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "BCM21664 SoC";
|
||||
compatible = "brcm,bcm21664";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -34,312 +24,46 @@
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@3ff00100 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x3ff01000 0x1000>,
|
||||
<0x3ff00100 0x100>;
|
||||
};
|
||||
|
||||
smc@3404e000 {
|
||||
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
|
||||
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
uartb: serial@3e000000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
reg = <0x3e000000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb2: serial@3e001000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
reg = <0x3e001000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb3: serial@3e002000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
reg = <0x3e002000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
L2: cache-controller@3ff20000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x3ff20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
brcm,resetmgr@35001f00 {
|
||||
compatible = "brcm,bcm21664-resetmgr";
|
||||
reg = <0x35001f00 0x24>;
|
||||
};
|
||||
|
||||
timer@35006000 {
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x35006000 0x1c>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
|
||||
gpio: gpio@35003000 {
|
||||
compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
|
||||
reg = <0x35003000 0x524>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sdio1: mmc@3f180000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f180000 0x801c>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: mmc@3f190000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f190000 0x801c>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: mmc@3f1a0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x801c>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio4: mmc@3f1b0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1b0000 0x801c>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc1: i2c@3e016000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e016000 0x70>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc2: i2c@3e017000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e017000 0x70>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc3: i2c@3e018000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e018000 0x70>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc4: i2c@3e01c000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e01c000 0x70>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* Fixed clocks are defined before CCUs whose
|
||||
* clocks may depend on them.
|
||||
*/
|
||||
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
root_ccu: root_ccu@35001000 {
|
||||
compatible = "brcm,bcm21664-root-ccu";
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu@35002000 {
|
||||
compatible = "brcm,bcm21664-aon-ccu";
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu@3f001000 {
|
||||
compatible = "brcm,bcm21664-master-ccu";
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"sdio1_sleep",
|
||||
"sdio2_sleep",
|
||||
"sdio3_sleep",
|
||||
"sdio4_sleep";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu@3e011000 {
|
||||
compatible = "brcm,bcm21664-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"bsc4";
|
||||
};
|
||||
};
|
||||
|
||||
usbotg: usb@3f120000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x3f120000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_otg_ahb_clk>;
|
||||
clock-names = "otg";
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@3f130000 {
|
||||
compatible = "brcm,kona-usb2-phy";
|
||||
reg = <0x3f130000 0x28>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&apps {
|
||||
gic: interrupt-controller@1c01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x01c01000 0x1000>,
|
||||
<0x01c00100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@1c20000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x01c20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&bsc1 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc2 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc3 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc4 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
|
||||
};
|
||||
|
||||
&smc {
|
||||
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
|
||||
};
|
||||
|
||||
334
arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi
Normal file
334
arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi
Normal file
@ -0,0 +1,334 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Common device tree for components shared between the BCM21664 and BCM23550
|
||||
* SoCs.
|
||||
*
|
||||
* Copyright (C) 2016 Broadcom
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/clock/bcm21664.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* Hub bus */
|
||||
hub: hub-bus@34000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x34000000 0x102f83ac>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
smc: smc@4e000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
resetmgr: reset-controller@1001f00 {
|
||||
compatible = "brcm,bcm21664-resetmgr";
|
||||
reg = <0x01001f00 0x24>;
|
||||
};
|
||||
|
||||
gpio: gpio@1003000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x01003000 0x524>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
timer@1006000 {
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x01006000 0x1c>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Slaves bus */
|
||||
slaves: slaves-bus@3e000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x3e000000 0x0001c070>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uartb: serial@0 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00000000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb2: serial@1000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00001000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb3: serial@2000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00002000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc1: i2c@16000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x00016000 0x70>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc2: i2c@17000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x00017000 0x70>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc3: i2c@18000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x00018000 0x70>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc4: i2c@1c000 {
|
||||
/* Compatible filled by SoC DTSI */
|
||||
reg = <0x0001c000 0x70>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* Apps bus */
|
||||
apps: apps-bus@3e300000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x3e300000 0x01c02000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
usbotg: usb@e20000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x00e20000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_otg_ahb_clk>;
|
||||
clock-names = "otg";
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@e30000 {
|
||||
compatible = "brcm,kona-usb2-phy";
|
||||
reg = <0x00e30000 0x28>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@e80000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00e80000 0x801c>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: mmc@e90000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00e90000 0x801c>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: mmc@ea0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00ea0000 0x801c>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio4: mmc@eb0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00eb0000 0x801c>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* Fixed clocks are defined before CCUs whose
|
||||
* clocks may depend on them.
|
||||
*/
|
||||
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
root_ccu: root_ccu@35001000 {
|
||||
compatible = "brcm,bcm21664-root-ccu";
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu@35002000 {
|
||||
compatible = "brcm,bcm21664-aon-ccu";
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu@3e011000 {
|
||||
compatible = "brcm,bcm21664-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"bsc4";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu@3f001000 {
|
||||
compatible = "brcm,bcm21664-master-ccu";
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"sdio1_sleep",
|
||||
"sdio2_sleep",
|
||||
"sdio3_sleep",
|
||||
"sdio4_sleep";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,45 +1,13 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* BSD LICENSE
|
||||
* Device tree for the BCM23550 SoC.
|
||||
*
|
||||
* Copyright(c) 2016 Broadcom. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* Copyright (C) 2016 Broadcom
|
||||
*/
|
||||
|
||||
/* BCM23550 and BCM21664 have almost identical clocks */
|
||||
#include <dt-bindings/clock/bcm21664.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "bcm2166x-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "BCM23550 SoC";
|
||||
compatible = "brcm,bcm23550";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
@ -80,180 +48,9 @@
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Hub bus */
|
||||
hub@34000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x34000000 0x102f83ac>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
smc@4e000 {
|
||||
compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
|
||||
reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
resetmgr: reset-controller@1001f00 {
|
||||
compatible = "brcm,bcm21664-resetmgr";
|
||||
reg = <0x01001f00 0x24>;
|
||||
};
|
||||
|
||||
gpio: gpio@1003000 {
|
||||
compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
|
||||
reg = <0x01003000 0x524>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
timer@1006000 {
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x01006000 0x1c>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Slaves bus */
|
||||
slaves@3e000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x3e000000 0x0001c070>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uartb: serial@0 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00000000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb2: serial@1000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00001000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb3: serial@2000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x00002000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc1: i2c@16000 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
reg = <0x00016000 0x70>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc2: i2c@17000 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
reg = <0x00017000 0x70>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc3: i2c@18000 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
reg = <0x00018000 0x70>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsc4: i2c@1c000 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
reg = <0x0001c000 0x70>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* Apps bus */
|
||||
apps@3e300000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x3e300000 0x01b77000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
usbotg: usb@e20000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x00e20000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_otg_ahb_clk>;
|
||||
clock-names = "otg";
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@e30000 {
|
||||
compatible = "brcm,kona-usb2-phy";
|
||||
reg = <0x00e30000 0x28>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@e80000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00e80000 0x801c>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: mmc@e90000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00e90000 0x801c>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: mmc@ea0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00ea0000 0x801c>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio4: mmc@eb0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x00eb0000 0x801c>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&apps {
|
||||
cdc: cdc@1b0e000 {
|
||||
compatible = "brcm,bcm23550-cdc";
|
||||
reg = <0x01b0e000 0x78>;
|
||||
@ -267,147 +64,28 @@
|
||||
reg = <0x01b21000 0x1000>,
|
||||
<0x01b22000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* Fixed clocks are defined before CCUs whose
|
||||
* clocks may depend on them.
|
||||
*/
|
||||
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
root_ccu: root_ccu@35001000 {
|
||||
compatible = "brcm,bcm21664-root-ccu";
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu@35002000 {
|
||||
compatible = "brcm,bcm21664-aon-ccu";
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu@3e011000 {
|
||||
compatible = "brcm,bcm21664-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"bsc4";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu@3f001000 {
|
||||
compatible = "brcm,bcm21664-master-ccu";
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"sdio1_sleep",
|
||||
"sdio2_sleep",
|
||||
"sdio3_sleep",
|
||||
"sdio4_sleep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&bsc1 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc2 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc3 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&bsc4 {
|
||||
compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
|
||||
};
|
||||
|
||||
&smc {
|
||||
compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
|
||||
};
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
<0x40000000 0x40000000 0x00001000>;
|
||||
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
|
||||
|
||||
local_intc: local_intc@40000000 {
|
||||
local_intc: interrupt-controller@40000000 {
|
||||
compatible = "brcm,bcm2836-l1-intc";
|
||||
reg = <0x40000000 0x100>;
|
||||
interrupt-controller;
|
||||
|
||||
@ -215,11 +215,15 @@
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
read-only;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mac_address: mac-address@66 {
|
||||
reg = <0x66 0x6>;
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mac_address: mac-address@66 {
|
||||
reg = <0x66 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -55,11 +55,15 @@
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
read-only;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mac_address: mac-address@66 {
|
||||
reg = <0x66 0x6>;
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mac_address: mac-address@66 {
|
||||
reg = <0x66 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -130,8 +130,8 @@
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
temp: lm75@48 {
|
||||
compatible = "lm75";
|
||||
temp: temperature-sensor@48 {
|
||||
compatible = "national,lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
|
||||
@ -423,14 +423,14 @@
|
||||
status = "okay";
|
||||
|
||||
/* U26 temperature sensor placed near SoC */
|
||||
temp1: nct75@4c {
|
||||
compatible = "lm75";
|
||||
temp1: temperature-sensor@4c {
|
||||
compatible = "ti,tmp75c";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
/* U27 temperature sensor placed near RTC battery */
|
||||
temp2: nct75@4d {
|
||||
compatible = "lm75";
|
||||
temp2: temperature-sensor@4d {
|
||||
compatible = "ti,tmp75c";
|
||||
reg = <0x4d>;
|
||||
};
|
||||
|
||||
|
||||
@ -198,8 +198,6 @@
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flx0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-analog-filter;
|
||||
i2c-digital-filter;
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
|
||||
@ -207,8 +207,6 @@
|
||||
status = "okay";
|
||||
|
||||
i2c0: i2c@600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flx0_default>;
|
||||
@ -254,8 +252,6 @@
|
||||
status = "okay";
|
||||
|
||||
i2c6: i2c@600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flx6_default>;
|
||||
|
||||
@ -31,6 +31,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_MAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
wifi_pwrseq: wifi_pwrseq {
|
||||
compatible = "mmc-pwrseq-wilc1000";
|
||||
reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
|
||||
@ -70,6 +78,11 @@
|
||||
mcp16502@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
pvin1-supply = <®_5v>;
|
||||
pvin2-supply = <®_5v>;
|
||||
pvin3-supply = <®_5v>;
|
||||
pvin4-supply = <®_5v>;
|
||||
status = "okay";
|
||||
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
|
||||
@ -84,6 +84,14 @@
|
||||
device_type = "memory";
|
||||
reg = <0x20000000 0x20000000>;
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V_MAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
@ -144,6 +152,11 @@
|
||||
mcp16502@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
pvin1-supply = <®_5v>;
|
||||
pvin2-supply = <®_5v>;
|
||||
pvin3-supply = <®_5v>;
|
||||
pvin4-supply = <®_5v>;
|
||||
status = "okay";
|
||||
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
|
||||
@ -78,6 +78,14 @@
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_MAIN_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
@ -190,6 +198,11 @@
|
||||
mcp16502@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
pvin1-supply = <®_5v>;
|
||||
pvin2-supply = <®_5v>;
|
||||
pvin3-supply = <®_5v>;
|
||||
pvin4-supply = <®_5v>;
|
||||
status = "okay";
|
||||
lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
|
||||
@ -72,6 +72,14 @@
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V_MAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
@ -189,6 +197,11 @@
|
||||
pmic@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
pvin1-supply = <®_5v>;
|
||||
pvin2-supply = <®_5v>;
|
||||
pvin3-supply = <®_5v>;
|
||||
pvin4-supply = <®_5v>;
|
||||
|
||||
regulators {
|
||||
vdd_3v3: VDD_IO {
|
||||
|
||||
@ -88,6 +88,14 @@
|
||||
reg = <0x60000000 0x20000000>;
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V_MAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "sama7g5ek audio";
|
||||
@ -239,6 +247,11 @@
|
||||
mcp16502@5b {
|
||||
compatible = "microchip,mcp16502";
|
||||
reg = <0x5b>;
|
||||
lvin-supply = <®_5v>;
|
||||
pvin1-supply = <®_5v>;
|
||||
pvin2-supply = <®_5v>;
|
||||
pvin3-supply = <®_5v>;
|
||||
pvin4-supply = <®_5v>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
@ -403,6 +416,42 @@
|
||||
i2c-digital-filter;
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
status = "okay";
|
||||
|
||||
eeprom0: eeprom@52 {
|
||||
compatible = "microchip,24aa025e48";
|
||||
reg = <0x52>;
|
||||
size = <256>;
|
||||
pagesize = <16>;
|
||||
vcc-supply = <&vdd_3v3>;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eeprom0_eui48: eui48@fa {
|
||||
reg = <0xfa 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom1: eeprom@53 {
|
||||
compatible = "microchip,24aa025e48";
|
||||
reg = <0x53>;
|
||||
size = <256>;
|
||||
pagesize = <16>;
|
||||
vcc-supply = <&vdd_3v3>;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eeprom1_eui48: eui48@fa {
|
||||
reg = <0xfa 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -440,6 +489,8 @@
|
||||
&pinctrl_gmac0_txck_default
|
||||
&pinctrl_gmac0_phy_irq>;
|
||||
phy-mode = "rgmii-id";
|
||||
nvmem-cells = <&eeprom0_eui48>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
status = "okay";
|
||||
|
||||
ethernet-phy@7 {
|
||||
@ -457,6 +508,8 @@
|
||||
&pinctrl_gmac1_mdio_default
|
||||
&pinctrl_gmac1_phy_irq>;
|
||||
phy-mode = "rmii";
|
||||
nvmem-cells = <&eeprom1_eui48>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
status = "okay"; /* Conflict with pdmc0. */
|
||||
|
||||
ethernet-phy@0 {
|
||||
|
||||
@ -225,7 +225,7 @@
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
|
||||
@ -170,7 +170,7 @@
|
||||
pinctrl: pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x600>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
|
||||
@ -317,7 +317,7 @@
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x600>;
|
||||
|
||||
atmel,mux-mask =
|
||||
|
||||
@ -167,7 +167,7 @@
|
||||
pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
|
||||
@ -40,13 +40,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds1 {
|
||||
led-ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
led-ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
@ -37,71 +37,71 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_blue {
|
||||
led-power-blue {
|
||||
label = "smartgw:power:blue";
|
||||
gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
power_green {
|
||||
led-power-green {
|
||||
label = "smartgw:power:green";
|
||||
gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
power_red {
|
||||
led-power-red {
|
||||
label = "smartgw:power:red";
|
||||
gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_blue {
|
||||
led-radio-blue {
|
||||
label = "smartgw:radio:blue";
|
||||
gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_green {
|
||||
led-radio-green {
|
||||
label = "smartgw:radio:green";
|
||||
gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_red {
|
||||
led-radio-red {
|
||||
label = "smartgw:radio:red";
|
||||
gpios = <&pioC 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_blue {
|
||||
led-internet-blue {
|
||||
label = "smartgw:internet:blue";
|
||||
gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_green {
|
||||
led-internet-green {
|
||||
label = "smartgw:internet:green";
|
||||
gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_red {
|
||||
led-internet-red {
|
||||
label = "smartgw:internet:red";
|
||||
gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
heartbeat {
|
||||
led-heartbeat {
|
||||
label = "smartgw:heartbeat";
|
||||
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
pb18 {
|
||||
led-pb18 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pd21 {
|
||||
led-pd21 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -190,7 +190,7 @@
|
||||
pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
|
||||
@ -226,7 +226,7 @@
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
|
||||
@ -207,19 +207,19 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d8 {
|
||||
led-d8 {
|
||||
label = "d8";
|
||||
gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
d9 {
|
||||
led-d9 {
|
||||
label = "d9";
|
||||
gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
d10 {
|
||||
led-d10 {
|
||||
label = "d10";
|
||||
gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
||||
@ -339,7 +339,7 @@
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
atmel,mux-mask =
|
||||
|
||||
@ -202,7 +202,7 @@
|
||||
pinctrl: pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
|
||||
@ -120,13 +120,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pb18 {
|
||||
led-pb18 {
|
||||
label = "pb18";
|
||||
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
pd21 {
|
||||
led-pd21 {
|
||||
label = "pd21";
|
||||
gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
@ -215,6 +215,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -284,6 +286,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -394,6 +398,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -443,6 +449,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -600,6 +608,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -649,6 +659,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -698,6 +710,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -766,6 +780,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -834,6 +850,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -902,6 +920,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -970,6 +990,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -1074,6 +1096,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -1123,6 +1147,8 @@
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
|
||||
dmas = <&dma0
|
||||
(AT91_XDMAC_DT_MEM_IF(0) |
|
||||
@ -1223,7 +1249,7 @@
|
||||
pinctrl: pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
|
||||
@ -1236,7 +1262,7 @@
|
||||
>;
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
@ -1247,7 +1273,7 @@
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
@ -1259,7 +1285,7 @@
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
@ -1270,7 +1296,7 @@
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
@ -1312,7 +1338,7 @@
|
||||
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffe20 0x20>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&clk32k 0>;
|
||||
clocks = <&clk32k 1>;
|
||||
};
|
||||
|
||||
pit: timer@fffffe40 {
|
||||
@ -1338,7 +1364,7 @@
|
||||
compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
|
||||
reg = <0xfffffea8 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&clk32k 0>;
|
||||
clocks = <&clk32k 1>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@ffffff80 {
|
||||
|
||||
@ -493,7 +493,7 @@
|
||||
pinctrl: pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
|
||||
compatible = "atmel,sama5d3-pinctrl", "simple-mfd";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
|
||||
@ -791,7 +791,7 @@
|
||||
pinctrl: pinctrl@fc06a000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
|
||||
compatible = "atmel,sama5d3-pinctrl", "simple-mfd";
|
||||
ranges = <0xfc068000 0xfc068000 0x100
|
||||
0xfc06a000 0xfc06a000 0x4000>;
|
||||
/* WARNING: revisit as pin spec has changed */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user