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Merge series "DAI driver for new XCVR IP" from "Viorel Suman (OSS)" <viorel.suman@oss.nxp.com>

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Viorel Suman <viorel.suman@nxp.com>:

From: Viorel Suman <viorel.suman@nxp.com>

DAI driver for new XCVR IP found in i.MX8MP.

Viorel Suman (2):
  ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI driver
  ASoC: dt-bindings: fsl_xcvr: Add document for XCVR

Changes since v1:
 - improved 6- and 12-ch layout comment
 - used regmap polling function, improved
   clocks handling in runtime_resume
 - added FW size check in FW load function,
   improved IRQ handler, removed dummy IRQ handlers
 - fixed yaml file

Changes since v2:
 - used devm_reset_control_get_exclusive instead of of_reset_control_get
 - moved reset_control_assert into runtime_suspend

Changes since v3:
 - removed "firmware-name" DTS property from both documentation and
   source code by porting it into SoC specific 'compatible' data structure.

 .../devicetree/bindings/sound/fsl,xcvr.yaml   |  104 ++
 sound/soc/fsl/Kconfig                         |   10 +
 sound/soc/fsl/Makefile                        |    2 +
 sound/soc/fsl/fsl_xcvr.c                      | 1359 +++++++++++++++++
 sound/soc/fsl/fsl_xcvr.h                      |  266 ++++
 5 files changed, 1741 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
 create mode 100644 sound/soc/fsl/fsl_xcvr.c
 create mode 100644 sound/soc/fsl/fsl_xcvr.h

--
2.26.2
This commit is contained in:
Mark Brown 2020-10-26 18:37:16 +00:00
commit 7a25748ba0
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5 changed files with 1741 additions and 0 deletions
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104
Documentation/devicetree/bindings/sound/fsl,xcvr.yaml Normal file
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@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,xcvr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Audio Transceiver (XCVR) Controller
maintainers:
- Viorel Suman <viorel.suman@nxp.com>
description: |
NXP XCVR (Audio Transceiver) is a on-chip functional module
that allows CPU to receive and transmit digital audio via
HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
properties:
$nodename:
pattern: "^xcvr@.*"
compatible:
enum:
- fsl,imx8mp-xcvr
reg:
items:
- description: 20K RAM for code and data
- description: registers space
- description: RX FIFO address
- description: TX FIFO address
reg-names:
items:
- const: ram
- const: regs
- const: rxfifo
- const: txfifo
interrupts:
maxItems: 1
clocks:
items:
- description: Peripheral clock
- description: PHY clock
- description: SPBA clock
- description: PLL clock
clock-names:
items:
- const: ipg
- const: phy
- const: spba
- const: pll_ipg
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
resets:
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
- dmas
- dma-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/reset/imx8mp-reset.h>
xcvr: xcvr@30cc0000 {
compatible = "fsl,imx8mp-xcvr";
reg = <0x30cc0000 0x800>,
<0x30cc0800 0x400>,
<0x30cc0c00 0x080>,
<0x30cc0e00 0x080>;
reg-names = "ram", "regs", "rxfifo", "txfifo";
interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
clock-names = "ipg", "phy", "spba", "pll_ipg";
dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
dma-names = "rx", "tx";
resets = <&audiomix_reset 0>;
};

10
sound/soc/fsl/Kconfig
View File

@ -95,6 +95,16 @@ config SND_SOC_FSL_EASRC
destination sample rate. It is a new design module compare with the
old ASRC.
config SND_SOC_FSL_XCVR
tristate "NXP Audio Transceiver (XCVR) module support"
select REGMAP_MMIO
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y if you want to add Audio Transceiver (XCVR) support for NXP
iMX CPUs. XCVR is a digital module that supports HDMI2.1 eARC,
HDMI1.4 ARC and SPDIF.
config SND_SOC_FSL_UTILS
tristate

2
sound/soc/fsl/Makefile
View File

@ -25,6 +25,7 @@ snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
snd-soc-fsl-mqs-objs := fsl_mqs.o
snd-soc-fsl-easrc-objs := fsl_easrc.o
snd-soc-fsl-xcvr-objs := fsl_xcvr.o
obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@ -38,6 +39,7 @@ obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_FSL_MQS) += snd-soc-fsl-mqs.o
obj-$(CONFIG_SND_SOC_FSL_EASRC) += snd-soc-fsl-easrc.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
# MPC5200 Platform Support
obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o

1359
sound/soc/fsl/fsl_xcvr.c Normal file
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File diff suppressed because it is too large Load Diff

266
sound/soc/fsl/fsl_xcvr.h Normal file
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@ -0,0 +1,266 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* NXP XCVR ALSA SoC Digital Audio Interface (DAI) driver
*
* Copyright 2019 NXP
*/
#ifndef __FSL_XCVR_H
#define __FSL_XCVR_H
#define FSL_XCVR_MODE_SPDIF 0
#define FSL_XCVR_MODE_ARC 1
#define FSL_XCVR_MODE_EARC 2
/* XCVR Registers */
#define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */
#define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */
#define FSL_XCVR_FIFO_WMK_RX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */
#define FSL_XCVR_FIFO_WMK_TX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */
#define FSL_XCVR_MAXBURST_RX (FSL_XCVR_FIFO_WMK_RX >> 2) /* 16 */
#define FSL_XCVR_MAXBURST_TX (FSL_XCVR_FIFO_WMK_TX >> 2) /* 16 */
#define FSL_XCVR_RX_FIFO_ADDR 0x0C00
#define FSL_XCVR_TX_FIFO_ADDR 0x0E00
#define FSL_XCVR_VERSION 0x00 /* Version */
#define FSL_XCVR_EXT_CTRL 0x10 /* Control */
#define FSL_XCVR_EXT_STATUS 0x20 /* Status */
#define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */
#define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */
#define FSL_XCVR_EXT_ISR 0x50 /* Interrupt status */
#define FSL_XCVR_EXT_ISR_SET 0x54 /* Interrupt status */
#define FSL_XCVR_EXT_ISR_CLR 0x58 /* Interrupt status */
#define FSL_XCVR_EXT_ISR_TOG 0x5C /* Interrupt status */
#define FSL_XCVR_IER 0x70 /* Interrupt en for M0+ */
#define FSL_XCVR_ISR 0x80 /* Interrupt status */
#define FSL_XCVR_ISR_SET 0x84 /* Interrupt status set */
#define FSL_XCVR_ISR_CLR 0x88 /* Interrupt status clear */
#define FSL_XCVR_ISR_TOG 0x8C /* Interrupt status toggle */
#define FSL_XCVR_PHY_AI_CTRL 0x90
#define FSL_XCVR_PHY_AI_CTRL_SET 0x94
#define FSL_XCVR_PHY_AI_CTRL_CLR 0x98
#define FSL_XCVR_PHY_AI_CTRL_TOG 0x9C
#define FSL_XCVR_PHY_AI_WDATA 0xA0
#define FSL_XCVR_PHY_AI_RDATA 0xA4
#define FSL_XCVR_CLK_CTRL 0xB0
#define FSL_XCVR_RX_DPTH_CTRL 0x180 /* RX datapath ctrl reg */
#define FSL_XCVR_RX_DPTH_CTRL_SET 0x184
#define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188
#define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c
#define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */
#define FSL_XCVR_TX_DPTH_CTRL_SET 0x224
#define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228
#define FSL_XCVR_TX_DPTH_CTRL_TOG 0x22C
#define FSL_XCVR_TX_CS_DATA_0 0x230 /* TX channel status bits regs */
#define FSL_XCVR_TX_CS_DATA_1 0x234
#define FSL_XCVR_TX_CS_DATA_2 0x238
#define FSL_XCVR_TX_CS_DATA_3 0x23C
#define FSL_XCVR_TX_CS_DATA_4 0x240
#define FSL_XCVR_TX_CS_DATA_5 0x244
#define FSL_XCVR_DEBUG_REG_0 0x2E0
#define FSL_XCVR_DEBUG_REG_1 0x2F0
#define FSL_XCVR_MAX_REG FSL_XCVR_DEBUG_REG_1
#define FSL_XCVR_EXT_CTRL_CORE_RESET BIT(31)
#define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET BIT(30)
#define FSL_XCVR_EXT_CTRL_TX_CMDC_RESET BIT(29)
#define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) (t ? BIT(29) : BIT(30))
#define FSL_XCVR_EXT_CTRL_RX_DPTH_RESET BIT(28)
#define FSL_XCVR_EXT_CTRL_TX_DPTH_RESET BIT(27)
#define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) (t ? BIT(27) : BIT(28))
#define FSL_XCVR_EXT_CTRL_TX_RX_MODE BIT(26)
#define FSL_XCVR_EXT_CTRL_DMA_RD_DIS BIT(25)
#define FSL_XCVR_EXT_CTRL_DMA_WR_DIS BIT(24)
#define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25))
#define FSL_XCVR_EXT_CTRL_SPDIF_MODE BIT(23)
#define FSL_XCVR_EXT_CTRL_SLEEP_MODE BIT(21)
#define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT 0
#define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0)
#define FSL_XCVR_EXT_CTRL_TX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_TX_FWM_SHFT) \
& FSL_XCVR_EXT_CTRL_TX_FWM_MASK)
#define FSL_XCVR_EXT_CTRL_RX_FWM_SHFT 8
#define FSL_XCVR_EXT_CTRL_RX_FWM_MASK GENMASK(14, 8)
#define FSL_XCVR_EXT_CTRL_RX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_RX_FWM_SHFT) \
& FSL_XCVR_EXT_CTRL_RX_FWM_MASK)
#define FSL_XCVR_EXT_CTRL_PAGE_SHFT 16
#define FSL_XCVR_EXT_CTRL_PAGE_MASK GENMASK(19, 16)
#define FSL_XCVR_EXT_CTRL_PAGE(i) (((i) << FSL_XCVR_EXT_CTRL_PAGE_SHFT) \
& FSL_XCVR_EXT_CTRL_PAGE_MASK)
#define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0)
#define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8)
#define FSL_XCVR_EXT_STUS_CM0_SLEEPING BIT(16)
#define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP BIT(17)
#define FSL_XCVR_EXT_STUS_CM0_SLP_HACK BIT(18)
#define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO BIT(23)
#define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO BIT(24)
#define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25)
#define FSL_XCVR_EXT_STUS_TX_CMDC_COTO BIT(26)
#define FSL_XCVR_EXT_STUS_HB_STATUS BIT(27)
#define FSL_XCVR_EXT_STUS_NEW_UD4_REC BIT(28)
#define FSL_XCVR_EXT_STUS_NEW_UD5_REC BIT(29)
#define FSL_XCVR_EXT_STUS_NEW_UD6_REC BIT(30)
#define FSL_XCVR_EXT_STUS_HPD_INPUT BIT(31)
#define FSL_XCVR_IRQ_NEW_CS BIT(0)
#define FSL_XCVR_IRQ_NEW_UD BIT(1)
#define FSL_XCVR_IRQ_MUTE BIT(2)
#define FSL_XCVR_IRQ_CMDC_RESP_TO BIT(3)
#define FSL_XCVR_IRQ_ECC_ERR BIT(4)
#define FSL_XCVR_IRQ_PREAMBLE_MISMATCH BIT(5)
#define FSL_XCVR_IRQ_FIFO_UOFL_ERR BIT(6)
#define FSL_XCVR_IRQ_HOST_WAKEUP BIT(7)
#define FSL_XCVR_IRQ_HOST_OHPD BIT(8)
#define FSL_XCVR_IRQ_DMAC_NO_DATA_REC BIT(9)
#define FSL_XCVR_IRQ_DMAC_FMT_CHG_DET BIT(10)
#define FSL_XCVR_IRQ_HB_STATE_CHG BIT(11)
#define FSL_XCVR_IRQ_CMDC_STATUS_UPD BIT(12)
#define FSL_XCVR_IRQ_TEMP_UPD BIT(13)
#define FSL_XCVR_IRQ_DMA_RD_REQ BIT(14)
#define FSL_XCVR_IRQ_DMA_WR_REQ BIT(15)
#define FSL_XCVR_IRQ_DMAC_BME_BIT_ERR BIT(16)
#define FSL_XCVR_IRQ_PREAMBLE_MATCH BIT(17)
#define FSL_XCVR_IRQ_M_W_PRE_MISMATCH BIT(18)
#define FSL_XCVR_IRQ_B_PRE_MISMATCH BIT(19)
#define FSL_XCVR_IRQ_UNEXP_PRE_REC BIT(20)
#define FSL_XCVR_IRQ_ARC_MODE BIT(21)
#define FSL_XCVR_IRQ_CH_UD_OFLOW BIT(22)
#define FSL_XCVR_IRQ_EARC_ALL (FSL_XCVR_IRQ_NEW_CS | \
FSL_XCVR_IRQ_NEW_UD | \
FSL_XCVR_IRQ_MUTE | \
FSL_XCVR_IRQ_FIFO_UOFL_ERR | \
FSL_XCVR_IRQ_HOST_WAKEUP | \
FSL_XCVR_IRQ_ARC_MODE)
#define FSL_XCVR_ISR_CMDC_TX_EN BIT(3)
#define FSL_XCVR_ISR_HPD_TGL BIT(15)
#define FSL_XCVR_ISR_DMAC_SPARE_INT BIT(19)
#define FSL_XCVR_ISR_SET_SPDIF_RX_INT BIT(20)
#define FSL_XCVR_ISR_SET_SPDIF_TX_INT BIT(21)
#define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20))
#define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22)
#define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23)
#define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0)
#define FSL_XCVR_PHY_AI_RESETN BIT(15)
#define FSL_XCVR_PHY_AI_TOG_PLL BIT(24)
#define FSL_XCVR_PHY_AI_TOG_DONE_PLL BIT(25)
#define FSL_XCVR_PHY_AI_TOG_PHY BIT(26)
#define FSL_XCVR_PHY_AI_TOG_DONE_PHY BIT(27)
#define FSL_XCVR_PHY_AI_RW_MASK BIT(31)
#define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS BIT(0)
#define FSL_XCVR_RX_DPTH_CTRL_DIS_PRE_ERR_CHK BIT(1)
#define FSL_XCVR_RX_DPTH_CTRL_DIS_NOD_REC_CHK BIT(2)
#define FSL_XCVR_RX_DPTH_CTRL_ECC_VUC_BIT_CHK BIT(3)
#define FSL_XCVR_RX_DPTH_CTRL_EN_CMP_PAR_CALC BIT(4)
#define FSL_XCVR_RX_DPTH_CTRL_RST_PKT_CNT_FIFO BIT(5)
#define FSL_XCVR_RX_DPTH_CTRL_STORE_FMT BIT(6)
#define FSL_XCVR_RX_DPTH_CTRL_EN_PAR_CALC BIT(7)
#define FSL_XCVR_RX_DPTH_CTRL_UDR BIT(8)
#define FSL_XCVR_RX_DPTH_CTRL_CSR BIT(9)
#define FSL_XCVR_RX_DPTH_CTRL_UDA BIT(10)
#define FSL_XCVR_RX_DPTH_CTRL_CSA BIT(11)
#define FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO BIT(12)
#define FSL_XCVR_RX_DPTH_CTRL_DIS_B_PRE_ERR_CHK BIT(13)
#define FSL_XCVR_RX_DPTH_CTRL_PABS BIT(19)
#define FSL_XCVR_RX_DPTH_CTRL_DTS_CDS BIT(20)
#define FSL_XCVR_RX_DPTH_CTRL_BLKC BIT(21)
#define FSL_XCVR_RX_DPTH_CTRL_MUTE_CTRL BIT(22)
#define FSL_XCVR_RX_DPTH_CTRL_MUTE_MODE BIT(23)
#define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_CTRL BIT(24)
#define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE BIT(25)
#define FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL BIT(26)
#define FSL_XCVR_RX_DPTH_CTRL_LAYB_MODE BIT(27)
#define FSL_XCVR_RX_DPTH_CTRL_PRC BIT(28)
#define FSL_XCVR_RX_DPTH_CTRL_COMP BIT(29)
#define FSL_XCVR_RX_DPTH_CTRL_FSM GENMASK(31, 30)
#define FSL_XCVR_TX_DPTH_CTRL_CS_ACK BIT(0)
#define FSL_XCVR_TX_DPTH_CTRL_UD_ACK BIT(1)
#define FSL_XCVR_TX_DPTH_CTRL_CS_MOD BIT(2)
#define FSL_XCVR_TX_DPTH_CTRL_UD_MOD BIT(3)
#define FSL_XCVR_TX_DPTH_CTRL_VLD_MOD BIT(4)
#define FSL_XCVR_TX_DPTH_CTRL_FRM_VLD BIT(5)
#define FSL_XCVR_TX_DPTH_CTRL_EN_PARITY BIT(6)
#define FSL_XCVR_TX_DPTH_CTRL_EN_PREAMBLE BIT(7)
#define FSL_XCVR_TX_DPTH_CTRL_EN_ECC_INTER BIT(8)
#define FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM BIT(10)
#define FSL_XCVR_TX_DPTH_CTRL_FRM_FMT BIT(11)
#define FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX BIT(14)
#define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_STR BIT(15)
#define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_END BIT(16)
#define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29)
#define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30)
#define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15)
#define FSL_XCVR_PLL_CTRL0 0x00
#define FSL_XCVR_PLL_CTRL0_SET 0x04
#define FSL_XCVR_PLL_CTRL0_CLR 0x08
#define FSL_XCVR_PLL_NUM 0x20
#define FSL_XCVR_PLL_DEN 0x30
#define FSL_XCVR_PLL_PDIV 0x40
#define FSL_XCVR_PLL_BANDGAP_SET 0x54
#define FSL_XCVR_PHY_CTRL 0x00
#define FSL_XCVR_PHY_CTRL_SET 0x04
#define FSL_XCVR_PHY_CTRL_CLR 0x08
#define FSL_XCVR_PHY_CTRL2 0x70
#define FSL_XCVR_PHY_CTRL2_SET 0x74
#define FSL_XCVR_PHY_CTRL2_CLR 0x78
#define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0)
#define FSL_XCVR_PLL_CTRL0_HROFF BIT(13)
#define FSL_XCVR_PLL_CTRL0_PWP BIT(14)
#define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24)
#define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25)
#define FSL_XCVR_PLL_CTRL0_CM2_EN BIT(26)
#define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i))
#define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0)
#define FSL_XCVR_PHY_CTRL_RX_CM_EN BIT(1)
#define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5)
#define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8)
#define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN BIT(9)
#define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN BIT(10)
#define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25)
#define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25)
#define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS BIT(26)
#define FSL_XCVR_PHY_CTRL2_EARC_TXMS BIT(14)
#define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31, 24)
#define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000
#define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000
#define FSL_XCVR_CS_DATA_0_FS_48000 0x2000000
#define FSL_XCVR_CS_DATA_0_FS_64000 0xB000000
#define FSL_XCVR_CS_DATA_0_FS_88200 0x8000000
#define FSL_XCVR_CS_DATA_0_FS_96000 0xA000000
#define FSL_XCVR_CS_DATA_0_FS_176400 0xC000000
#define FSL_XCVR_CS_DATA_0_FS_192000 0xE000000
#define FSL_XCVR_CS_DATA_0_CH_MASK 0x3A
#define FSL_XCVR_CS_DATA_0_CH_U2LPCM 0x00
#define FSL_XCVR_CS_DATA_0_CH_UMLPCM 0x20
#define FSL_XCVR_CS_DATA_0_CH_U1BAUD 0x30
#define FSL_XCVR_CS_DATA_1_CH_MASK 0xF000
#define FSL_XCVR_CS_DATA_1_CH_2 0x0000
#define FSL_XCVR_CS_DATA_1_CH_8 0x7000
#define FSL_XCVR_CS_DATA_1_CH_16 0xB000
#define FSL_XCVR_CS_DATA_1_CH_32 0x3000
/* Data memory structures */
#define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */
#define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */
#define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */
#define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */
#define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */
#endif /* __FSL_XCVR_H */