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bnx2x: don't reset device while reading its configuration.

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Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Kravkov 2011-08-30 00:08:43 +00:00 committed by David S. Miller
parent 3395a033a7
commit 7a06a12232
2 changed files with 16 additions and 10 deletions
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24
drivers/net/bnx2x/bnx2x_main.c
View File

@ -5822,7 +5822,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
* take the UNDI lock to protect undi_unload flow from accessing * take the UNDI lock to protect undi_unload flow from accessing
* registers while we're resetting the chip * registers while we're resetting the chip
*/ */
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
bnx2x_reset_common(bp); bnx2x_reset_common(bp);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
@ -5834,7 +5834,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
} }
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
@ -8570,10 +8570,12 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
/* Check if there is any driver already loaded */ /* Check if there is any driver already loaded */
val = REG_RD(bp, MISC_REG_UNPREPARED); val = REG_RD(bp, MISC_REG_UNPREPARED);
if (val == 0x1) { if (val == 0x1) {
/* Check if it is the UNDI driver
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
/*
* Check if it is the UNDI driver
* UNDI driver initializes CID offset for normal bell to 0x7 * UNDI driver initializes CID offset for normal bell to 0x7
*/ */
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
if (val == 0x7) { if (val == 0x7) {
u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
@ -8611,9 +8613,6 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
bnx2x_fw_command(bp, reset_code, 0); bnx2x_fw_command(bp, reset_code, 0);
} }
/* now it's safe to release the lock */
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
bnx2x_undi_int_disable(bp); bnx2x_undi_int_disable(bp);
port = BP_PORT(bp); port = BP_PORT(bp);
@ -8663,8 +8662,10 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
bp->fw_seq = bp->fw_seq =
(SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
DRV_MSG_SEQ_NUMBER_MASK); DRV_MSG_SEQ_NUMBER_MASK);
} else }
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
/* now it's safe to release the lock */
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
} }
} }
@ -9440,6 +9441,10 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
bp->igu_base_sb = 0; bp->igu_base_sb = 0;
} else { } else {
bp->common.int_block = INT_BLOCK_IGU; bp->common.int_block = INT_BLOCK_IGU;
/* do not allow device reset during IGU info preocessing */
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
@ -9471,6 +9476,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
bnx2x_get_igu_cam_info(bp); bnx2x_get_igu_cam_info(bp);
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
} }
/* /*

2
drivers/net/bnx2x/bnx2x_reg.h
View File

@ -5766,7 +5766,7 @@
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
#define HW_LOCK_RESOURCE_SPIO 2 #define HW_LOCK_RESOURCE_SPIO 2
#define HW_LOCK_RESOURCE_UNDI 5 #define HW_LOCK_RESOURCE_RESET 5
#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)