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gpio: loongson: add gpio driver support
The Loongson platforms GPIO controller contains 60 GPIO pins in total, 4 of which are dedicated GPIO pins, and the remaining 56 are reused with other functions. Each GPIO can set input/output and has the interrupt capability. This driver added support for Loongson GPIO controller and support to use DTS or ACPI to descibe GPIO device resources. Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Hongchen Zhang <zhanghongchen@loongson.cn> Signed-off-by: Liu Peibao <liupeibao@loongson.cn> Signed-off-by: Juxin Gao <gaojuxin@loongson.cn> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Yinbo Zhu
Bartosz Golaszewski
parent
db2056e21c
commit
7944d3b7fe
@ -12121,6 +12121,7 @@ M: Yinbo Zhu <zhuyinbo@loongson.cn>
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L: linux-gpio@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml
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F: drivers/gpio/gpio-loongson-64bit.c
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LOONGSON-2 SOC SERIES CLOCK DRIVER
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M: Yinbo Zhu <zhuyinbo@loongson.cn>
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@ -380,6 +380,18 @@ config GPIO_LOONGSON
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help
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Driver for GPIO functionality on Loongson-2F/3A/3B processors.
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config GPIO_LOONGSON_64BIT
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tristate "Loongson 64 bit GPIO support"
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depends on LOONGARCH || COMPILE_TEST
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select OF_GPIO
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select GPIO_GENERIC
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help
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Say yes here to support the GPIO functionality of a number of
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Loongson series of chips. The Loongson GPIO controller supports
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up to 60 GPIOS in total, 4 of which are dedicated GPIO pins, and
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the remaining 56 are reused with other functions, with edge or
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level triggered interrupts.
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config GPIO_LPC18XX
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tristate "NXP LPC18XX/43XX GPIO support"
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default y if ARCH_LPC18XX
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@ -80,6 +80,7 @@ obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
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obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
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obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
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obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
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obj-$(CONFIG_GPIO_LOONGSON_64BIT) += gpio-loongson-64bit.o
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obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
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obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
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obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
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239
drivers/gpio/gpio-loongson-64bit.c
Normal file
239
drivers/gpio/gpio-loongson-64bit.c
Normal file
@ -0,0 +1,239 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Loongson GPIO Support
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*
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <asm/types.h>
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enum loongson_gpio_mode {
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BIT_CTRL_MODE,
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BYTE_CTRL_MODE,
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};
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struct loongson_gpio_chip_data {
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const char *label;
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enum loongson_gpio_mode mode;
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unsigned int conf_offset;
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unsigned int out_offset;
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unsigned int in_offset;
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};
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struct loongson_gpio_chip {
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struct gpio_chip chip;
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struct fwnode_handle *fwnode;
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spinlock_t lock;
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void __iomem *reg_base;
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const struct loongson_gpio_chip_data *chip_data;
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};
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static inline struct loongson_gpio_chip *to_loongson_gpio_chip(struct gpio_chip *chip)
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{
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return container_of(chip, struct loongson_gpio_chip, chip);
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}
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static inline void loongson_commit_direction(struct loongson_gpio_chip *lgpio, unsigned int pin,
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int input)
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{
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u8 bval = input ? 1 : 0;
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writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
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}
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static void loongson_commit_level(struct loongson_gpio_chip *lgpio, unsigned int pin, int high)
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{
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u8 bval = high ? 1 : 0;
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writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin);
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}
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static int loongson_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_direction(lgpio, pin, 1);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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return 0;
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}
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static int loongson_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, int value)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_level(lgpio, pin, value);
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loongson_commit_direction(lgpio, pin, 0);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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return 0;
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}
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static int loongson_gpio_get(struct gpio_chip *chip, unsigned int pin)
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{
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u8 bval;
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int val;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin);
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val = bval & 1;
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return val;
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}
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static int loongson_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
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{
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u8 bval;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
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if (bval & 1)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static void loongson_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_level(lgpio, pin, value);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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}
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static int loongson_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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struct platform_device *pdev = to_platform_device(chip->parent);
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return platform_get_irq(pdev, offset);
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}
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static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgpio,
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struct device_node *np, void __iomem *reg_base)
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{
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int ret;
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u32 ngpios;
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lgpio->reg_base = reg_base;
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if (lgpio->chip_data->mode == BIT_CTRL_MODE) {
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ret = bgpio_init(&lgpio->chip, dev, 8,
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lgpio->reg_base + lgpio->chip_data->in_offset,
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lgpio->reg_base + lgpio->chip_data->out_offset,
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NULL, NULL,
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lgpio->reg_base + lgpio->chip_data->conf_offset,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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} else {
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lgpio->chip.direction_input = loongson_gpio_direction_input;
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lgpio->chip.get = loongson_gpio_get;
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lgpio->chip.get_direction = loongson_gpio_get_direction;
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lgpio->chip.direction_output = loongson_gpio_direction_output;
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lgpio->chip.set = loongson_gpio_set;
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lgpio->chip.parent = dev;
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spin_lock_init(&lgpio->lock);
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}
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device_property_read_u32(dev, "ngpios", &ngpios);
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lgpio->chip.can_sleep = 0;
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lgpio->chip.ngpio = ngpios;
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lgpio->chip.label = lgpio->chip_data->label;
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lgpio->chip.to_irq = loongson_gpio_to_irq;
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return devm_gpiochip_add_data(dev, &lgpio->chip, lgpio);
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}
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static int loongson_gpio_probe(struct platform_device *pdev)
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{
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void __iomem *reg_base;
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struct loongson_gpio_chip *lgpio;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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lgpio = devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL);
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if (!lgpio)
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return -ENOMEM;
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lgpio->chip_data = device_get_match_data(dev);
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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return loongson_gpio_init(dev, lgpio, np, reg_base);
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}
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = {
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.label = "ls2k_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0x20,
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.out_offset = 0x10,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls7a_data = {
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.label = "ls7a_gpio",
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.mode = BYTE_CTRL_MODE,
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.conf_offset = 0x800,
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.in_offset = 0xa00,
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.out_offset = 0x900,
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};
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static const struct of_device_id loongson_gpio_of_match[] = {
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{
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.compatible = "loongson,ls2k-gpio",
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.data = &loongson_gpio_ls2k_data,
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},
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{
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.compatible = "loongson,ls7a-gpio",
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.data = &loongson_gpio_ls7a_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, loongson_gpio_of_match);
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static const struct acpi_device_id loongson_gpio_acpi_match[] = {
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{
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.id = "LOON0002",
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.driver_data = (kernel_ulong_t)&loongson_gpio_ls7a_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(acpi, loongson_gpio_acpi_match);
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static struct platform_driver loongson_gpio_driver = {
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.driver = {
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.name = "loongson-gpio",
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.owner = THIS_MODULE,
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.of_match_table = loongson_gpio_of_match,
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.acpi_match_table = loongson_gpio_acpi_match,
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},
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.probe = loongson_gpio_probe,
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};
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static int __init loongson_gpio_setup(void)
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{
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return platform_driver_register(&loongson_gpio_driver);
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}
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postcore_initcall(loongson_gpio_setup);
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MODULE_DESCRIPTION("Loongson gpio driver");
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MODULE_LICENSE("GPL");
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