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rtw88: 8723d: 11N chips don't support H2C queue
H2C queue is used to send command to firmware. Since 8723D doesn't support this queue, this commit check wlan_cpu flag to avoid to set H2C related registers. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-6-yhchuang@realtek.com
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@ -1016,7 +1016,8 @@ static int txdma_queue_mapping(struct rtw_dev *rtwdev)
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rtw_write8(rtwdev, REG_CR, 0);
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rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
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rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
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if (rtw_chip_wcpu_11ac(rtwdev))
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rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
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return 0;
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}
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@ -1135,6 +1136,9 @@ static int init_h2c(struct rtw_dev *rtwdev)
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u32 h2cq_free;
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u32 wp, rp;
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if (rtw_chip_wcpu_11n(rtwdev))
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return 0;
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h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
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h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT;
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@ -411,12 +411,14 @@ static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev)
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dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma;
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rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma);
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len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len;
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dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma;
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rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0;
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rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0;
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rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK);
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rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma);
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if (!rtw_chip_wcpu_11n(rtwdev)) {
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len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len;
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dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma;
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rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0;
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rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0;
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rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK);
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rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma);
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}
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len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len;
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dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma;
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@ -471,8 +473,9 @@ static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev)
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rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff);
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/* reset H2C Queue index in a single write */
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rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR,
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BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX);
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if (rtw_chip_wcpu_11ac(rtwdev))
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rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR,
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BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX);
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}
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static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev)
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@ -489,7 +492,9 @@ static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev,
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rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0]);
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rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]);
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rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]);
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if (rtw_chip_wcpu_11ac(rtwdev))
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rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]);
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rtwpci->irq_enabled = true;
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spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags);
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@ -507,7 +512,9 @@ static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev,
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rtw_write32(rtwdev, RTK_PCI_HIMR0, 0);
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rtw_write32(rtwdev, RTK_PCI_HIMR1, 0);
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rtw_write32(rtwdev, RTK_PCI_HIMR3, 0);
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if (rtw_chip_wcpu_11ac(rtwdev))
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rtw_write32(rtwdev, RTK_PCI_HIMR3, 0);
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rtwpci->irq_enabled = false;
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out:
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@ -1012,13 +1019,17 @@ static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev,
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irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0);
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irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1);
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irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3);
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if (rtw_chip_wcpu_11ac(rtwdev))
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irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3);
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else
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irq_status[3] = 0;
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irq_status[0] &= rtwpci->irq_mask[0];
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irq_status[1] &= rtwpci->irq_mask[1];
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irq_status[3] &= rtwpci->irq_mask[3];
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rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]);
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rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]);
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rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]);
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if (rtw_chip_wcpu_11ac(rtwdev))
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rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]);
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spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags);
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}
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