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arm64: dts: Add SC9863A clock nodes

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add clock devicetree nodes for SC9863A.

Link: https://lore.kernel.org/r/20200414101636.24503-2-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Chunyan Zhang 2020-04-14 18:16:35 +08:00 committed by Arnd Bergmann
parent 0e698dfa28
commit 78efc0199f
2 changed files with 188 additions and 0 deletions
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24
arch/arm64/boot/dts/sprd/sc9863a.dtsi
View File

@ -159,6 +159,30 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ap_clk: clock-controller@21500000 {
compatible = "sprd,sc9863a-ap-clk";
reg = <0 0x21500000 0 0x1000>;
clocks = <&ext_32k>, <&ext_26m>;
clock-names = "ext-32k", "ext-26m";
#clock-cells = <1>;
};
aon_clk: clock-controller@402d0000 {
compatible = "sprd,sc9863a-aon-clk";
reg = <0 0x402d0000 0 0x1000>;
clocks = <&ext_26m>, <&rco_100m>,
<&ext_32k>, <&ext_4m>;
clock-names = "ext-26m", "rco-100m",
"ext-32k", "ext-4m";
#clock-cells = <1>;
};
mm_clk: clock-controller@60900000 {
compatible = "sprd,sc9863a-mm-clk";
reg = <0 0x60900000 0 0x1000>;
#clock-cells = <1>;
};
funnel@10001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;

164
arch/arm64/boot/dts/sprd/sharkl3.dtsi
View File

@ -16,6 +16,149 @@
#size-cells = <2>;
ranges;
ap_ahb_regs: syscon@20e00000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x20e00000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20e00000 0x4000>;
apahb_gate: apahb-gate {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
};
};
pmu_regs: syscon@402b0000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x402b0000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x402b0000 0x4000>;
pmu_gate: pmu-gate {
compatible = "sprd,sc9863a-pmu-gate";
reg = <0 0x1200>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
aon_apb_regs: syscon@402e0000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x402e0000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x402e0000 0x4000>;
aonapb_gate: aonapb-gate {
compatible = "sprd,sc9863a-aonapb-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
};
};
anlg_phy_g2_regs: syscon@40353000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40353000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40353000 0x3000>;
pll: pll {
compatible = "sprd,sc9863a-pll";
reg = <0 0x100>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_g4_regs: syscon@40359000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40359000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40359000 0x3000>;
mpll: mpll {
compatible = "sprd,sc9863a-mpll";
reg = <0 0x100>;
#clock-cells = <1>;
};
};
anlg_phy_g5_regs: syscon@4035c000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x4035c000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x4035c000 0x3000>;
rpll: rpll {
compatible = "sprd,sc9863a-rpll";
reg = <0 0x100>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
anlg_phy_g7_regs: syscon@40363000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x40363000 0 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x40363000 0x3000>;
dpll: dpll {
compatible = "sprd,sc9863a-dpll";
reg = <0 0x100>;
#clock-cells = <1>;
};
};
mm_ahb_regs: syscon@60800000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x60800000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x60800000 0x3000>;
mm_gate: mm-gate {
compatible = "sprd,sc9863a-mm-gate";
reg = <0 0x1100>;
#clock-cells = <1>;
};
};
ap_apb_regs: syscon@71300000 {
compatible = "sprd,sc9863a-glbregs", "syscon",
"simple-mfd";
reg = <0 0x71300000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x71300000 0x4000>;
apapb_gate: apapb-gate {
compatible = "sprd,sc9863a-apapb-gate";
reg = <0 0x1000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
};
apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -75,4 +218,25 @@
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
ext_32k: ext-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext-32k";
};
ext_4m: ext-4m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <4000000>;
clock-output-names = "ext-4m";
};
rco_100m: rco-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "rco-100m";
};
};