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Merge branch 'i2c-fixes' of git://git.fluff.org/bjdooks/linux
* 'i2c-fixes' of git://git.fluff.org/bjdooks/linux: i2c-mpc: Do not generate STOP after read. i2c: imx: disable clock when it's possible to save power. i2c: imx: only imx1 needs disable delay i2c: imx: check busy bit when START/STOP
This commit is contained in:
Linus Torvalds
commit
78e1e34056
@ -120,19 +120,26 @@ struct imx_i2c_struct {
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wait_queue_head_t queue;
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unsigned long i2csr;
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unsigned int disable_delay;
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int stopped;
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unsigned int ifdr; /* IMX_I2C_IFDR */
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};
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/** Functions for IMX I2C adapter driver ***************************************
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*******************************************************************************/
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx)
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
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{
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unsigned long orig_jiffies = jiffies;
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unsigned int temp;
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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/* wait for bus not busy */
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while (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_IBB) {
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while (1) {
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temp = readb(i2c_imx->base + IMX_I2C_I2SR);
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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break;
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if (signal_pending(current)) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> I2C Interrupted\n", __func__);
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@ -179,41 +186,62 @@ static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
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return 0;
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}
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static void i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int temp = 0;
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int result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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clk_enable(i2c_imx->clk);
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writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
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/* Enable I2C controller */
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writeb(0, i2c_imx->base + IMX_I2C_I2SR);
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writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
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/* Wait controller to be stable */
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udelay(50);
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/* Start I2C transaction */
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp |= I2CR_MSTA;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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result = i2c_imx_bus_busy(i2c_imx, 1);
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if (result)
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return result;
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i2c_imx->stopped = 0;
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temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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return result;
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}
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static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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{
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unsigned int temp = 0;
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/* Stop I2C transaction */
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~I2CR_MSTA;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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/* setup chip registers to defaults */
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writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
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writeb(0, i2c_imx->base + IMX_I2C_I2SR);
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/*
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* This delay caused by an i.MXL hardware bug.
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* If no (or too short) delay, no "STOP" bit will be generated.
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*/
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udelay(i2c_imx->disable_delay);
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if (!i2c_imx->stopped) {
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/* Stop I2C transaction */
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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i2c_imx->stopped = 1;
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}
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if (cpu_is_mx1()) {
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/*
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* This delay caused by an i.MXL hardware bug.
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* If no (or too short) delay, no "STOP" bit will be generated.
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*/
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udelay(i2c_imx->disable_delay);
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}
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if (!i2c_imx->stopped)
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i2c_imx_bus_busy(i2c_imx, 0);
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/* Disable I2C controller */
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writeb(0, i2c_imx->base + IMX_I2C_I2CR);
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clk_disable(i2c_imx->clk);
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}
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static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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@ -233,8 +261,8 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
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else
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for (i = 0; i2c_clk_div[i][0] < div; i++);
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/* Write divider value to register */
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writeb(i2c_clk_div[i][1], i2c_imx->base + IMX_I2C_IFDR);
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/* Store divider value */
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i2c_imx->ifdr = i2c_clk_div[i][1];
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/*
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* There dummy delay is calculated.
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@ -341,11 +369,15 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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if (result)
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return result;
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if (i == (msgs->len - 1)) {
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/* It must generate STOP before read I2DR to prevent
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controller from generating another clock cycle */
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> clear MSTA\n", __func__);
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp &= ~I2CR_MSTA;
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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i2c_imx_bus_busy(i2c_imx, 0);
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i2c_imx->stopped = 1;
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} else if (i == (msgs->len - 2)) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> set TXAK\n", __func__);
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@ -370,14 +402,11 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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/* Check if i2c bus is not busy */
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result = i2c_imx_bus_busy(i2c_imx);
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/* Start I2C transfer */
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result = i2c_imx_start(i2c_imx);
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if (result)
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goto fail0;
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/* Start I2C transfer */
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i2c_imx_start(i2c_imx);
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/* read/write data */
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for (i = 0; i < num; i++) {
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if (i) {
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@ -386,6 +415,9 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp |= I2CR_RSTA;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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result = i2c_imx_bus_busy(i2c_imx, 1);
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if (result)
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goto fail0;
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}
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> transfer message: %d\n", __func__, i);
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@ -500,7 +532,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
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dev_err(&pdev->dev, "can't get I2C clock\n");
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goto fail3;
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}
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clk_enable(i2c_imx->clk);
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/* Request IRQ */
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ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
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@ -549,7 +580,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
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fail5:
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free_irq(i2c_imx->irq, i2c_imx);
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fail4:
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clk_disable(i2c_imx->clk);
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clk_put(i2c_imx->clk);
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fail3:
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release_mem_region(i2c_imx->res->start, resource_size(res));
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@ -586,8 +616,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
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if (pdata && pdata->exit)
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pdata->exit(&pdev->dev);
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/* Disable I2C clock */
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clk_disable(i2c_imx->clk);
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clk_put(i2c_imx->clk);
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release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
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@ -365,9 +365,6 @@ static int mpc_write(struct mpc_i2c *i2c, int target,
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unsigned timeout = i2c->adap.timeout;
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u32 flags = restart ? CCR_RSTA : 0;
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/* Start with MEN */
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if (!restart)
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writeccr(i2c, CCR_MEN);
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/* Start as master */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target byte */
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@ -396,9 +393,6 @@ static int mpc_read(struct mpc_i2c *i2c, int target,
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int i, result;
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u32 flags = restart ? CCR_RSTA : 0;
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/* Start with MEN */
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if (!restart)
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writeccr(i2c, CCR_MEN);
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/* Switch to read - restart */
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
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/* Write target address byte - this time with the read flag set */
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@ -425,9 +419,9 @@ static int mpc_read(struct mpc_i2c *i2c, int target,
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/* Generate txack on next to last byte */
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if (i == length - 2)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
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/* Generate stop on last byte */
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/* Do not generate stop on last byte */
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if (i == length - 1)
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
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writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
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data[i] = readb(i2c->base + MPC_I2C_DR);
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}
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