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clk: imx: add imx6ul clk tree support
Add imx6ul clock driver support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
05e062f92c
commit
787b4271a6
@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
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obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
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obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
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obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
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obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
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obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
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obj-$(CONFIG_SOC_VF610) += clk-vf610.o
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drivers/clk/imx/clk-imx6ul.c
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432
drivers/clk/imx/clk-imx6ul.c
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@ -0,0 +1,432 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/types.h>
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#include "clk.h"
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#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
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#define CCDR 0x4
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static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
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static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
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static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
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static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
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static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
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static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
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static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
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static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
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static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m", "pll2_bus", };
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static const char *step_sels[] = { "osc", "ca7_secondary_sel", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *axi_sels[] = {"periph", "axi_alt_sel", };
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static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
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static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
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static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", };
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static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
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static const char *sai_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
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static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
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static const char *sim_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
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static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
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static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
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static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
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static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
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static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
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static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
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static const char *ecspi_sels[] = { "pll3_60m", "osc", };
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static const char *uart_sels[] = { "pll3_80m", "osc", };
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static const char *perclk_sels[] = { "ipg", "osc", };
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static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
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static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static struct clk *clks[IMX6UL_CLK_END];
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static struct clk_onecell_data clk_data;
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static int const clks_init_on[] __initconst = {
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IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
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IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
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IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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{ .val = 0, .div = 20, },
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{ .val = 1, .div = 10, },
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{ .val = 2, .div = 5, },
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{ .val = 3, .div = 4, },
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{ }
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};
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static struct clk_div_table post_div_table[] = {
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{ .val = 2, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 4, },
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{ }
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};
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static struct clk_div_table video_div_table[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 2, .div = 1, },
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{ .val = 3, .div = 4, },
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{ }
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};
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static u32 share_count_asrc;
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static u32 share_count_audio;
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static u32 share_count_sai1;
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static u32 share_count_sai2;
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static u32 share_count_sai3;
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static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
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clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
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/* ipp_di clock is external input */
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clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
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clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
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clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
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clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
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clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
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clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
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clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
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clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
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clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT);
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/* Do not bypass PLLs initially */
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clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]);
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clk_set_parent(clks[IMX6UL_PLL2_BYPASS], clks[IMX6UL_CLK_PLL2]);
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clk_set_parent(clks[IMX6UL_PLL3_BYPASS], clks[IMX6UL_CLK_PLL3]);
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clk_set_parent(clks[IMX6UL_PLL4_BYPASS], clks[IMX6UL_CLK_PLL4]);
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clk_set_parent(clks[IMX6UL_PLL5_BYPASS], clks[IMX6UL_CLK_PLL5]);
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clk_set_parent(clks[IMX6UL_PLL6_BYPASS], clks[IMX6UL_CLK_PLL6]);
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clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]);
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clks[IMX6UL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
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clks[IMX6UL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
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clks[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
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clks[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
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clks[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
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clks[IMX6UL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
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clks[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
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/*
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* Bit 20 is the reserved and read-only bit, we do this only for:
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* - Do nothing for usbphy clk_enable/disable
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* - Keep refcount when do usbphy clk_enable/disable, in that case,
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* the clk framework many need to enable/disable usbphy's parent
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*/
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clks[IMX6UL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
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clks[IMX6UL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
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/*
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* usbphy*_gate needs to be on after system boots up, and software
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* never needs to control it anymore.
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*/
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clks[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
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clks[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
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/* name parent_name reg idx */
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clks[IMX6UL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clks[IMX6UL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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clks[IMX6UL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
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clks[IMX6UL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
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clks[IMX6UL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
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clks[IMX6UL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
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clks[IMX6UL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
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clks[IMX6UL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
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clks[IMX6UL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
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base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
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clks[IMX6UL_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
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base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
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clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
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clks[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
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clks[IMX6UL_CLK_ENET_PTP] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
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clks[IMX6UL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clks[IMX6UL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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/* name parent_name mult div */
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clks[IMX6UL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
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clks[IMX6UL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clks[IMX6UL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clks[IMX6UL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels));
|
||||
clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
|
||||
clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
|
||||
clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0);
|
||||
clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
|
||||
clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
|
||||
clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels));
|
||||
clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels));
|
||||
clks[IMX6UL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6UL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6UL_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels));
|
||||
clks[IMX6UL_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels));
|
||||
clks[IMX6UL_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels));
|
||||
clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
|
||||
clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
|
||||
clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
|
||||
clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
|
||||
clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
|
||||
clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
|
||||
clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
|
||||
clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
|
||||
clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
|
||||
clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
|
||||
clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
|
||||
|
||||
clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
|
||||
clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
|
||||
|
||||
clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
|
||||
clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
|
||||
clks[IMX6UL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "qspi1_sel", 1, 7);
|
||||
|
||||
clks[IMX6UL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
clks[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clks[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clks[IMX6UL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3);
|
||||
clks[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
|
||||
clks[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
|
||||
clks[IMX6UL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
|
||||
clks[IMX6UL_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
|
||||
clks[IMX6UL_CLK_GPMI_PODF] = imx_clk_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3);
|
||||
clks[IMX6UL_CLK_BCH_PODF] = imx_clk_divider("bch_podf", "bch_sel", base + 0x24, 19, 3);
|
||||
clks[IMX6UL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clks[IMX6UL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clks[IMX6UL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
|
||||
clks[IMX6UL_CLK_SAI3_PRED] = imx_clk_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3);
|
||||
clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6);
|
||||
clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3);
|
||||
clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6);
|
||||
clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3);
|
||||
clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6);
|
||||
clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
|
||||
clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
|
||||
clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
|
||||
clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
|
||||
|
||||
clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
/* CCGR0 */
|
||||
clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
|
||||
clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
|
||||
clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4);
|
||||
clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
|
||||
clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
|
||||
clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
|
||||
clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
|
||||
clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
|
||||
clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
|
||||
clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
|
||||
clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24);
|
||||
clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26);
|
||||
clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
|
||||
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
|
||||
clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
|
||||
|
||||
/* CCGR1 */
|
||||
clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
|
||||
clks[IMX6UL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
|
||||
clks[IMX6UL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
|
||||
clks[IMX6UL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
|
||||
clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8);
|
||||
clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
|
||||
clks[IMX6UL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10);
|
||||
clks[IMX6UL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
|
||||
clks[IMX6UL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
|
||||
clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16);
|
||||
clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
|
||||
clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
|
||||
clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
|
||||
clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
|
||||
|
||||
/* CCGR2 */
|
||||
clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2);
|
||||
clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
|
||||
clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
|
||||
clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
|
||||
clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
|
||||
clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
|
||||
clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
|
||||
clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
|
||||
|
||||
/* CCGR3 */
|
||||
clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2);
|
||||
clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2);
|
||||
clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
|
||||
clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4);
|
||||
clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
|
||||
clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
|
||||
clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
|
||||
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
|
||||
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
|
||||
clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
|
||||
clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
|
||||
clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28);
|
||||
|
||||
/* CCGR4 */
|
||||
clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12);
|
||||
clks[IMX6UL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
|
||||
clks[IMX6UL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
|
||||
clks[IMX6UL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
|
||||
clks[IMX6UL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
||||
clks[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24);
|
||||
clks[IMX6UL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26);
|
||||
clks[IMX6UL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc_podf", base + 0x78, 28);
|
||||
clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30);
|
||||
|
||||
/* CCGR5 */
|
||||
clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
|
||||
clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6UL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6UL_CLK_SAI3] = imx_clk_gate2_shared("sai3", "sai3_podf", base + 0x7c, 22, &share_count_sai3);
|
||||
clks[IMX6UL_CLK_SAI3_IPG] = imx_clk_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3);
|
||||
clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24);
|
||||
clks[IMX6UL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24);
|
||||
clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26);
|
||||
clks[IMX6UL_CLK_UART7_SERIAL] = imx_clk_gate2("uart7_serial", "uart_podf", base + 0x7c, 26);
|
||||
clks[IMX6UL_CLK_SAI1] = imx_clk_gate2_shared("sai1", "sai1_podf", base + 0x7c, 28, &share_count_sai1);
|
||||
clks[IMX6UL_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
|
||||
clks[IMX6UL_CLK_SAI2] = imx_clk_gate2_shared("sai2", "sai2_podf", base + 0x7c, 30, &share_count_sai2);
|
||||
clks[IMX6UL_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
|
||||
|
||||
/* CCGR6 */
|
||||
clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6);
|
||||
clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8);
|
||||
clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10);
|
||||
clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
|
||||
clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14);
|
||||
clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14);
|
||||
clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20);
|
||||
clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
|
||||
clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
|
||||
clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
|
||||
clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("Pwm7", "perclk", base + 0x80, 30);
|
||||
|
||||
/* mask handshake of mmdc */
|
||||
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/* set perclk to from OSC */
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);
|
||||
|
||||
clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000);
|
||||
clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
|
||||
clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
|
||||
|
||||
/* keep all the clks on just for bringup */
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]);
|
||||
clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
|
||||
|
||||
clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);
|
240
include/dt-bindings/clock/imx6ul-clock.h
Normal file
240
include/dt-bindings/clock/imx6ul-clock.h
Normal file
@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX6UL_H
|
||||
|
||||
#define IMX6UL_CLK_DUMMY 0
|
||||
#define IMX6UL_CLK_CKIL 1
|
||||
#define IMX6UL_CLK_CKIH 2
|
||||
#define IMX6UL_CLK_OSC 3
|
||||
#define IMX6UL_PLL1_BYPASS_SRC 4
|
||||
#define IMX6UL_PLL2_BYPASS_SRC 5
|
||||
#define IMX6UL_PLL3_BYPASS_SRC 6
|
||||
#define IMX6UL_PLL4_BYPASS_SRC 7
|
||||
#define IMX6UL_PLL5_BYPASS_SRC 8
|
||||
#define IMX6UL_PLL6_BYPASS_SRC 9
|
||||
#define IMX6UL_PLL7_BYPASS_SRC 10
|
||||
#define IMX6UL_CLK_PLL1 11
|
||||
#define IMX6UL_CLK_PLL2 12
|
||||
#define IMX6UL_CLK_PLL3 13
|
||||
#define IMX6UL_CLK_PLL4 14
|
||||
#define IMX6UL_CLK_PLL5 15
|
||||
#define IMX6UL_CLK_PLL6 16
|
||||
#define IMX6UL_CLK_PLL7 17
|
||||
#define IMX6UL_PLL1_BYPASS 18
|
||||
#define IMX6UL_PLL2_BYPASS 19
|
||||
#define IMX6UL_PLL3_BYPASS 20
|
||||
#define IMX6UL_PLL4_BYPASS 21
|
||||
#define IMX6UL_PLL5_BYPASS 22
|
||||
#define IMX6UL_PLL6_BYPASS 23
|
||||
#define IMX6UL_PLL7_BYPASS 24
|
||||
#define IMX6UL_CLK_PLL1_SYS 25
|
||||
#define IMX6UL_CLK_PLL2_BUS 26
|
||||
#define IMX6UL_CLK_PLL3_USB_OTG 27
|
||||
#define IMX6UL_CLK_PLL4_AUDIO 28
|
||||
#define IMX6UL_CLK_PLL5_VIDEO 29
|
||||
#define IMX6UL_CLK_PLL6_ENET 30
|
||||
#define IMX6UL_CLK_PLL7_USB_HOST 31
|
||||
#define IMX6UL_CLK_USBPHY1 32
|
||||
#define IMX6UL_CLK_USBPHY2 33
|
||||
#define IMX6UL_CLK_USBPHY1_GATE 34
|
||||
#define IMX6UL_CLK_USBPHY2_GATE 35
|
||||
#define IMX6UL_CLK_PLL2_PFD0 36
|
||||
#define IMX6UL_CLK_PLL2_PFD1 37
|
||||
#define IMX6UL_CLK_PLL2_PFD2 38
|
||||
#define IMX6UL_CLK_PLL2_PFD3 39
|
||||
#define IMX6UL_CLK_PLL3_PFD0 40
|
||||
#define IMX6UL_CLK_PLL3_PFD1 41
|
||||
#define IMX6UL_CLK_PLL3_PFD2 42
|
||||
#define IMX6UL_CLK_PLL3_PFD3 43
|
||||
#define IMX6UL_CLK_ENET_REF 44
|
||||
#define IMX6UL_CLK_ENET2_REF 45
|
||||
#define IMX6UL_CLK_ENET2_REF_125M 46
|
||||
#define IMX6UL_CLK_ENET_PTP_REF 47
|
||||
#define IMX6UL_CLK_ENET_PTP 48
|
||||
#define IMX6UL_CLK_PLL4_POST_DIV 49
|
||||
#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
|
||||
#define IMX6UL_CLK_PLL5_POST_DIV 51
|
||||
#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
|
||||
#define IMX6UL_CLK_PLL2_198M 53
|
||||
#define IMX6UL_CLK_PLL3_80M 54
|
||||
#define IMX6UL_CLK_PLL3_60M 55
|
||||
#define IMX6UL_CLK_STEP 56
|
||||
#define IMX6UL_CLK_PLL1_SW 57
|
||||
#define IMX6UL_CLK_AXI_ALT_SEL 58
|
||||
#define IMX6UL_CLK_AXI_SEL 59
|
||||
#define IMX6UL_CLK_PERIPH_PRE 60
|
||||
#define IMX6UL_CLK_PERIPH2_PRE 61
|
||||
#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
|
||||
#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
|
||||
#define IMX6UL_CLK_USDHC1_SEL 64
|
||||
#define IMX6UL_CLK_USDHC2_SEL 65
|
||||
#define IMX6UL_CLK_BCH_SEL 66
|
||||
#define IMX6UL_CLK_GPMI_SEL 67
|
||||
#define IMX6UL_CLK_EIM_SLOW_SEL 68
|
||||
#define IMX6UL_CLK_SPDIF_SEL 69
|
||||
#define IMX6UL_CLK_SAI1_SEL 70
|
||||
#define IMX6UL_CLK_SAI2_SEL 71
|
||||
#define IMX6UL_CLK_SAI3_SEL 72
|
||||
#define IMX6UL_CLK_LCDIF_PRE_SEL 73
|
||||
#define IMX6UL_CLK_SIM_PRE_SEL 74
|
||||
#define IMX6UL_CLK_LDB_DI0_SEL 75
|
||||
#define IMX6UL_CLK_LDB_DI1_SEL 76
|
||||
#define IMX6UL_CLK_ENFC_SEL 77
|
||||
#define IMX6UL_CLK_CAN_SEL 78
|
||||
#define IMX6UL_CLK_ECSPI_SEL 79
|
||||
#define IMX6UL_CLK_UART_SEL 80
|
||||
#define IMX6UL_CLK_QSPI1_SEL 81
|
||||
#define IMX6UL_CLK_PERCLK_SEL 82
|
||||
#define IMX6UL_CLK_LCDIF_SEL 83
|
||||
#define IMX6UL_CLK_SIM_SEL 84
|
||||
#define IMX6UL_CLK_PERIPH 85
|
||||
#define IMX6UL_CLK_PERIPH2 86
|
||||
#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
|
||||
#define IMX6UL_CLK_LDB_DI0_DIV_7 88
|
||||
#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
|
||||
#define IMX6UL_CLK_LDB_DI1_DIV_7 90
|
||||
#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
|
||||
#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
|
||||
#define IMX6UL_CLK_ARM 93
|
||||
#define IMX6UL_CLK_PERIPH_CLK2 94
|
||||
#define IMX6UL_CLK_PERIPH2_CLK2 95
|
||||
#define IMX6UL_CLK_AHB 96
|
||||
#define IMX6UL_CLK_MMDC_PODF 97
|
||||
#define IMX6UL_CLK_AXI_PODF 98
|
||||
#define IMX6UL_CLK_PERCLK 99
|
||||
#define IMX6UL_CLK_IPG 100
|
||||
#define IMX6UL_CLK_USDHC1_PODF 101
|
||||
#define IMX6UL_CLK_USDHC2_PODF 102
|
||||
#define IMX6UL_CLK_BCH_PODF 103
|
||||
#define IMX6UL_CLK_GPMI_PODF 104
|
||||
#define IMX6UL_CLK_EIM_SLOW_PODF 105
|
||||
#define IMX6UL_CLK_SPDIF_PRED 106
|
||||
#define IMX6UL_CLK_SPDIF_PODF 107
|
||||
#define IMX6UL_CLK_SAI1_PRED 108
|
||||
#define IMX6UL_CLK_SAI1_PODF 109
|
||||
#define IMX6UL_CLK_SAI2_PRED 110
|
||||
#define IMX6UL_CLK_SAI2_PODF 111
|
||||
#define IMX6UL_CLK_SAI3_PRED 112
|
||||
#define IMX6UL_CLK_SAI3_PODF 113
|
||||
#define IMX6UL_CLK_LCDIF_PRED 114
|
||||
#define IMX6UL_CLK_LCDIF_PODF 115
|
||||
#define IMX6UL_CLK_SIM_PODF 116
|
||||
#define IMX6UL_CLK_QSPI1_PDOF 117
|
||||
#define IMX6UL_CLK_ENFC_PRED 118
|
||||
#define IMX6UL_CLK_ENFC_PODF 119
|
||||
#define IMX6UL_CLK_CAN_PODF 120
|
||||
#define IMX6UL_CLK_ECSPI_PODF 121
|
||||
#define IMX6UL_CLK_UART_PODF 122
|
||||
#define IMX6UL_CLK_ADC1 123
|
||||
#define IMX6UL_CLK_ADC2 124
|
||||
#define IMX6UL_CLK_AIPSTZ1 125
|
||||
#define IMX6UL_CLK_AIPSTZ2 126
|
||||
#define IMX6UL_CLK_AIPSTZ3 127
|
||||
#define IMX6UL_CLK_APBHDMA 128
|
||||
#define IMX6UL_CLK_ASRC_IPG 129
|
||||
#define IMX6UL_CLK_ASRC_MEM 130
|
||||
#define IMX6UL_CLK_GPMI_BCH_APB 131
|
||||
#define IMX6UL_CLK_GPMI_BCH 132
|
||||
#define IMX6UL_CLK_GPMI_IO 133
|
||||
#define IMX6UL_CLK_GPMI_APB 134
|
||||
#define IMX6UL_CLK_CAAM_MEM 135
|
||||
#define IMX6UL_CLK_CAAM_ACLK 136
|
||||
#define IMX6UL_CLK_CAAM_IPG 137
|
||||
#define IMX6UL_CLK_CSI 138
|
||||
#define IMX6UL_CLK_ECSPI1 139
|
||||
#define IMX6UL_CLK_ECSPI2 140
|
||||
#define IMX6UL_CLK_ECSPI3 141
|
||||
#define IMX6UL_CLK_ECSPI4 142
|
||||
#define IMX6UL_CLK_EIM 143
|
||||
#define IMX6UL_CLK_ENET 144
|
||||
#define IMX6UL_CLK_ENET_AHB 145
|
||||
#define IMX6UL_CLK_EPIT1 146
|
||||
#define IMX6UL_CLK_EPIT2 147
|
||||
#define IMX6UL_CLK_CAN1_IPG 148
|
||||
#define IMX6UL_CLK_CAN1_SERIAL 149
|
||||
#define IMX6UL_CLK_CAN2_IPG 150
|
||||
#define IMX6UL_CLK_CAN2_SERIAL 151
|
||||
#define IMX6UL_CLK_GPT1_BUS 152
|
||||
#define IMX6UL_CLK_GPT1_SERIAL 153
|
||||
#define IMX6UL_CLK_GPT2_BUS 154
|
||||
#define IMX6UL_CLK_GPT2_SERIAL 155
|
||||
#define IMX6UL_CLK_I2C1 156
|
||||
#define IMX6UL_CLK_I2C2 157
|
||||
#define IMX6UL_CLK_I2C3 158
|
||||
#define IMX6UL_CLK_I2C4 159
|
||||
#define IMX6UL_CLK_IOMUXC 160
|
||||
#define IMX6UL_CLK_LCDIF_APB 161
|
||||
#define IMX6UL_CLK_LCDIF_PIX 162
|
||||
#define IMX6UL_CLK_MMDC_P0_FAST 163
|
||||
#define IMX6UL_CLK_MMDC_P0_IPG 164
|
||||
#define IMX6UL_CLK_OCOTP 165
|
||||
#define IMX6UL_CLK_OCRAM 166
|
||||
#define IMX6UL_CLK_PWM1 167
|
||||
#define IMX6UL_CLK_PWM2 168
|
||||
#define IMX6UL_CLK_PWM3 169
|
||||
#define IMX6UL_CLK_PWM4 170
|
||||
#define IMX6UL_CLK_PWM5 171
|
||||
#define IMX6UL_CLK_PWM6 172
|
||||
#define IMX6UL_CLK_PWM7 173
|
||||
#define IMX6UL_CLK_PWM8 174
|
||||
#define IMX6UL_CLK_PXP 175
|
||||
#define IMX6UL_CLK_QSPI 176
|
||||
#define IMX6UL_CLK_ROM 177
|
||||
#define IMX6UL_CLK_SAI1 178
|
||||
#define IMX6UL_CLK_SAI1_IPG 179
|
||||
#define IMX6UL_CLK_SAI2 180
|
||||
#define IMX6UL_CLK_SAI2_IPG 181
|
||||
#define IMX6UL_CLK_SAI3 182
|
||||
#define IMX6UL_CLK_SAI3_IPG 183
|
||||
#define IMX6UL_CLK_SDMA 184
|
||||
#define IMX6UL_CLK_SIM 185
|
||||
#define IMX6UL_CLK_SIM_S 186
|
||||
#define IMX6UL_CLK_SPBA 187
|
||||
#define IMX6UL_CLK_SPDIF 188
|
||||
#define IMX6UL_CLK_UART1_IPG 189
|
||||
#define IMX6UL_CLK_UART1_SERIAL 190
|
||||
#define IMX6UL_CLK_UART2_IPG 191
|
||||
#define IMX6UL_CLK_UART2_SERIAL 192
|
||||
#define IMX6UL_CLK_UART3_IPG 193
|
||||
#define IMX6UL_CLK_UART3_SERIAL 194
|
||||
#define IMX6UL_CLK_UART4_IPG 195
|
||||
#define IMX6UL_CLK_UART4_SERIAL 196
|
||||
#define IMX6UL_CLK_UART5_IPG 197
|
||||
#define IMX6UL_CLK_UART5_SERIAL 198
|
||||
#define IMX6UL_CLK_UART6_IPG 199
|
||||
#define IMX6UL_CLK_UART6_SERIAL 200
|
||||
#define IMX6UL_CLK_UART7_IPG 201
|
||||
#define IMX6UL_CLK_UART7_SERIAL 202
|
||||
#define IMX6UL_CLK_UART8_IPG 203
|
||||
#define IMX6UL_CLK_UART8_SERIAL 204
|
||||
#define IMX6UL_CLK_USBOH3 205
|
||||
#define IMX6UL_CLK_USDHC1 206
|
||||
#define IMX6UL_CLK_USDHC2 207
|
||||
#define IMX6UL_CLK_WDOG1 208
|
||||
#define IMX6UL_CLK_WDOG2 209
|
||||
#define IMX6UL_CLK_WDOG3 210
|
||||
#define IMX6UL_CLK_LDB_DI0 211
|
||||
#define IMX6UL_CLK_AXI 212
|
||||
#define IMX6UL_CLK_SPDIF_GCLK 213
|
||||
#define IMX6UL_CLK_GPT_3M 214
|
||||
#define IMX6UL_CLK_SIM2 215
|
||||
#define IMX6UL_CLK_SIM1 216
|
||||
#define IMX6UL_CLK_IPP_DI0 217
|
||||
#define IMX6UL_CLK_IPP_DI1 218
|
||||
#define IMX6UL_CA7_SECONDARY_SEL 219
|
||||
#define IMX6UL_CLK_PER_BCH 220
|
||||
#define IMX6UL_CLK_CSI_SEL 221
|
||||
#define IMX6UL_CLK_CSI_PODF 222
|
||||
#define IMX6UL_CLK_PLL3_120M 223
|
||||
|
||||
#define IMX6UL_CLK_END 224
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
|
Loading…
Reference in New Issue
Block a user