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ARM: tegra30: clk: Fix output_rate overflow
Change the type of variable from "unsigned long" to "u64". This avoids the overflow while clock rate calculating. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct clk_tegra *c = to_clk_tegra(hw);
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unsigned long input_rate = *prate;
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unsigned long output_rate = *prate;
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u64 output_rate = *prate;
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const struct clk_pll_freq_table *sel;
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struct clk_pll_freq_table cfg;
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int mul;
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