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mt76x0: unify freq offset parsing
Unify frequency offset parsing with mt76x2 driver using eeprom utility routines available in mt76x02-lib module Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@ -102,7 +102,8 @@ mt76x0_eeprom_param_read(struct seq_file *file, void *data)
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u16 val;
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int i;
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seq_printf(file, "RF freq offset: %hhx\n", dev->ee->rf_freq_off);
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seq_printf(file, "RF freq offset: %hhx\n",
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dev->caldata.freq_offset);
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seq_printf(file, "RSSI offset: %hhx %hhx\n",
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dev->caldata.rssi_offset[0], dev->caldata.rssi_offset[1]);
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seq_printf(file, "Temperature offset: %hhx\n",
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@ -103,23 +103,21 @@ static void mt76x0_set_temp_offset(struct mt76x0_dev *dev)
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dev->caldata.temp_offset = -10;
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}
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static void
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mt76x0_set_rf_freq_off(struct mt76x0_dev *dev, u8 *eeprom)
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static void mt76x0_set_freq_offset(struct mt76x0_dev *dev)
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{
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u8 comp;
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struct mt76x0_caldata *caldata = &dev->caldata;
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u8 val;
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comp = eeprom[MT_EE_FREQ_OFFSET_COMPENSATION];
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if (!mt76x02_field_valid(comp))
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comp = 0;
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val = mt76x02_eeprom_get(&dev->mt76, MT_EE_FREQ_OFFSET);
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if (!mt76x02_field_valid(val))
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val = 0;
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caldata->freq_offset = val;
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dev->ee->rf_freq_off = eeprom[MT_EE_FREQ_OFFSET];
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if (!mt76x02_field_valid(dev->ee->rf_freq_off))
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dev->ee->rf_freq_off = 0;
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val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TSSI_BOUND4) >> 8;
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if (!mt76x02_field_valid(val))
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val = 0;
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if (comp & BIT(7))
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dev->ee->rf_freq_off -= comp & 0x7f;
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else
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dev->ee->rf_freq_off += comp;
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caldata->freq_offset -= mt76x02_sign_extend(val, 8);
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}
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void mt76x0_read_rx_gain(struct mt76x0_dev *dev)
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@ -286,7 +284,7 @@ mt76x0_eeprom_init(struct mt76x0_dev *dev)
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mt76x02_mac_setaddr(&dev->mt76, eeprom + MT_EE_MAC_ADDR);
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mt76x0_set_chip_cap(dev, eeprom);
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mt76x0_set_rf_freq_off(dev, eeprom);
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mt76x0_set_freq_offset(dev);
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mt76x0_set_temp_offset(dev);
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dev->chainmask = 0x0101;
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@ -33,11 +33,10 @@ struct mt76x0_caldata {
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s8 lna_gain;
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s16 temp_offset;
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u8 freq_offset;
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};
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struct mt76x0_eeprom_params {
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u8 rf_freq_off;
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/* TX_PWR_CFG_* values from EEPROM for 20 and 40 Mhz bandwidths. */
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u32 tx_pwr_cfg_2g[5][2];
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u32 tx_pwr_cfg_5g[5][2];
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@ -942,7 +942,8 @@ mt76x0_rf_init(struct mt76x0_dev *dev)
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E1: B0.R22<6:0>: xo_cxo<6:0>
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E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1>
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*/
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rf_wr(dev, MT_RF(0, 22), min_t(u8, dev->ee->rf_freq_off, 0xBF));
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rf_wr(dev, MT_RF(0, 22),
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min_t(u8, dev->caldata.freq_offset, 0xbf));
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val = rf_rr(dev, MT_RF(0, 22));
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/*
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@ -74,7 +74,12 @@ enum mt76x02_eeprom_field {
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MT_EE_2G_TARGET_POWER = 0x0d0,
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MT_EE_TEMP_OFFSET = 0x0d1,
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MT_EE_TSSI_BOUND1 = 0x0d4,
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MT_EE_TSSI_BOUND2 = 0x0d6,
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MT_EE_TSSI_BOUND3 = 0x0d8,
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MT_EE_TSSI_BOUND4 = 0x0da,
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MT_EE_FREQ_OFFSET_COMPENSATION = 0x0db,
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MT_EE_TSSI_BOUND5 = 0x0dc,
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MT_EE_TX_POWER_BYRATE_BASE = 0x0de,
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MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2,
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