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soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR
i.MX8MP HDMI supports HDCP and HRV_MWR(HDMI RX Video Memory Write Master for RXRX validation), so add them. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -235,6 +235,13 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
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regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
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break;
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case IMX8MP_HDMIBLK_PD_HDCP:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
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break;
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case IMX8MP_HDMIBLK_PD_HRV:
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regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
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regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
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break;
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default:
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break;
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}
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@ -283,6 +290,13 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
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regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
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break;
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case IMX8MP_HDMIBLK_PD_HDCP:
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
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break;
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case IMX8MP_HDMIBLK_PD_HRV:
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regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
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regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
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break;
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default:
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break;
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}
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@ -365,6 +379,22 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
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.num_clks = 2,
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.gpc_name = "hdmi-tx-phy",
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},
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[IMX8MP_HDMIBLK_PD_HRV] = {
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.name = "hdmiblk-hrv",
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.clk_names = (const char *[]){ "axi", "apb" },
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.num_clks = 2,
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.gpc_name = "hrv",
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.path_names = (const char *[]){"hrv"},
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.num_paths = 1,
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},
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[IMX8MP_HDMIBLK_PD_HDCP] = {
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.name = "hdmiblk-hdcp",
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.clk_names = (const char *[]){ "axi", "apb" },
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.num_clks = 2,
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.gpc_name = "hdcp",
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.path_names = (const char *[]){"hdcp"},
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.num_paths = 1,
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},
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};
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static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
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