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ath9k_hw: Add support to reuse Carrier leak calibration
This patch adds support to reuse Carrier leak calibration during fast channel change for AR9480 chips. Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -905,8 +905,23 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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bool txiqcal_done = false;
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bool is_reusable = true;
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bool txiqcal_done = false, txclcal_done = false;
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bool is_reusable = true, txclcal_enabled;
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u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
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AR_PHY_CL_TAB_1,
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AR_PHY_CL_TAB_2 };
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txclcal_enabled = !!(REG_READ(ah, AR_PHY_CL_CAL_CTL) &
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AR_PHY_CL_CAL_ENABLE);
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if (txclcal_enabled) {
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if (caldata && caldata->done_txclcal_once)
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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else
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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}
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/* Do Tx IQ Calibration */
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
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@ -950,6 +965,33 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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else if (caldata && caldata->done_txiqcal_once)
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ar9003_hw_tx_iq_cal_reload(ah);
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#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
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if (caldata && txclcal_enabled) {
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int i, j;
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txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_CLC_SUCCESS);
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if (caldata->done_txclcal_once) {
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->txchainmask & (1 << i)))
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continue;
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for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
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REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
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caldata->tx_clcal[i][j]);
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}
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} else if (is_reusable && txclcal_done) {
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (!(ah->txchainmask & (1 << i)))
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continue;
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for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
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caldata->tx_clcal[i][j] =
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REG_READ(ah,
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CL_TAB_ENTRY(cl_idx[i]));
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}
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caldata->done_txclcal_once = true;
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}
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}
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#undef CL_TAB_ENTRY
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ath9k_hw_loadnf(ah, chan);
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ath9k_hw_start_nfcal(ah, true);
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@ -1707,8 +1707,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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ath9k_hw_init_bb(ah, chan);
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if (caldata)
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if (caldata) {
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caldata->done_txiqcal_once = false;
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caldata->done_txclcal_once = false;
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}
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if (!ath9k_hw_init_cal(ah, chan))
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return -EIO;
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@ -338,6 +338,7 @@ enum ath9k_int {
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CHANNEL_HT40MINUS)
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#define MAX_IQCAL_MEASUREMENT 8
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#define MAX_CL_TAB_ENTRY 16
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struct ath9k_hw_cal_data {
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u16 channel;
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@ -349,10 +350,12 @@ struct ath9k_hw_cal_data {
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bool nfcal_pending;
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bool nfcal_interference;
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bool done_txiqcal_once;
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bool done_txclcal_once;
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u16 small_signal_gain[AR9300_MAX_CHAINS];
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u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
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u32 num_measures[AR9300_MAX_CHAINS];
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int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
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u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
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struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
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};
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