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drm/radeon/kms: skip cb/db checking if SX_MISC is 1 on r600+

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Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Marek Olšák 2012-03-08 00:56:00 +01:00 committed by Dave Airlie
parent 9c1dfc5574
commit 779923bc40
5 changed files with 16 additions and 3 deletions
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8
drivers/gpu/drm/radeon/evergreen_cs.c
View File

@ -85,6 +85,7 @@ struct evergreen_cs_track {
u32 db_s_write_offset;
struct radeon_bo *db_s_read_bo;
struct radeon_bo *db_s_write_bo;
bool sx_misc_kill_all_prims;
};
static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
@ -162,6 +163,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
}
track->sx_misc_kill_all_prims = false;
}
struct eg_surface {
@ -821,6 +823,9 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
}
}
if (track->sx_misc_kill_all_prims)
return 0;
/* check that we have a cb for each enabled target
*/
tmp = track->cb_target_mask;
@ -1748,6 +1753,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
}
ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
break;
case SX_MISC:
track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
break;
default:
dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
return -EINVAL;

8
drivers/gpu/drm/radeon/r600_cs.c
View File

@ -74,6 +74,7 @@ struct r600_cs_track {
u32 db_offset;
struct radeon_bo *db_bo;
u64 db_bo_mc;
bool sx_misc_kill_all_prims;
};
#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
@ -322,6 +323,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
}
track->sx_misc_kill_all_prims = false;
}
static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
@ -479,6 +481,9 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
}
}
if (track->sx_misc_kill_all_prims)
return 0;
/* check that we have a cb for each enabled target, we don't check
* shader_mask because it seems mesa isn't always setting it :(
*/
@ -1279,6 +1284,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
}
ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
break;
case SX_MISC:
track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
break;
default:
dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
return -EINVAL;

1
drivers/gpu/drm/radeon/reg_srcs/cayman
View File

@ -208,7 +208,6 @@ cayman 0x9400
0x00028344 PA_SC_VPORT_ZMAX_14
0x00028348 PA_SC_VPORT_ZMIN_15
0x0002834C PA_SC_VPORT_ZMAX_15
0x00028350 SX_MISC
0x00028354 SX_SURFACE_SYNC
0x0002835C SX_SCATTER_EXPORT_SIZE
0x00028380 SQ_VTX_SEMANTIC_0

1
drivers/gpu/drm/radeon/reg_srcs/evergreen
View File

@ -224,7 +224,6 @@ evergreen 0x9400
0x00028344 PA_SC_VPORT_ZMAX_14
0x00028348 PA_SC_VPORT_ZMIN_15
0x0002834C PA_SC_VPORT_ZMAX_15
0x00028350 SX_MISC
0x00028354 SX_SURFACE_SYNC
0x00028380 SQ_VTX_SEMANTIC_0
0x00028384 SQ_VTX_SEMANTIC_1

1
drivers/gpu/drm/radeon/reg_srcs/r600
View File

@ -438,7 +438,6 @@ r600 0x9400
0x00028638 SPI_VS_OUT_ID_9
0x00028438 SX_ALPHA_REF
0x00028410 SX_ALPHA_TEST_CONTROL
0x00028350 SX_MISC
0x00028354 SX_SURFACE_SYNC
0x00009014 SX_MEMORY_EXPORT_SIZE
0x00009604 TC_INVALIDATE