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MIPS: Cavium: Add CPU hotplugging code.
Thanks to Cavium Inc. for the code contribution and help. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
9801b321ec
commit
773cb77d0e
@ -601,6 +601,7 @@ config CAVIUM_OCTEON_SIMULATOR
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_HOTPLUG_CPU
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select SYS_HAS_CPU_CAVIUM_OCTEON
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help
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The Octeon simulator is software performance model of the Cavium
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@ -615,6 +616,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_HOTPLUG_CPU
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select SYS_HAS_EARLY_PRINTK
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select SYS_HAS_CPU_CAVIUM_OCTEON
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select SWAP_IO_SPACE
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@ -501,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void)
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}
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
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{
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unsigned int isset;
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#ifdef CONFIG_SMP
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int coreid = cpu_logical_map(cpu);
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#else
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int coreid = cvmx_get_core_num();
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#endif
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int bit = (irq < OCTEON_IRQ_WDOG0) ?
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irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
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if (irq < 64) {
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isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
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(1ull << bit)) >> bit;
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} else {
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isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
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(1ull << bit)) >> bit;
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}
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return isset;
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}
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void fixup_irqs(void)
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{
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int irq;
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for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
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octeon_irq_core_disable_local(irq);
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for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
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if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
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/* ciu irq migrates to next cpu */
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octeon_irq_chip_ciu0.disable(irq);
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octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
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}
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}
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#if 0
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for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
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octeon_irq_mailbox_mask(irq);
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#endif
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for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
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if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
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/* ciu irq migrates to next cpu */
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octeon_irq_chip_ciu0.disable(irq);
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octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
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}
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}
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for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
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if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
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/* ciu irq migrates to next cpu */
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octeon_irq_chip_ciu1.disable(irq);
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octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
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}
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}
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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70
arch/mips/cavium-octeon/octeon_boot.h
Normal file
70
arch/mips/cavium-octeon/octeon_boot.h
Normal file
@ -0,0 +1,70 @@
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/*
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* (C) Copyright 2004, 2005 Cavium Networks
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __OCTEON_BOOT_H__
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#define __OCTEON_BOOT_H__
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#include <linux/types.h>
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struct boot_init_vector {
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uint32_t stack_addr;
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uint32_t code_addr;
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uint32_t app_start_func_addr;
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uint32_t k0_val;
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uint32_t flags;
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uint32_t boot_info_addr;
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uint32_t pad;
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uint32_t pad2;
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};
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/* similar to bootloader's linux_app_boot_info but without global data */
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struct linux_app_boot_info {
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uint32_t labi_signature;
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uint32_t start_core0_addr;
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uint32_t avail_coremask;
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uint32_t pci_console_active;
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uint32_t icache_prefetch_disable;
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uint32_t InitTLBStart_addr;
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uint32_t start_app_addr;
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uint32_t cur_exception_base;
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uint32_t no_mark_private_data;
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uint32_t compact_flash_common_base_addr;
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uint32_t compact_flash_attribute_base_addr;
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uint32_t led_display_base_addr;
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};
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/* If not to copy a lot of bootloader's structures
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here is only offset of requested member */
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#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c
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/* hardcoded in bootloader */
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#define LABI_ADDR_IN_BOOTLOADER 0x700
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#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
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#define LABI_SIGNATURE 0xAABBCCDD
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/* from uboot-headers/octeon_mem_map.h */
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#define EXCEPTION_BASE_INCR (4 * 1024)
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/* Increment size for exception base addresses (4k minimum) */
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#define EXCEPTION_BASE_BASE 0
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#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800)
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#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE)
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#endif /* __OCTEON_BOOT_H__ */
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@ -5,6 +5,7 @@
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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@ -19,10 +20,16 @@
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#include <asm/octeon/octeon.h>
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#include "octeon_boot.h"
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volatile unsigned long octeon_processor_boot = 0xff;
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volatile unsigned long octeon_processor_sp;
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volatile unsigned long octeon_processor_gp;
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#ifdef CONFIG_HOTPLUG_CPU
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static unsigned int InitTLBStart_addr;
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#endif
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static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
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{
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const int coreid = cvmx_get_core_num();
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@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
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}
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/**
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* Detect available CPUs, populate phys_cpu_present_map
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* Detect available CPUs, populate cpu_possible_map
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*/
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static void octeon_smp_hotplug_setup(void)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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uint32_t labi_signature;
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labi_signature =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof(struct linux_app_boot_info,
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labi_signature)));
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if (labi_signature != LABI_SIGNATURE)
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pr_err("The bootloader version on this board is incorrect\n");
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InitTLBStart_addr =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof(struct linux_app_boot_info,
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InitTLBStart_addr)));
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#endif
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}
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static void octeon_smp_setup(void)
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{
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const int coreid = cvmx_get_core_num();
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@ -91,6 +118,9 @@ static void octeon_smp_setup(void)
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cpus++;
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}
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}
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cpu_present_map = cpu_possible_map;
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octeon_smp_hotplug_setup();
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}
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/**
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@ -128,6 +158,17 @@ static void octeon_init_secondary(void)
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const int coreid = cvmx_get_core_num();
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union cvmx_ciu_intx_sum0 interrupt_enable;
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#ifdef CONFIG_HOTPLUG_CPU
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unsigned int cur_exception_base;
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cur_exception_base = cvmx_read64_uint32(
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CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof(struct linux_app_boot_info,
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cur_exception_base)));
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/* cur_exception_base is incremented in bootloader after setting */
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write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
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#endif
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octeon_check_cpu_bist();
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octeon_init_cvmcount();
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/*
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@ -199,6 +240,193 @@ static void octeon_cpus_done(void)
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#endif
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/* State of each CPU. */
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DEFINE_PER_CPU(int, cpu_state);
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extern void fixup_irqs(void);
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static DEFINE_SPINLOCK(smp_reserve_lock);
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static int octeon_cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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if (cpu == 0)
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return -EBUSY;
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spin_lock(&smp_reserve_lock);
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cpu_clear(cpu, cpu_online_map);
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cpu_clear(cpu, cpu_callin_map);
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local_irq_disable();
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fixup_irqs();
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local_irq_enable();
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flush_cache_all();
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local_flush_tlb_all();
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spin_unlock(&smp_reserve_lock);
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return 0;
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}
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static void octeon_cpu_die(unsigned int cpu)
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{
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int coreid = cpu_logical_map(cpu);
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uint32_t avail_coremask;
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struct cvmx_bootmem_named_block_desc *block_desc;
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#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG
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/* Disable the watchdog */
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cvmx_ciu_wdogx_t ciu_wdog;
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ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu));
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ciu_wdog.s.mode = 0;
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cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64);
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#endif
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while (per_cpu(cpu_state, cpu) != CPU_DEAD)
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cpu_relax();
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/*
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* This is a bit complicated strategics of getting/settig available
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* cores mask, copied from bootloader
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*/
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/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
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block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
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if (!block_desc) {
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avail_coremask =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof
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(struct linux_app_boot_info,
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avail_coremask)));
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} else { /* alternative, already initialized */
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avail_coremask =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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block_desc->base_addr +
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AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
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}
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avail_coremask |= 1 << coreid;
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/* Setting avail_coremask for bootoct binary */
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if (!block_desc) {
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cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof(struct linux_app_boot_info,
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avail_coremask)),
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avail_coremask);
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} else {
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cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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block_desc->base_addr +
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AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
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avail_coremask);
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}
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pr_info("Reset core %d. Available Coremask = %x \n", coreid,
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avail_coremask);
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cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
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cvmx_write_csr(CVMX_CIU_PP_RST, 0);
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}
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void play_dead(void)
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{
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int coreid = cvmx_get_core_num();
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idle_task_exit();
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octeon_processor_boot = 0xff;
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per_cpu(cpu_state, coreid) = CPU_DEAD;
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while (1) /* core will be reset here */
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;
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}
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extern void kernel_entry(unsigned long arg1, ...);
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static void start_after_reset(void)
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{
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kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
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}
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int octeon_update_boot_vector(unsigned int cpu)
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{
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int coreid = cpu_logical_map(cpu);
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unsigned int avail_coremask;
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struct cvmx_bootmem_named_block_desc *block_desc;
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struct boot_init_vector *boot_vect =
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(struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
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BOOTLOADER_BOOT_VECTOR);
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block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
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if (!block_desc) {
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avail_coremask =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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LABI_ADDR_IN_BOOTLOADER +
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offsetof(struct linux_app_boot_info,
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avail_coremask)));
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} else { /* alternative, already initialized */
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avail_coremask =
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cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
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block_desc->base_addr +
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AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
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}
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if (!(avail_coremask & (1 << coreid))) {
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/* core not available, assume, that catched by simple-executive */
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cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
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cvmx_write_csr(CVMX_CIU_PP_RST, 0);
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}
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boot_vect[coreid].app_start_func_addr =
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(uint32_t) (unsigned long) start_after_reset;
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boot_vect[coreid].code_addr = InitTLBStart_addr;
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CVMX_SYNC;
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cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
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return 0;
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}
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static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned long)hcpu;
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switch (action) {
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case CPU_UP_PREPARE:
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octeon_update_boot_vector(cpu);
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break;
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case CPU_ONLINE:
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pr_info("Cpu %d online\n", cpu);
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break;
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case CPU_DEAD:
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
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.notifier_call = octeon_cpu_callback,
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};
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static int __cpuinit register_cavium_notifier(void)
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{
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register_hotcpu_notifier(&octeon_cpu_notifier);
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return 0;
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}
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late_initcall(register_cavium_notifier);
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#endif /* CONFIG_HOTPLUG_CPU */
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struct plat_smp_ops octeon_smp_ops = {
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.send_ipi_single = octeon_send_ipi_single,
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.send_ipi_mask = octeon_send_ipi_mask,
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@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = {
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.boot_secondary = octeon_boot_secondary,
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.smp_setup = octeon_smp_setup,
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.prepare_cpus = octeon_prepare_cpus,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = octeon_cpu_disable,
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.cpu_die = octeon_cpu_die,
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#endif
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};
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@ -41,7 +41,7 @@ extern int __cpu_logical_map[NR_CPUS];
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/* Octeon - Tell another core to flush its icache */
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#define SMP_ICACHE_FLUSH 0x4
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extern cpumask_t cpu_callin_map;
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extern volatile cpumask_t cpu_callin_map;
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|
||||
extern void asmlinkage smp_bootstrap(void);
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user