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[PATCH] m68knommu: 532x UART support
ColdFire serial driver support for the new 532x CPU family UARTs. Patch submitted by Matt Waddel <Matt.Waddel@freescale.com>. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -60,11 +60,11 @@ struct timer_list mcfrs_timer_struct;
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#if defined(CONFIG_HW_FEITH)
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#define CONSOLE_BAUD_RATE 38400
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#define DEFAULT_CBAUD B38400
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#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB)
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#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || defined(CONFIG_M5329EVB)
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#define CONSOLE_BAUD_RATE 115200
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#define DEFAULT_CBAUD B115200
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#elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
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defined(CONFIG_senTec) || defined(CONFIG_SNEHA)
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defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET)
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#define CONSOLE_BAUD_RATE 19200
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#define DEFAULT_CBAUD B19200
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#endif
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@ -93,7 +93,7 @@ static struct tty_driver *mcfrs_serial_driver;
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#undef SERIAL_DEBUG_FLOW
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x)
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defined(CONFIG_M520x) || defined(CONFIG_M532x)
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#define IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
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#else
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#define IRQBASE 73
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@ -1545,6 +1545,28 @@ static void mcfrs_irqinit(struct mcf_serial *info)
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*feci2c_par |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2
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| MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
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}
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#elif defined(CONFIG_M532x)
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volatile unsigned char *uartp;
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uartp = info->addr;
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switch (info->line) {
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case 0:
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MCF_INTC0_ICR26 = 0x3;
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MCF_INTC0_CIMR = 26;
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/* GPIO initialization */
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MCF_GPIO_PAR_UART |= 0x000F;
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break;
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case 1:
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MCF_INTC0_ICR27 = 0x3;
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MCF_INTC0_CIMR = 27;
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/* GPIO initialization */
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MCF_GPIO_PAR_UART |= 0x0FF0;
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break;
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case 2:
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MCF_INTC0_ICR28 = 0x3;
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MCF_INTC0_CIMR = 28;
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/* GPIOs also must be initalized, depends on board */
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break;
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}
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#else
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volatile unsigned char *icrp, *uartp;
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