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ath9k_hw: Fix PLL initialization for AR9485.

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Increase the delay to make sure the initialization of pll
passes.

Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vivek Natarajan 2011-03-10 11:05:42 +05:30 committed by John W. Linville
parent 7ea1362c5d
commit 75e0351245
1 changed files with 2 additions and 2 deletions
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4
drivers/net/wireless/ath/ath9k/hw.c
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@ -701,7 +701,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
udelay(100);
udelay(1000);
REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
@ -713,7 +713,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
udelay(110);
udelay(1000);
}
pll = ath9k_hw_compute_pll_control(ah, chan);