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ARM: SoC devicetree updates for 3.16

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As with previous release, this continues to be among the largest branches
 we merge, with lots of new contents.
 
 New things for this release are among other things:
 
 - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request)
 - Qualcomm APQ8064 and APQ8084 SoCs and eval boards
 - Nvidia Jetson TK1 development board (Tegra T124-based)
 
 Two new SoCs that didn't need enough new platform code to stand out
 enough for me to notice when writing the SoC tag, but that adds new DT
 contents are:
 
 - TI DRA72
 - Marvell Berlin 2Q
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Merge tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC devicetree updates from Olof Johansson:
 "As with previous release, this continues to be among the largest
  branches we merge, with lots of new contents.

  New things for this release are among other things:

   - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request)
   - Qualcomm APQ8064 and APQ8084 SoCs and eval boards
   - Nvidia Jetson TK1 development board (Tegra T124-based)

  Two new SoCs that didn't need enough new platform code to stand out
  enough for me to notice when writing the SoC tag, but that adds new DT
  contents are:

   - TI DRA72
   - Marvell Berlin 2Q"

* tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (500 commits)
  ARM: dts: add secure firmware support for exynos5420-arndale-octa
  ARM: dts: add pmu sysreg node to exynos3250
  ARM: dts: correct the usb phy node in exynos5800-peach-pi
  ARM: dts: correct the usb phy node in exynos5420-peach-pit
  ARM: dts: add dts files for exynos5410 and exynos5410-smdk5410
  ARM: dts: add dts files for exynos3250 SoC
  ARM: dts: add mfc node for exynos5800
  ARM: dts: add Vbus regulator for USB 3.0 on exynos5800-peach-pi
  ARM: dts: enable fimd for exynos5800-peach-pi
  ARM: dts: enable display controller for exynos5800-peach-pi
  ARM: dts: enable hdmi for exynos5800-peach-pi
  ARM: dts: add dts file for exynos5800-peach-pi board
  ARM: dts: add dts file for exynos5800 SoC
  ARM: dts: add dts file for exynos5260-xyref5260 board
  ARM: dts: add dts files for exynos5260 SoC
  ARM: dts: update watchdog node name in exynos5440
  ARM: dts: use key code macros on Origen and Arndale boards
  ARM: dts: enable RTC and WDT nodes on Origen boards
  ARM: dts: qcom: Add APQ8084-MTP board support
  ARM: dts: qcom: Add APQ8084 SoC support
  ...
This commit is contained in:
Linus Torvalds 2014-06-02 16:34:00 -07:00
commit 755a9ba7bf
368 changed files with 24590 additions and 2092 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
Documentation/devicetree/bindings/arm/marvell,berlin.txt
View File

@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
* Example:
@ -22,3 +23,104 @@ SoC and board used. Currently known SoC compatibles are:
...
}
* Marvell Berlin2 chip control binding
Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with pinmux, padmux, clock, reset, and secondary
CPU boot address. Unfortunately, the individual registers are spread among the
chip control registers, so there should be a single DT node only providing the
different functions which are described below.
Required properties:
- compatible: shall be one of
"marvell,berlin2-chip-ctrl" for BG2
"marvell,berlin2cd-chip-ctrl" for BG2CD
"marvell,berlin2q-chip-ctrl" for BG2Q
- reg: address and length of following register sets for
BG2/BG2CD: chip control register set
BG2Q: chip control register set and cpu pll registers
* Marvell Berlin2 system control binding
Marvell Berlin SoCs have a system control register set providing several
individual registers dealing with pinmux, padmux, and reset.
Required properties:
- compatible: should be one of
"marvell,berlin2-system-ctrl" for BG2
"marvell,berlin2cd-system-ctrl" for BG2CD
"marvell,berlin2q-system-ctrl" for BG2Q
- reg: address and length of the system control register set
* Clock provider binding
As clock related registers are spread among the chip control registers, the
chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
SoCs share the same IP for PLLs and clocks, with some minor differences in
features and register layout.
Required properties:
- #clock-cells: shall be set to 1
- clocks: clock specifiers referencing the core clock input clocks
- clock-names: array of strings describing the input clock specifiers above.
Allowed clock-names for the reference clocks are
"refclk" for the SoCs osciallator input on all SoCs,
and SoC-specific input clocks for
BG2/BG2CD: "video_ext0" for the external video clock input
Clocks provided by core clocks shall be referenced by a clock specifier
indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
for the corresponding index mapping.
* Pin controller binding
Pin control registers are part of both register sets, chip control and system
control. The pins controlled are organized in groups, so no actual pin
information is needed.
A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and the muxing
function used.
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
a 'function' in the pin-controller subsystem.
Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.
Example:
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
reg = <0xea0000 0x400>;
clocks = <&refclk>, <&externaldev 0>;
clock-names = "refclk", "video_ext0";
spi1_pmux: spi1-pmux {
groups = "G0";
function = "spi1";
};
};
sysctrl: system-controller@d000 {
compatible = "marvell,berlin2-system-ctrl";
reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux {
groups = "GSM4";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM5";
function = "uart1";
};
uart2_pmux: uart2-pmux {
groups = "GSM3";
function = "uart2";
};
};

18
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -80,7 +80,10 @@ SoCs:
compatible = "ti,omap5432", "ti,omap5"
- DRA742
compatible = "ti,dra7xx", "ti,dra7"
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
- DRA722
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
- AM4372
compatible = "ti,am4372", "ti,am43"
@ -102,6 +105,12 @@ Boards:
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
compatible = "ti,omap3-evm", "ti,omap3"
@ -120,5 +129,8 @@ Boards:
- AM437x GP EVM
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
- DRA7 EVM: Software Developement Board for DRA7XX
compatible = "ti,dra7-evm", "ti,dra7"
- DRA742 EVM: Software Developement Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
- DRA722 EVM: Software Development Board for DRA722
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"

10
Documentation/devicetree/bindings/arm/rockchip.txt Normal file
View File

@ -0,0 +1,10 @@
Rockchip platforms device tree bindings
---------------------------------------
- bq Curie 2 tablet:
Required root node properties:
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
- Radxa Rock board:
Required root node properties:
- compatible = "radxa,rock", "rockchip,rk3188";

4
Documentation/devicetree/bindings/arm/samsung/pmu.txt
View File

@ -2,6 +2,10 @@ SAMSUNG Exynos SoC series PMU Registers
Properties:
- compatible : should contain two values. First value must be one from following list:
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
second value must be always "syscon".

11
Documentation/devicetree/bindings/arm/samsung/sysreg.txt
View File

@ -1,8 +1,10 @@
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
Properties:
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
- compatible : should contain two values. First value must be one from following list:
- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
second value must be always "syscon".
- reg : offset and length of the register set.
Example:
@ -10,3 +12,8 @@ Example:
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
syscon@10050000 {
compatible = "samsung,exynos5-sysreg", "syscon";
reg = <0x10050000 0x5000>;
};

4
Documentation/devicetree/bindings/clock/altr_socfpga.txt
View File

@ -21,8 +21,8 @@ Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
and the bit index.
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
and width.
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
the divider register, bit shift, and width.
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

2
Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt → Documentation/devicetree/bindings/reset/socfpga-reset.txt
View File

@ -3,9 +3,11 @@ Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)
- #reset-cells: 1
Example:
rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};

78
Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt Normal file
View File

@ -0,0 +1,78 @@
QCOM GSBI (General Serial Bus Interface) Driver
The GSBI controller is modeled as a node with zero or more child nodes, each
representing a serial sub-node device that is mux'd as part of the GSBI
configuration settings. The mode setting will govern the input/output mode of
the 4 GSBI IOs.
Required properties:
- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
- reg: Address range for GSBI registers
- clocks: required clock
- clock-names: must contain "iface" entry
- qcom,mode : indicates MUX value for configuration of the serial interface.
Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
Optional properties:
- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
Required properties if child node exists:
- #address-cells: Must be 1
- #size-cells: Must be 1
- ranges: Must be present
Properties for children:
A GSBI controller node can contain 0 or more child nodes representing serial
devices. These serial devices can be a QCOM UART, I2C controller, spi
controller, or some combination of aforementioned devices.
See the following for child node definitions:
Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
Example for APQ8064:
#include <dt-bindings/soc/qcom,gsbi.h>
gsbi4@16300000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16300000 0x100>;
clocks = <&gcc GSBI4_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,mode = <GSBI_PROT_I2C_UART>;
qcom,crci = <GSBI_CRCI_QUP>;
/* child nodes go under here */
i2c_qup4: i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16380000 0x1000>;
interrupts = <0 153 0>;
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
clock-frequency = <200000>;
#address-cells = <1>;
#size-cells = <0>;
};
uart4: serial@16340000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x1000>,
<0x16300000 0x1000>;
interrupts = <0 152 0x0>;
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "ok";
};
};

4
Documentation/devicetree/bindings/usb/omap-usb.txt
View File

@ -44,7 +44,9 @@ Board specific device node entry
};
OMAP DWC3 GLUE
- compatible : Should be "ti,dwc3"
- compatible : Should be
* "ti,dwc3" for OMAP5 and DRA7
* "ti,am437x-dwc3" for AM437x
- ti,hwmods : Should be "usb_otg_ss"
- reg : Address and length of the register set for the device.
- interrupts : The irq number of this device that is used to interrupt the

4
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -79,6 +79,7 @@ microchip Microchip Technology Inc.
mosaixtech Mosaix Technologies, Inc.
moxa Moxa
mpl MPL AG
mundoreader Mundo Reader S.L.
mxicy Macronix International Co., Ltd.
national National Semiconductor
neonode Neonode Inc.
@ -98,6 +99,7 @@ powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc
qnap QNAP Systems, Inc.
radxa Radxa
raidsonic RaidSonic Technology GmbH
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
@ -123,10 +125,12 @@ stericsson ST-Ericsson
synology Synology, Inc.
ti Texas Instruments
tlm Trusted Logic Mobility
toradex Toradex AG
toshiba Toshiba Corporation
toumaz Toumaz
usi Universal Scientifc Industrial Co., Ltd.
v3 V3 Semiconductor
variscite Variscite Ltd.
via VIA Technologies, Inc.
voipac Voipac Technologies s.r.o.
winbond Winbond Electronics corp.

124
arch/arm/boot/dts/Makefile
View File

@ -57,7 +57,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
bcm21664-garnet.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb
berlin2cd-google-chromecast.dtb \
berlin2q-marvell-dmp.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
@ -73,11 +74,14 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5260-xyref5260.dtb \
exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
exynos5440-ssdk5440.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
@ -129,6 +133,9 @@ kirkwood := \
kirkwood-nsa310a.dtb \
kirkwood-openblocks_a6.dtb \
kirkwood-openblocks_a7.dtb \
kirkwood-openrd-base.dtb \
kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \
kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-a0.dtb \
kirkwood-rd88f6281-a1.dtb \
@ -159,10 +166,12 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb \
imx50-evk.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
imx51-babbage.dtb \
imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx53-ard.dtb \
imx53-m53evk.dtb \
@ -181,6 +190,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-gw54xx.dtb \
imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
@ -205,6 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-udoo.dtb \
imx6q-wandboard.dtb \
imx6sl-evk.dtb \
vf610-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@ -232,73 +244,80 @@ dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
nspire-tp.dtb \
nspire-clp.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap2430-sdp.dtb \
dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \
omap2420-n800.dtb \
omap2420-n810.dtb \
omap2420-n810-wimax.dtb \
omap2430-sdp.dtb
dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
omap3-cm-t3517.dtb \
omap3-sbc-t3517.dtb \
omap3-cm-t3530.dtb \
omap3-sbc-t3530.dtb \
omap3-cm-t3730.dtb \
omap3-sbc-t3730.dtb \
omap3-devkit8000.dtb \
omap3-beagle-xm.dtb \
omap3-beagle-xm-ab.dtb \
omap3-cm-t3517.dtb \
omap3-cm-t3530.dtb \
omap3-cm-t3730.dtb \
omap3-devkit8000.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
omap3-ldp.dtb \
omap3-lilly-dbb056.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
omap3-overo-alto35.dtb \
omap3-overo-storm-alto35.dtb \
omap3-overo-chestnut43.dtb \
omap3-overo-storm-chestnut43.dtb \
omap3-overo-gallop43.dtb \
omap3-overo-storm-gallop43.dtb \
omap3-overo-palo43.dtb \
omap3-overo-storm-alto35.dtb \
omap3-overo-storm-chestnut43.dtb \
omap3-overo-storm-gallop43.dtb \
omap3-overo-storm-palo43.dtb \
omap3-overo-summit.dtb \
omap3-overo-storm-summit.dtb \
omap3-overo-tobi.dtb \
omap3-overo-storm-tobi.dtb \
omap3-gta04.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
omap3-lilly-dbb056.dtb \
omap3-zoom3.dtb \
omap4-duovero-parlor.dtb \
omap3-overo-summit.dtb \
omap3-overo-tobi.dtb \
omap3-sbc-t3517.dtb \
omap3-sbc-t3530.dtb \
omap3-sbc-t3730.dtb \
omap3-zoom3.dtb
dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-nano.dtb
dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
omap4-panda.dtb \
omap4-panda-a4.dtb \
omap4-panda-es.dtb \
omap4-var-som.dtb \
omap4-sdp.dtb \
omap4-sdp-es23plus.dtb \
omap5-uevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-nano.dtb \
am335x-base0033.dtb \
am3517-craneboard.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
am43x-epos-evm.dtb \
am437x-gp-evm.dtb \
dra7-evm.dtb
omap4-var-dvk-om44.dtb \
omap4-var-stk-om44.dtb
dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
am437x-gp-evm.dtb
dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
omap5-sbc-t54.dtb \
omap5-uevm.dtb
dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
dra72-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
orion5x-lacie-ethernet-disk-mini-v2.dtb \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-rd88f5182-nas.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-apq8074-dragonboard.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-ifc6410.dtb \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-mtp.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
@ -318,11 +337,13 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_vt.dtb
dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
spear1340-evb.dtb
@ -331,24 +352,33 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2020.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
stih416-b2000.dtb \
stih416-b2020.dtb \
stih416-b2020-revE.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
sun4i-a10-pcduino.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-olinuxino-micro.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-m9.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-olinuxino-micro.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
@ -363,7 +393,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \

41
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -182,31 +182,31 @@
&usb {
status = "okay";
};
control@44e10620 {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
&usb1_phy {
status = "okay";
};
usb@47401000 {
status = "okay";
};
&usb0 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
dma-controller@47402000 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&i2c0 {
@ -280,13 +280,14 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&mmc1 {

96
arch/arm/boot/dts/am335x-evm.dts
View File

@ -268,34 +268,34 @@
lcd_pins_s0: lcd_pins_s0 {
pinctrl-single,pins = <
0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
@ -330,31 +330,31 @@
&usb {
status = "okay";
};
control@44e10620 {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
&usb1_phy {
status = "okay";
};
usb@47401000 {
status = "okay";
};
&usb0 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
dma-controller@47402000 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&i2c1 {
@ -614,12 +614,14 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {

51
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -57,6 +57,17 @@
enable-active-high;
};
vtt_fixed: fixedregulator@3 {
compatible = "regulator-fixed";
regulator-name = "vtt";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
@ -363,31 +374,31 @@
&usb {
status = "okay";
};
control@44e10620 {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
&usb1_phy {
status = "okay";
};
usb@47401000 {
status = "okay";
};
&usb0 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
dma-controller@47402000 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&epwmss2 {
@ -484,12 +495,14 @@
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {

46
arch/arm/boot/dts/am335x-igep0033.dtsi
View File

@ -95,6 +95,14 @@
};
};
&mac {
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
@ -200,31 +208,31 @@
&usb {
status = "okay";
};
control@44e10620 {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
&usb1_phy {
status = "okay";
};
usb@47401000 {
status = "okay";
};
&usb0 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
dma-controller@47402000 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"

5
arch/arm/boot/dts/am335x-nano.dts
View File

@ -344,6 +344,11 @@
&mac {
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&cpsw_emac0 {

30
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -96,47 +96,29 @@
clock-div = <1>;
};
ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm0_gate_tbclk>;
};
ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm1_gate_tbclk>;
};
ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm2_gate_tbclk>;
};
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {

2
arch/arm/boot/dts/am33xx.dtsi
View File

@ -688,6 +688,7 @@
*/
interrupts = <40 41 42 43>;
ranges;
status = "disabled";
davinci_mdio: mdio@4a101000 {
compatible = "ti,davinci_mdio";
@ -696,6 +697,7 @@
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a101000 0x100>;
status = "disabled";
};
cpsw_emac0: slave@4a100200 {

121
arch/arm/boot/dts/am4372.dtsi
View File

@ -525,6 +525,12 @@
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@44e10650 {
compatible = "ti,am43xx-cpsw-phy-sel";
reg= <0x44e10650 0x4>;
reg-names = "gmii-sel";
};
};
epwmss0: epwmss@48300000 {
@ -739,6 +745,121 @@
#size-cells = <1>;
status = "disabled";
};
am43xx_control_usb2phy1: control-phy@44e10620 {
compatible = "ti,control-phy-usb2-am437";
reg = <0x44e10620 0x4>;
reg-names = "power";
};
am43xx_control_usb2phy2: control-phy@0x44e10628 {
compatible = "ti,control-phy-usb2-am437";
reg = <0x44e10628 0x4>;
reg-names = "power";
};
ocp2scp0: ocp2scp@483a8000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp0";
usb2_phy1: phy@483a8000 {
compatible = "ti,am437x-usb2";
reg = <0x483a8000 0x8000>;
ctrl-module = <&am43xx_control_usb2phy1>;
clocks = <&usb_phy0_always_on_clk32k>,
<&usb_otg_ss0_refclk960m>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
ocp2scp1: ocp2scp@483e8000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp1";
usb2_phy2: phy@483e8000 {
compatible = "ti,am437x-usb2";
reg = <0x483e8000 0x8000>;
ctrl-module = <&am43xx_control_usb2phy2>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
dwc3_1: omap_dwc3@48380000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss0";
reg = <0x48380000 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x17000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
};
};
dwc3_2: omap_dwc3@483c0000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x483c0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x17000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
};
};
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
interrupts = <0 138 0x4>;
num-cs = <4>;
status = "disabled";
};
hdq: hdq@48347000 {
compatible = "ti,am43xx-hdq";
reg = <0x48347000 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&func_12m_clk>;
clock-names = "fck";
ti,hwmods = "hdq1w";
status = "disabled";
};
};
};

229
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -27,6 +27,17 @@
enable-active-high;
};
vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@ -81,6 +92,85 @@
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&i2c0 {
@ -93,6 +183,20 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
pixcir_ts@5c {
compatible = "pixcir,pixcir_tangoc";
pinctrl-names = "default";
pinctrl-0 = <&pixcir_ts_pins>;
reg = <0x5c>;
interrupt-parent = <&gpio3>;
interrupts = <22 0>;
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
x-size = <1024>;
y-size = <600>;
};
};
&epwmss0 {
@ -130,3 +234,128 @@
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
&usb2_phy1 {
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};
&usb2_phy2 {
status = "okay";
};
&usb2 {
dr_mode = "host";
status = "okay";
};
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,wait-pin = <0>;
gpmc,wait-on-read;
gpmc,wait-on-write;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000c0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002c0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x1f600000>;
};
};
};

105
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -138,6 +138,29 @@
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
qspi1_default: qspi1_default {
pinctrl-single,pins = <
0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
>;
};
pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
>;
};
hdq_pins: pinmux_hdq_pins {
pinctrl-single,pins = <
0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
>;
};
};
matrix_keypad: matrix_keypad@0 {
@ -226,7 +249,9 @@
};
pixcir_ts@5c {
compatible = "pixcir,pixcir_ts";
compatible = "pixcir,pixcir_tangoc";
pinctrl-names = "default";
pinctrl-0 = <&pixcir_ts_pins>;
reg = <0x5c>;
interrupt-parent = <&gpio1>;
interrupts = <17 0>;
@ -234,7 +259,7 @@
attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
x-size = <1024>;
y-size = <768>;
y-size = <600>;
};
};
@ -367,3 +392,79 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
};
&usb2_phy1 {
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};
&usb2_phy2 {
status = "okay";
};
&usb2 {
dr_mode = "host";
status = "okay";
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_default>;
spi-max-frequency = <48000000>;
m25p80@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
spi-cpha;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first 512KiB
* for a valid file to boot(XIP).
*/
partition@0 {
label = "QSPI.U_BOOT";
reg = <0x00000000 0x000080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
reg = <0x00080000 0x00080000>;
};
partition@2 {
label = "QSPI.U-BOOT-SPL_OS";
reg = <0x00100000 0x00010000>;
};
partition@3 {
label = "QSPI.U_BOOT_ENV";
reg = <0x00110000 0x00010000>;
};
partition@4 {
label = "QSPI.U-BOOT-ENV.backup";
reg = <0x00120000 0x00010000>;
};
partition@5 {
label = "QSPI.KERNEL";
reg = <0x00130000 0x0800000>;
};
partition@6 {
label = "QSPI.FILESYSTEM";
reg = <0x00930000 0x36D0000>;
};
};
};
&hdq {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&hdq_pins>;
};

107
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -9,6 +9,22 @@
*/
&scrm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
crystal_freq_sel_ck: crystal_freq_sel_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@ -87,6 +103,54 @@
clock-mult = <1>;
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
ehrpwm3_tbclk: ehrpwm3_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
ehrpwm4_tbclk: ehrpwm4_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
ehrpwm5_tbclk: ehrpwm5_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {
@ -229,6 +293,7 @@
reg = <0x2e30>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
ti,set-rate-parent;
};
dpll_per_ck: dpll_per_ck {
@ -511,6 +576,7 @@
compatible = "ti,mux-clock";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x4244>;
ti,set-rate-parent;
};
dpll_extdev_ck: dpll_extdev_ck {
@ -609,10 +675,13 @@
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_per_ck>;
clock-mult = <1>;
clock-div = <1>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x2e14>;
ti,invert-autoidle-bit;
};
dll_aging_clk_div: dll_aging_clk_div {
@ -653,4 +722,36 @@
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4260>;
};
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a40>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a48>;
};
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a60>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a68>;
};
};

1
arch/arm/boot/dts/armada-370-db.dts
View File

@ -35,7 +35,6 @@
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@a0000 {

1
arch/arm/boot/dts/armada-370-mirabox.dts
View File

@ -47,7 +47,6 @@
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
timer@20300 {

1
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View File

@ -50,7 +50,6 @@
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};

1
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View File

@ -50,7 +50,6 @@
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};

1
arch/arm/boot/dts/armada-370-rd.dts
View File

@ -51,7 +51,6 @@
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@a0000 {

7
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -157,6 +157,7 @@
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12100 {
@ -165,6 +166,7 @@
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -203,6 +205,11 @@
reg = <0x20300 0x34>, <0x20704 0x4>;
};
pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;

5
arch/arm/boot/dts/armada-370.dtsi
View File

@ -220,6 +220,11 @@
clocks = <&coreclk 2>;
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
audio_controller: audio-controller@30000 {
compatible = "marvell,armada370-audio";
reg = <0x30000 0x4000>;

9
arch/arm/boot/dts/armada-375-db.dts
View File

@ -68,7 +68,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
@ -107,6 +106,14 @@
};
};
usb@54000 {
status = "okay";
};
usb3@58000 {
status = "okay";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";

55
arch/arm/boot/dts/armada-375.dtsi
View File

@ -39,6 +39,8 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-375-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
@ -128,6 +130,11 @@
cache-level = <2>;
};
scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
@ -194,6 +201,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -203,6 +211,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -320,6 +329,46 @@
clocks = <&coreclk 0>;
};
watchdog@20300 {
compatible = "marvell,armada-375-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
clocks = <&coreclk 0>;
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
coherency-fabric@21010 {
compatible = "marvell,armada-375-coherency-fabric";
reg = <0x21010 0x1c>;
};
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
status = "disabled";
};
usb@54000 {
compatible = "marvell,orion-ehci";
reg = <0x54000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 26>;
status = "disabled";
};
usb3@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 16>;
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
@ -391,6 +440,12 @@
status = "disabled";
};
thermal@e8078 {
compatible = "marvell,armada375-thermal";
reg = <0xe8078 0x4>, <0xe807c 0x8>;
status = "okay";
};
coreclk: mvebu-sar@e8204 {
compatible = "marvell,armada-375-core-clock";
reg = <0xe8204 0x04>;

2
arch/arm/boot/dts/armada-380.dtsi
View File

@ -21,6 +21,8 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-380-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";

29
arch/arm/boot/dts/armada-385-db.dts
View File

@ -55,7 +55,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
@ -65,6 +64,10 @@
phy-mode = "rgmii-id";
};
usb@50000 {
status = "ok";
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
@ -81,6 +84,14 @@
};
};
sata@a8000 {
status = "okay";
};
sata@e0000 {
status = "okay";
};
flash@d0000 {
status = "okay";
num-cs = <1>;
@ -101,6 +112,22 @@
reg = <0x1000000 0x3f000000>;
};
};
sdhci@d8000 {
clock-frequency = <200000000>;
broken-cd;
wp-inverted;
bus-width = <8>;
status = "okay";
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
};
};
pcie-controller {

5
arch/arm/boot/dts/armada-385-rd.dts
View File

@ -51,7 +51,6 @@
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
@ -77,6 +76,10 @@
reg = <1>;
};
};
usb3@f0000 {
status = "okay";
};
};
pcie-controller {

2
arch/arm/boot/dts/armada-385.dtsi
View File

@ -21,6 +21,8 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-380-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";

84
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -108,6 +108,11 @@
cache-level = <2>;
};
scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
@ -174,6 +179,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -183,6 +189,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -267,6 +274,28 @@
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
@ -283,6 +312,14 @@
status = "disabled";
};
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
@ -339,6 +376,22 @@
clocks = <&gateclk 4>;
};
sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 15>;
status = "disabled";
};
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>;
status = "disabled";
};
coredivclk: clock@e4250 {
compatible = "marvell,armada-380-corediv-clock";
reg = <0xe4250 0xc>;
@ -347,6 +400,12 @@
clock-output-names = "nand";
};
thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>;
status = "okay";
};
flash@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
@ -356,6 +415,31 @@
clocks = <&coredivclk 0>;
status = "disabled";
};
sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg = <0xd8000 0x1000>, <0xdc000 0x100>;
interrupts = <0 25 0x4>;
clocks = <&gateclk 17>;
mrvl,clk-delay-cycles = <0x1F>;
status = "disabled";
};
usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 9>;
status = "disabled";
};
usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 10>;
status = "disabled";
};
};
};

2
arch/arm/boot/dts/armada-xp-axpwifiap.dts
View File

@ -95,12 +95,10 @@
};
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};

4
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -106,19 +106,15 @@
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};

4
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -104,19 +104,15 @@
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};

4
arch/arm/boot/dts/armada-xp-matrix.dts
View File

@ -37,19 +37,15 @@
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};

1
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -27,6 +27,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-xp-smp";
cpu@0 {
device_type = "cpu";

1
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -29,6 +29,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-xp-smp";
cpu@0 {
device_type = "cpu";

1
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -30,6 +30,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-xp-smp";
cpu@0 {
device_type = "cpu";

1
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View File

@ -138,7 +138,6 @@
};
serial@12000 {
clocks = <&coreclk 0>;
status = "okay";
};

2
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View File

@ -72,11 +72,9 @@
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {

8
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -58,6 +58,7 @@
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12300 {
@ -66,6 +67,7 @@
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
@ -117,9 +119,9 @@
clock-names = "nbclk", "fixed";
};
armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu";
reg = <0x22100 0x400>, <0x20800 0x20>;
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x20>;
};
eth2: ethernet@30000 {

62
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -51,11 +51,54 @@
};
i2c0: i2c@f0014000 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";
};
i2c1: i2c@f0018000 {
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "okay";
regulators {
vcc_1v8_reg: DCDC_REG1 {
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_1v2_reg: DCDC_REG2 {
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_3v3_reg: DCDC_REG3 {
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vddfuse_reg: LDO_REG1 {
regulator-name = "FUSE_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vddana_reg: LDO_REG2 {
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
macb0: ethernet@f0028000 {
@ -63,6 +106,12 @@
status = "okay";
};
pwm0: pwm@f002c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>;
status = "okay";
};
usart0: serial@f001c000 {
status = "okay";
};
@ -110,6 +159,7 @@
i2c2: i2c@f801c000 {
dmas = <0>, <0>; /* Do not use DMA for i2c2 */
pinctrl-0 = <&pinctrl_i2c2_pu>;
status = "okay";
};
@ -124,6 +174,18 @@
pinctrl@fffff200 {
board {
pinctrl_i2c0_pu: i2c0_pu {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_i2c2_pu: i2c2_pu {
atmel,pins =
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;

114
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -29,6 +29,7 @@
i2c0 = &i2c0;
ssc0 = &ssc0;
ssc1 = &ssc1;
ssc2 = &ssc2;
};
cpus {
@ -194,6 +195,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clock-names = "pclk";
status = "disabled";
};
@ -203,6 +206,19 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
clocks = <&ssc1_clk>;
clock-names = "pclk";
status = "disabled";
};
ssc2: ssc@fffc4000 {
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffc4000 0x4000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
clocks = <&ssc2_clk>;
clock-names = "pclk";
status = "disabled";
};
@ -397,6 +413,22 @@
};
};
ssc2 {
pinctrl_ssc2_tx: ssc2_tx-0 {
atmel,pins =
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_ssc2_rx: ssc2_rx-0 {
atmel,pins =
<AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
@ -564,7 +596,8 @@
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
<190000000 240000000 2 1>;
};
pllb: pllbck {
@ -573,9 +606,9 @@
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
atmel,clk-input-range = <1000000 32000000>;
atmel,clk-input-range = <1000000 5000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
};
mck: masterck {
@ -584,16 +617,48 @@
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 3>;
atmel,clk-divisors = <1 2 4 0>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
atmel,clk-divisors = <1 2 4 3>;
atmel,clk-divisors = <1 2 4 0>;
clocks = <&pllb>;
};
prog: progck {
compatible = "atmel,at91rm9200-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
prog2: prog2 {
#clock-cells = <0>;
reg = <2>;
interrupts = <AT91_PMC_PCKRDY(2)>;
};
prog3: prog3 {
#clock-cells = <0>;
reg = <3>;
interrupts = <AT91_PMC_PCKRDY(3)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
@ -611,6 +676,30 @@
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
pck2: pck2 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
pck3: pck3 {
#clock-cells = <0>;
reg = <11>;
clocks = <&prog3>;
};
hclk0: hclk0 {
#clock-cells = <0>;
reg = <16>;
@ -685,6 +774,21 @@
reg = <13>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <14>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <15>;
};
ssc2_clk: ssc2_clk {
#clock-cells = <0>;
reg = <16>;
};
tc0_clk: tc0_clk {
#clock-cells = <0>;
reg = <17>;

33
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -136,6 +136,36 @@
>;
/* shared pinctrl settings */
adc0 {
pinctrl_adc0_adtrg: adc0_adtrg {
atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad0: adc0_ad0 {
atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad1: adc0_ad1 {
atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad2: adc0_ad2 {
atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad3: adc0_ad3 {
atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad4: adc0_ad4 {
atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad5: adc0_ad5 {
atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad6: adc0_ad6 {
atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad7: adc0_ad7 {
atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
@ -634,10 +664,9 @@
adc0: adc@fffb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc";
compatible = "atmel,at91sam9g45-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>;
atmel,adc-startup-time = <40>;

20
arch/arm/boot/dts/at91sam9m10g45ek.dts
View File

@ -8,6 +8,7 @@
*/
/dts-v1/;
#include "at91sam9g45.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Atmel AT91SAM9M10G45-EK";
@ -130,6 +131,21 @@
status = "okay";
};
adc0: adc@fffb0000 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
&pinctrl_adc0_ad5
&pinctrl_adc0_ad6
&pinctrl_adc0_ad7>;
atmel,adc-ts-wires = <4>;
status = "okay";
};
pwm0: pwm@fffb8000 {
status = "okay";
@ -216,14 +232,14 @@
d6 {
label = "d6";
pwms = <&pwm0 3 5000 0>;
pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "nand-disk";
};
d7 {
label = "d7";
pwms = <&pwm0 1 5000 0>;
pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "mmc0";
};

348
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
model = "Atmel AT91SAM9N12 SoC";
@ -49,6 +50,18 @@
reg = <0x20000000 0x10000000>;
};
slow_xtal: slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
main_xtal: main_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -75,8 +88,280 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
compatible = "atmel,at91sam9n12-pmc";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
clock-frequency = <12000000>;
clock-accuracy = <50000000>;
};
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
clocks = <&main_rc_osc>, <&main_osc>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
<695000000 750000000 1 0>,
<645000000 700000000 2 0>,
<595000000 650000000 3 0>,
<545000000 600000000 0 1>,
<495000000 555000000 1 1>,
<445000000 500000000 1 2>,
<400000000 450000000 1 3>;
};
plladiv: plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0>;
clocks = <&plla>;
};
pllb: pllbck {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <3>;
atmel,pll-clk-output-ranges = <30000000 100000000 0>;
};
mck: masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
atmel,master-clk-have-div3-pres;
};
usb: usbck {
compatible = "atmel,at91sam9n12-clk-usb";
#clock-cells = <0>;
clocks = <&pllb>;
};
prog: progck {
compatible = "atmel,at91sam9x5-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck: ddrck {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
lcdck: lcdck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
};
periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioAB_clk: pioAB_clk {
#clock-cells = <0>;
reg = <2>;
};
pioCD_clk: pioCD_clk {
#clock-cells = <0>;
reg = <3>;
};
fuse_clk: fuse_clk {
#clock-cells = <0>;
reg = <4>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <5>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <6>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <7>;
};
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <8>;
};
twi0_clk: twi0_clk {
reg = <9>;
#clock-cells = <0>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <10>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <12>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <13>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <14>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <15>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <16>;
};
tcb_clk: tcb_clk {
#clock-cells = <0>;
reg = <17>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <18>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <19>;
};
dma0_clk: dma0_clk {
#clock-cells = <0>;
reg = <20>;
};
uhphs_clk: uhphs_clk {
#clock-cells = <0>;
reg = <22>;
};
udphs_clk: udphs_clk {
#clock-cells = <0>;
reg = <23>;
};
lcdc_clk: lcdc_clk {
#clock-cells = <0>;
reg = <25>;
};
sha_clk: sha_clk {
#clock-cells = <0>;
reg = <27>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <28>;
};
aes_clk: aes_clk {
#clock-cells = <0>;
reg = <29>;
};
trng_clk: trng_clk {
#clock-cells = <0>;
reg = <30>;
};
};
};
rstc@fffffe00 {
@ -88,6 +373,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
};
shdwc@fffffe10 {
@ -95,12 +381,38 @@
reg = <0xfffffe10 0x10>;
};
sckc@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
slow_osc: slow_osc {
compatible = "atmel,at91sam9x5-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>, <&slow_osc>;
};
};
mmc0: mmc@f0008000 {
compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
clocks = <&mci0_clk>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -110,12 +422,16 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>;
clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>;
clock-names = "t0_clk";
};
dma: dma-controller@ffffec00 {
@ -123,6 +439,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma0_clk>;
clock-names = "dma_clk";
};
pinctrl@fffff400 {
@ -392,6 +710,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
@ -402,6 +721,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioC: gpio@fffff800 {
@ -412,6 +732,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioD: gpio@fffffa00 {
@ -422,6 +743,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
};
@ -431,6 +753,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clock-names = "usart";
status = "disabled";
};
@ -443,6 +767,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clock-names = "pclk";
status = "disabled";
};
@ -452,6 +778,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clock-names = "usart";
status = "disabled";
};
@ -461,6 +789,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clock-names = "usart";
status = "disabled";
};
@ -470,6 +800,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clock-names = "usart";
status = "disabled";
};
@ -479,6 +811,8 @@
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
clocks = <&usart3_clk>;
clock-names = "usart";
status = "disabled";
};
@ -493,6 +827,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&twi0_clk>;
status = "disabled";
};
@ -507,6 +842,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&twi1_clk>;
status = "disabled";
};
@ -521,6 +857,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clock-names = "spi_clk";
status = "disabled";
};
@ -535,6 +873,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clock-names = "spi_clk";
status = "disabled";
};
@ -554,6 +894,7 @@
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
status = "disabled";
};
};
@ -584,6 +925,9 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
<&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};

8
arch/arm/boot/dts/at91sam9n12ek.dts
View File

@ -21,6 +21,14 @@
reg = <0x20000000 0x8000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <16000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;

272
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -11,6 +11,7 @@
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Atmel AT91SAM9RL family SoC";
@ -32,6 +33,7 @@
i2c1 = &i2c1;
ssc0 = &ssc0;
ssc1 = &ssc1;
pwm0 = &pwm0;
};
cpus {
@ -60,12 +62,31 @@
clock-frequency = <0>;
};
clocks {
adc_op_clk: adc_op_clk{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
fb0: fb@00500000 {
compatible = "atmel,at91sam9rl-lcdc";
reg = <0x00500000 0x1000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
clocks = <&lcd_clk>, <&lcd_clk>;
clock-names = "hclk", "lcdc_clk";
status = "disabled";
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
@ -199,6 +220,16 @@
status = "disabled";
};
pwm0: pwm@fffc8000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xfffc8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
clock-names = "pwm_clk";
status = "disabled";
};
spi0: spi@fffcc000 {
#address-cells = <1>;
#size-cells = <0>;
@ -212,6 +243,111 @@
status = "disabled";
};
adc0: adc@fffd0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-adc";
reg = <0xfffd0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0x3f>;
atmel,adc-vref = <3300>;
atmel,adc-startup-time = <40>;
atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";
trigger@0 {
reg = <0>;
trigger-name = "timer-counter-0";
trigger-value = <0x1>;
};
trigger@1 {
reg = <1>;
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
};
trigger@2 {
reg = <2>;
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
};
trigger@3 {
reg = <3>;
trigger-name = "external";
trigger-value = <0x13>;
trigger-external;
};
};
usb0: gadget@fffd4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udphs_clk>, <&utmi>;
clock-names = "pclk", "hclk";
status = "disabled";
ep0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
ep6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
};
ramc0: ramc@ffffea00 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffea00 0x200>;
@ -250,6 +386,44 @@
<0x003fffff 0x0001ff3c>; /* pioD */
/* shared pinctrl settings */
adc0 {
pinctrl_adc0_ts: adc0_ts-0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad0: adc0_ad0-0 {
atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad1: adc0_ad1-0 {
atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad2: adc0_ad2-0 {
atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad3: adc0_ad3-0 {
atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad4: adc0_ad4-0 {
atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad5: adc0_ad5-0 {
atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adc0_adtrg: adc0_adtrg-0 {
atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
@ -258,6 +432,33 @@
};
};
fb {
pinctrl_fb: fb-0 {
atmel,pins =
<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
i2c_gpio0 {
pinctrl_i2c_gpio0: i2c_gpio0-0 {
atmel,pins =
@ -319,6 +520,61 @@
};
};
pwm0 {
pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
@ -351,15 +607,6 @@
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
tcb0 {
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
@ -574,8 +821,9 @@
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
#atmel,pll-clk-output-range-cells = <3>;
atmel,pll-clk-output-ranges = <80000000 200000000 0>,
<190000000 240000000 2>;
};
utmi: utmick {
@ -592,7 +840,7 @@
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 3>;
atmel,clk-divisors = <1 2 4 0>;
};
prog: progck {

90
arch/arm/boot/dts/at91sam9rlek.dts
View File

@ -41,6 +41,37 @@
};
ahb {
fb0: fb@00500000 {
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;
atmel,lcdcon2 = <0x80008002>;
atmel,guard-time = <1>;
atmel,lcd-wiring-mode = "RGB";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <4965000>;
hactive = <240>;
vactive = <320>;
hback-porch = <1>;
hfront-porch = <33>;
vback-porch = <1>;
vfront-porch = <0>;
hsync-len = <5>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
@ -101,6 +132,43 @@
status = "okay";
};
adc0: adc@fffd0000 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
&pinctrl_adc0_ad5
&pinctrl_adc0_adtrg>;
atmel,adc-ts-wires = <4>;
status = "okay";
};
usb0: gadget@fffd4000 {
atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>;
status = "okay";
};
spi0: spi@fffcc000 {
status = "okay";
cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;
};
};
pwm0: pwm@fffc8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm1_2>,
<&pinctrl_pwm0_pwm2_2>;
};
dbgu: serial@fffff200 {
status = "okay";
};
@ -126,18 +194,24 @@
};
};
leds {
compatible = "gpio-leds";
pwmleds {
compatible = "pwm-leds";
ds1 {
label = "ds1";
gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
};
ds2 {
label = "ds2";
gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
};
};
leds {
compatible = "gpio-leds";
ds3 {
label = "ds3";
@ -163,4 +237,12 @@
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
};
i2c@1 {
status = "okay";
};
};

355
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/ {
model = "Atmel AT91SAM9x5 family SoC";
@ -51,6 +52,24 @@
reg = <0x20000000 0x10000000>;
};
slow_xtal: slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
main_xtal: main_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
adc_op_clk: adc_op_clk{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <5000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -77,8 +96,272 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
compatible = "atmel,at91sam9x5-pmc";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
clock-frequency = <12000000>;
clock-accuracy = <50000000>;
};
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
clocks = <&main_rc_osc>, <&main_osc>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <745000000 800000000 0 0
695000000 750000000 1 0
645000000 700000000 2 0
595000000 650000000 3 0
545000000 600000000 0 1
495000000 555000000 1 1
445000000 500000000 1 2
400000000 450000000 1 3>;
};
plladiv: plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0>;
clocks = <&plla>;
};
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKU>;
clocks = <&main>;
};
mck: masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
atmel,master-clk-have-div3-pres;
};
usb: usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
prog: progck {
compatible = "atmel,at91sam9x5-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
};
smd: smdclk {
compatible = "atmel,at91sam9x5-clk-smd";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck: ddrck {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
smdck: smdck {
#clock-cells = <0>;
reg = <4>;
clocks = <&smd>;
};
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
};
periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioAB_clk: pioAB_clk {
#clock-cells = <0>;
reg = <2>;
};
pioCD_clk: pioCD_clk {
#clock-cells = <0>;
reg = <3>;
};
smd_clk: smd_clk {
#clock-cells = <0>;
reg = <4>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <5>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <6>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <7>;
};
twi0_clk: twi0_clk {
reg = <9>;
#clock-cells = <0>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <10>;
};
twi2_clk: twi2_clk {
#clock-cells = <0>;
reg = <11>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <12>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <13>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <14>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <15>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <16>;
};
tcb0_clk: tcb0_clk {
#clock-cells = <0>;
reg = <17>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <18>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <19>;
};
dma0_clk: dma0_clk {
#clock-cells = <0>;
reg = <20>;
};
dma1_clk: dma1_clk {
#clock-cells = <0>;
reg = <21>;
};
uhphs_clk: uhphs_clk {
#clock-cells = <0>;
reg = <22>;
};
udphs_clk: udphs_clk {
#clock-cells = <0>;
reg = <23>;
};
mci1_clk: mci1_clk {
#clock-cells = <0>;
reg = <26>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <28>;
};
};
};
rstc@fffffe00 {
@ -95,18 +378,47 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
};
sckc@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
slow_osc: slow_osc {
compatible = "atmel,at91sam9x5-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>, <&slow_osc>;
};
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>;
clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>;
clock-names = "t0_clk";
};
dma0: dma-controller@ffffec00 {
@ -114,6 +426,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma0_clk>;
clock-names = "dma_clk";
};
dma1: dma-controller@ffffee00 {
@ -121,6 +435,8 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma1_clk>;
clock-names = "dma_clk";
};
pinctrl@fffff400 {
@ -453,6 +769,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
@ -464,6 +781,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioC: gpio@fffff800 {
@ -474,6 +792,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioD: gpio@fffffa00 {
@ -485,6 +804,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
};
@ -497,6 +817,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clock-names = "pclk";
status = "disabled";
};
@ -507,6 +829,8 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
clocks = <&mci0_clk>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -519,6 +843,8 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
clocks = <&mci1_clk>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -530,6 +856,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clock-names = "usart";
status = "disabled";
};
@ -539,6 +867,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clock-names = "usart";
status = "disabled";
};
@ -548,6 +878,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clock-names = "usart";
status = "disabled";
};
@ -557,6 +889,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clock-names = "usart";
status = "disabled";
};
@ -571,6 +905,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&twi0_clk>;
status = "disabled";
};
@ -585,6 +920,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&twi1_clk>;
status = "disabled";
};
@ -599,6 +935,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&twi2_clk>;
status = "disabled";
};
@ -608,6 +945,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart0_clk>;
clock-names = "usart";
status = "disabled";
};
@ -617,6 +956,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart1_clk>;
clock-names = "usart";
status = "disabled";
};
@ -626,6 +967,9 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>;
@ -673,6 +1017,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clock-names = "spi_clk";
status = "disabled";
};
@ -687,6 +1033,8 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clock-names = "spi_clk";
status = "disabled";
};
@ -805,6 +1153,9 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
<&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@ -812,6 +1163,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ehci_clk", "uhpck";
status = "disabled";
};
};

31
arch/arm/boot/dts/at91sam9x5_can.dtsi Normal file
View File

@ -0,0 +1,31 @@
/*
* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
* Ethernet interface.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
can0_clk: can0_clk {
#clock-cells = <0>;
reg = <29>;
};
can1_clk: can1_clk {
#clock-cells = <0>;
reg = <30>;
};
};
};
};
};
};

26
arch/arm/boot/dts/at91sam9x5_isi.dtsi Normal file
View File

@ -0,0 +1,26 @@
/*
* at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
* Image Sensor Interface.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
isi_clk: isi_clk {
#clock-cells = <0>;
reg = <25>;
};
};
};
};
};
};

26
arch/arm/boot/dts/at91sam9x5_lcd.dtsi Normal file
View File

@ -0,0 +1,26 @@
/*
* at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
* LCD controller.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk {
#clock-cells = <0>;
reg = <25>;
};
};
};
};
};
};

11
arch/arm/boot/dts/at91sam9x5_macb0.dtsi
View File

@ -43,12 +43,23 @@
};
};
pmc: pmc@fffffc00 {
periphck {
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <24>;
};
};
};
macb0: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
};
};

11
arch/arm/boot/dts/at91sam9x5_macb1.dtsi
View File

@ -31,12 +31,23 @@
};
};
pmc: pmc@fffffc00 {
periphck {
macb1_clk: macb1_clk {
#clock-cells = <0>;
reg = <27>;
};
};
};
macb1: ethernet@f8030000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
clocks = <&macb1_clk>, <&macb1_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
};
};

11
arch/arm/boot/dts/at91sam9x5_usart3.dtsi
View File

@ -42,12 +42,23 @@
};
};
pmc: pmc@fffffc00 {
periphck {
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <8>;
};
};
};
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
clocks = <&usart3_clk>;
clock-names = "usart";
status = "disabled";
};
};

8
arch/arm/boot/dts/at91sam9x5cm.dtsi
View File

@ -23,6 +23,14 @@
};
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
ahb {
apb {
pinctrl@fffff400 {

31
arch/arm/boot/dts/atlas6.dtsi
View File

@ -39,6 +39,11 @@
};
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <29>;
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
@ -167,6 +172,7 @@
compatible = "sirf,prima2-dspif";
reg = <0xa8000000 0x10000>;
interrupts = <9>;
resets = <&rstc 1>;
};
gps@a8010000 {
@ -174,6 +180,7 @@
reg = <0xa8010000 0x10000>;
interrupts = <7>;
clocks = <&clks 9>;
resets = <&rstc 2>;
};
dsp@a9000000 {
@ -181,6 +188,7 @@
reg = <0xa9000000 0x1000000>;
interrupts = <8>;
clocks = <&clks 8>;
resets = <&rstc 0>;
};
};
@ -298,9 +306,9 @@
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
sirf,spi-num-chipselects = <1>;
cs-gpios = <&gpio 0 0>;
sirf,spi-dma-rx-channel = <25>;
sirf,spi-dma-tx-channel = <20>;
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 19>;
@ -313,8 +321,9 @@
reg = <0xb0170000 0x10000>;
interrupts = <16>;
sirf,spi-num-chipselects = <1>;
sirf,spi-dma-rx-channel = <12>;
sirf,spi-dma-tx-channel = <13>;
dmas = <&dmac0 12>,
<&dmac0 13>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 20>;
@ -555,6 +564,18 @@
sirf,function = "usp0_uart_nostreamctrl";
};
};
usp0_only_utfs_pins_a: usp0@2 {
usp0 {
sirf,pins = "usp0_only_utfs_grp";
sirf,function = "usp0_only_utfs";
};
};
usp0_only_urfs_pins_a: usp0@3 {
usp0 {
sirf,pins = "usp0_only_urfs_grp";
sirf,function = "usp0_only_urfs";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";

8
arch/arm/boot/dts/bcm11351.dtsi
View File

@ -193,6 +193,14 @@
status = "disabled";
};
pwm: pwm@3e01a000 {
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
reg = <0x3e01a000 0xcc>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
#pwm-cells = <3>;
status = "disabled";
};
clocks {
#address-cells = <1>;
#size-cells = <1>;

4
arch/arm/boot/dts/bcm28155-ap.dts
View File

@ -69,6 +69,10 @@
status = "okay";
};
pwm: pwm@3e01a000 {
status = "okay";
};
usbotg: usb@3f120000 {
vusb_d-supply = <&usbldo_reg>;
vusb_a-supply = <&iosr1_reg>;

21
arch/arm/boot/dts/bcm59056.dtsi
View File

@ -70,5 +70,26 @@
vsr_reg: vsr {
};
gpldo1_reg: gpldo1 {
};
gpldo2_reg: gpldo2 {
};
gpldo3_reg: gpldo3 {
};
gpldo4_reg: gpldo4 {
};
gpldo5_reg: gpldo5 {
};
gpldo6_reg: gpldo6 {
};
vbus_reg: vbus {
};
};
};

191
arch/arm/boot/dts/berlin2.dtsi
View File

@ -12,6 +12,7 @@
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@ -37,24 +38,10 @@
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc {
@ -72,6 +59,11 @@
cache-level = <2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@ -83,7 +75,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clocks = <&chip CLKID_TWD>;
};
apb@e80000 {
@ -94,11 +86,83 @@
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@0400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@0800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@0c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@ -107,7 +171,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@ -116,7 +180,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -125,7 +189,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -134,7 +198,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -143,7 +207,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -152,7 +216,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -161,7 +225,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -176,6 +240,14 @@
};
};
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -184,13 +256,48 @@
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
sm_gpio1: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
};
};
sm_gpio0: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <11>;
};
};
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
clocks = <&refclk>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
@ -200,7 +307,9 @@
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
clocks = <&refclk>;
pinctrl-0 = <&uart1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
@ -210,10 +319,32 @@
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <10>;
clocks = <&smclk>;
clocks = <&refclk>;
pinctrl-0 = <&uart2_pmux>;
pinctrl-names = "default";
status = "disabled";
};
sysctrl: system-controller@d000 {
compatible = "marvell,berlin2-system-ctrl";
reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux {
groups = "GSM4";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM5";
function = "uart1";
};
uart2_pmux: uart2-pmux {
groups = "GSM3";
function = "uart2";
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;

167
arch/arm/boot/dts/berlin2cd.dtsi
View File

@ -12,6 +12,7 @@
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@ -30,24 +31,10 @@
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc {
@ -76,7 +63,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clocks = <&chip CLKID_TWD>;
};
apb@e80000 {
@ -87,11 +74,83 @@
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@0400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@0800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@0c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@ -100,7 +159,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@ -109,7 +168,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -118,7 +177,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -127,7 +186,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -136,7 +195,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -145,7 +204,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -154,7 +213,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@ -169,6 +228,19 @@
};
};
chip: chip-control@ea0000 {
compatible = "marvell,berlin2cd-chip-ctrl";
#clock-cells = <1>;
reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";
uart0_pmux: uart0-pmux {
groups = "G6";
function = "uart0";
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -177,13 +249,45 @@
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
sm_gpio1: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
};
};
sm_gpio0: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <8>;
reg = <0>;
};
};
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
clocks = <&refclk>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
@ -193,10 +297,15 @@
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
clocks = <&refclk>;
status = "disabled";
};
sysctrl: system-controller@d000 {
compatible = "marvell,berlin2cd-system-ctrl";
reg = <0xd000 0x100>;
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;

39
arch/arm/boot/dts/berlin2q-marvell-dmp.dts Normal file
View File

@ -0,0 +1,39 @@
/*
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "berlin2q.dtsi"
/ {
model = "Marvell BG2-Q DMP";
compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};
choosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
};
&sdhci1 {
broken-cd;
sdhci,wp-inverted;
status = "okay";
};
&sdhci2 {
non-removable;
status = "okay";
};
&uart0 {
status = "okay";
};

363
arch/arm/boot/dts/berlin2q.dtsi Normal file
View File

@ -0,0 +1,363 @@
/*
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
model = "Marvell Armada 1500 pro (BG2-Q) SoC";
compatible = "marvell,berlin2q", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <3>;
};
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf7000000 0x1000000>;
interrupt-parent = <&gic>;
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci2: sdhci@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SDIO1XIN>;
status = "disabled";
};
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-level = <2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
clocks = <&chip CLKID_TWD>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@0400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@0800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@0c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
interrupts = <8>;
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3800 {
compatible = "snps,dw-apb-ictl";
reg = <0x3800 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
gpio4: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio5: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
};
chip: chip-control@ea0000 {
compatible = "marvell,berlin2q-chip-ctrl";
#clock-cells = <1>;
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
clocks = <&refclk>;
clock-names = "refclk";
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
uart0: uart@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
interrupt-parent = <&sic>;
interrupts = <8>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart1: uart@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
interrupt-parent = <&sic>;
interrupts = <9>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
sysctrl: pin-controller@d000 {
compatible = "marvell,berlin2q-system-ctrl";
reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux {
groups = "GSM12";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM14";
function = "uart1";
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

228
arch/arm/boot/dts/dra7-evm.dts
View File

@ -7,11 +7,11 @@
*/
/dts-v1/;
#include "dra7.dtsi"
#include "dra74x.dtsi"
/ {
model = "TI DRA7";
compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
model = "TI DRA742";
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
memory {
device_type = "memory";
@ -93,6 +93,64 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins = <
0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
* SW5.9 (GPMC_WPN) = LOW
* SW5.1 (NAND_BOOTn) = HIGH */
pinctrl-single,pins = <
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
};
&i2c1 {
@ -273,3 +331,167 @@
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <48000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@5 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00010000>;
};
partition@6 {
label = "QSPI.u-boot-env";
reg = <0x00150000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
reg = <0x00160000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
reg = <0x00170000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
reg = <0x00970000 0x01690000>;
};
};
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb2_pins>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <5>;
gpmc,we-off-ns = <25>;
gpmc,oe-on-ns = <2>;
gpmc,oe-off-ns = <20>;
gpmc,access-ns = <20>;
gpmc,wr-access-ns = <40>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,wait-pin = <0>;
gpmc,wait-on-read;
gpmc,wait-on-write;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};

249
arch/arm/boot/dts/dra7.dtsi
View File

@ -33,33 +33,6 @@
serial5 = &uart6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1060000
1176000 1160000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@ -789,6 +762,228 @@
dma-names = "tx0", "rx0";
status = "disabled";
};
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>;
reg-names = "qspi_base";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
clocks = <&qspi_gfclk_div>;
clock-names = "fck";
num-cs = <4>;
interrupts = <0 343 0x4>;
status = "disabled";
};
omap_control_sata: control-phy@4a002374 {
compatible = "ti,control-phy-pipe3";
reg = <0x4a002374 0x4>;
reg-names = "power";
clocks = <&sys_clkin1>;
clock-names = "sysclk";
};
/* OCP2SCP3 */
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x4a090000 0x20>;
ti,hwmods = "ocp2scp3";
sata_phy: phy@4A096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_sata>;
clocks = <&sys_clkin1>;
clock-names = "sysclk";
#phy-cells = <0>;
};
};
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
};
omap_control_usb2phy1: control-phy@4a002300 {
compatible = "ti,control-phy-usb2";
reg = <0x4a002300 0x4>;
reg-names = "power";
};
omap_control_usb3phy1: control-phy@4a002370 {
compatible = "ti,control-phy-pipe3";
reg = <0x4a002370 0x4>;
reg-names = "power";
};
omap_control_usb2phy2: control-phy@0x4a002e74 {
compatible = "ti,control-phy-usb2-dra7";
reg = <0x4a002e74 0x4>;
reg-names = "power";
};
/* OCP2SCP1 */
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x4a080000 0x20>;
ti,hwmods = "ocp2scp1";
usb2_phy1: phy@4a084000 {
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x400>;
ctrl-module = <&omap_control_usb2phy1>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
};
usb2_phy2: phy@4a085000 {
compatible = "ti,omap-usb2";
reg = <0x4a085000 0x400>;
ctrl-module = <&omap_control_usb2phy2>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
};
usb3_phy1: phy@4a084400 {
compatible = "ti,omap-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb3phy1>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
"sysclk",
"refclk";
#phy-cells = <0>;
};
};
omap_dwc3_1@48880000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x48880000 0x10000>;
interrupts = <0 77 4>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
usb1: usb@48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
interrupts = <0 76 4>;
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
omap_dwc3_2@488c0000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss2";
reg = <0x488c0000 0x10000>;
interrupts = <0 92 4>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
usb2: usb@488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
interrupts = <0 78 4>;
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
omap_dwc3_3@48900000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss3";
reg = <0x48900000 0x10000>;
/* interrupts = <0 TBD 4>; */
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
status = "disabled";
usb3: usb@48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
/* interrupts = <0 93 4>; */
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
reg = <0x48940000 0x10000>;
/* interrupts = <0 TBD 4>; */
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
status = "disabled";
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
/* interrupts = <0 TBD 4>; */
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
elm: elm@48078000 {
compatible = "ti,am3352-elm";
reg = <0x48078000 0xfc0>; /* device IO registers */
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
status = "disabled";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
};
};
};

24
arch/arm/boot/dts/dra72-evm.dts Normal file
View File

@ -0,0 +1,24 @@
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
/ {
model = "TI DRA722";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1024 MB */
};
};
&uart1 {
status = "okay";
};

25
arch/arm/boot/dts/dra72x.dtsi Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
#include "dra7.dtsi"
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
};
};

41
arch/arm/boot/dts/dra74x.dtsi Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
#include "dra7.dtsi"
/ {
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1060000
1176000 1160000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
};
};

12
arch/arm/boot/dts/dra7xx-clocks.dtsi
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@ -1386,6 +1386,14 @@
ti,dividers = <1>, <8>;
};
l3init_960m_gfclk: l3init_960m_gfclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
dss_32khz_clk: dss_32khz_clk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@ -1533,7 +1541,7 @@
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x13f0>;
};
@ -1541,7 +1549,7 @@
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
clocks = <&l3init_960m_gfclk>;
ti,bit-shift = <8>;
reg = <0x1340>;
};

475
arch/arm/boot/dts/exynos3250-pinctrl.dtsi Normal file
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@ -0,0 +1,475 @@
/*
* Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
* tree nodes are listed in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl_0 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb: gpb {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <0x2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpb-0", "gpb-2", "gpb-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c4_bus: i2c4-bus {
samsung,pins = "gpb-0", "gpb-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpb-4", "gpb-6", "gpb-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c5_bus: i2c5-bus {
samsung,pins = "gpb-2", "gpb-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm2_bus: pcm2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c6_bus: i2c6-bus {
samsung,pins = "gpc1-3", "gpc1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c7_bus: i2c7-bus {
samsung,pins = "gpd0-2", "gpd0-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpd1-0", "gpd1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
mipi0_clk: mipi0-clk {
samsung,pins = "gpd1-0", "gpd1-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c1_bus: i2c1-bus {
samsung,pins = "gpd1-2", "gpd1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_1 {
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
};
gpe2: gpe2 {
gpio-controller;
#gpio-cells = <2>;
};
gpk0: gpk0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk1: gpk1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk2: gpk2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpl0: gpl0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm0: gpm0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm1: gpm1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm2: gpm2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm3: gpm3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm4: gpm4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
<0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
#interrupt-cells = <2>;
};
gpx1: gpx1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
<0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
#interrupt-cells = <2>;
};
gpx2: gpx2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx3: gpx3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpk0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpk0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpk0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_rdqs: sd0-rdqs {
samsung,pins = "gpk0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpk0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpk1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpk1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cd: sd1-cd {
samsung,pins = "gpk1-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpk1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
cam_port_b_clk_active: cam-port-b-clk-active {
samsung,pins = "gpm2-2";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
cam_port_b_clk_idle: cam-port-b-clk-idle {
samsung,pins = "gpm2-2";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_i2c0: fimc-is-i2c0 {
samsung,pins = "gpm4-0", "gpm4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_i2c1: fimc-is-i2c1 {
samsung,pins = "gpm4-2", "gpm4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_uart: fimc-is-uart {
samsung,pins = "gpm3-5", "gpm3-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};

444
arch/arm/boot/dts/exynos3250.dtsi Normal file
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@ -0,0 +1,444 @@
/*
* Samsung's Exynos3250 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos3250.h>
/ {
compatible = "samsung,exynos3250";
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &i2c_4;
i2c5 = &i2c_5;
i2c6 = &i2c_6;
i2c7 = &i2c_7;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
fixed-rate-clocks {
#address-cells = <1>;
#size-cells = <0>;
xusbxti: clock@0 {
compatible = "fixed-clock";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
clock-frequency = <0>;
#clock-cells = <0>;
clock-output-names = "xusbxti";
};
xxti: clock@1 {
compatible = "fixed-clock";
reg = <1>;
clock-frequency = <0>;
#clock-cells = <0>;
clock-output-names = "xxti";
};
xtcxo: clock@2 {
compatible = "fixed-clock";
reg = <2>;
clock-frequency = <0>;
#clock-cells = <0>;
clock-output-names = "xtcxo";
};
};
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
smp-sysram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@3f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x3f000 0x1000>;
};
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
sys_reg: syscon@10010000 {
compatible = "samsung,exynos3-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos3250-pmu", "syscon";
reg = <0x10020000 0x4000>;
};
pd_cam: cam-power-domain@10023C00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
};
pd_mfc: mfc-power-domain@10023C40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
};
pd_g3d: g3d-power-domain@10023C60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
};
pd_lcd0: lcd0-power-domain@10023C80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
};
pd_isp: isp-power-domain@10023CA0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
};
cmu: clock-controller@10030000 {
compatible = "samsung,exynos3250-cmu";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <0 73 0>, <0 74 0>;
status = "disabled";
};
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 225 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 48 0>;
};
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 240 0>;
};
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12510000 0x1000>;
interrupts = <0 142 0>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mshc_1: mshc@12520000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12520000 0x1000>;
interrupts = <0 143 0>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges;
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <0 138 0>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <0 139 0>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
adc: adc@126C0000 {
compatible = "samsung,exynos-adc-v3";
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
interrupts = <0 137 0>;
clock-names = "adc", "sclk_tsadc";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 109 0>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
interrupts = <0 110 0>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <0 113 0>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
status = "disabled";
};
i2c_1: i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <0 114 0>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
status = "disabled";
};
i2c_2: i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <0 115 0>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
status = "disabled";
};
i2c_3: i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <0 116 0>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
status = "disabled";
};
i2c_4: i2c@138A0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
interrupts = <0 117 0>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_bus>;
status = "disabled";
};
i2c_5: i2c@138B0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
interrupts = <0 118 0>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_bus>;
status = "disabled";
};
i2c_6: i2c@138C0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
interrupts = <0 119 0>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c6_bus>;
status = "disabled";
};
i2c_7: i2c@138D0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
interrupts = <0 120 0>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c7_bus>;
status = "disabled";
};
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
interrupts = <0 121 0>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
clock-names = "spi", "spi_busclk0";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
};
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
interrupts = <0 122 0>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
clock-names = "spi", "spi_busclk0";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
};
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
<0 107 0>, <0 108 0>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 18 0>, <0 19 0>;
};
};
};
#include "exynos3250-pinctrl.dtsi"

66
arch/arm/boot/dts/exynos4.dtsi
View File

@ -20,6 +20,7 @@
*/
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include "skeleton.dtsi"
/ {
@ -45,6 +46,23 @@
fimc3 = &fimc_3;
};
clock_audss: clock-controller@03810000 {
compatible = "samsung,exynos4210-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
};
i2s0: i2s@03830000 {
compatible = "samsung,s5pv210-i2s";
reg = <0x03830000 0x100>;
clocks = <&clock_audss EXYNOS_I2S_BUS>;
clock-names = "iis";
dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
dma-names = "tx", "rx", "tx-sec";
samsung,idma-addr = <0x03000000>;
status = "disabled";
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
@ -110,6 +128,11 @@
reg = <0x10010000 0x400>;
};
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos4210-pmu", "syscon";
reg = <0x10020000 0x4000>;
};
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
@ -117,7 +140,7 @@
samsung,power-domain = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock 286>, <&clock 143>;
clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
clock-names = "bus_clk", "pll_clk";
status = "disabled";
#address-cells = <1>;
@ -271,6 +294,27 @@
status = "disabled";
};
exynos_usbphy: exynos-usbphy@125B0000 {
compatible = "samsung,exynos4210-usb2-phy";
reg = <0x125B0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
clock-names = "phy", "ref";
#phy-cells = <1>;
status = "disabled";
};
hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <0 71 0>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
phy-names = "usb2-phy";
status = "disabled";
};
ehci@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
@ -289,6 +333,26 @@
status = "disabled";
};
i2s1: i2s@13960000 {
compatible = "samsung,s5pv210-i2s";
reg = <0x13960000 0x100>;
clocks = <&clock CLK_I2S1>;
clock-names = "iis";
dmas = <&pdma1 12>, <&pdma1 11>;
dma-names = "tx", "rx";
status = "disabled";
};
i2s2: i2s@13970000 {
compatible = "samsung,s5pv210-i2s";
reg = <0x13970000 0x100>;
clocks = <&clock CLK_I2S2>;
clock-names = "iis";
dmas = <&pdma0 14>, <&pdma0 13>;
dma-names = "tx", "rx";
status = "disabled";
};
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;

19
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -16,6 +16,7 @@
/dts-v1/;
#include "exynos4210.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Insignal Origen evaluation board based on Exynos4210";
@ -48,6 +49,14 @@
};
};
watchdog@10060000 {
status = "okay";
};
rtc@10070000 {
status = "okay";
};
tmu@100C0000 {
status = "okay";
};
@ -251,35 +260,35 @@
up {
label = "Up";
gpios = <&gpx2 0 1>;
linux,code = <103>;
linux,code = <KEY_UP>;
gpio-key,wakeup;
};
down {
label = "Down";
gpios = <&gpx2 1 1>;
linux,code = <108>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
};
back {
label = "Back";
gpios = <&gpx1 7 1>;
linux,code = <158>;
linux,code = <KEY_BACK>;
gpio-key,wakeup;
};
home {
label = "Home";
gpios = <&gpx1 6 1>;
linux,code = <102>;
linux,code = <KEY_HOME>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpx1 5 1>;
linux,code = <139>;
linux,code = <KEY_MENU>;
gpio-key,wakeup;
};
};

10
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -88,6 +88,12 @@
};
};
hsotg@12480000 {
vusb_d-supply = <&vusb_reg>;
vusb_a-supply = <&vusbdac_reg>;
status = "okay";
};
sdhci_emmc: sdhci@12510000 {
bus-width = <8>;
non-removable;
@ -97,6 +103,10 @@
status = "okay";
};
exynos-usbphy@125B0000 {
status = "okay";
};
serial@13800000 {
status = "okay";
};

59
arch/arm/boot/dts/exynos4210-universal_c210.dts
View File

@ -68,6 +68,12 @@
enable-active-high;
};
hsotg@12480000 {
vusb_d-supply = <&ldo3_reg>;
vusb_a-supply = <&ldo8_reg>;
status = "okay";
};
sdhci_emmc: sdhci@12510000 {
bus-width = <8>;
non-removable;
@ -77,6 +83,34 @@
status = "okay";
};
sdhci_sd: sdhci@12530000 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
pinctrl-names = "default";
vmmc-supply = <&ldo5_reg>;
cd-gpios = <&gpx3 4 0>;
cd-inverted;
status = "okay";
};
ehci@12580000 {
status = "okay";
port@0 {
status = "okay";
};
};
ohci@12590000 {
status = "okay";
port@0 {
status = "okay";
};
};
exynos-usbphy@125B0000 {
status = "okay";
};
serial@13800000 {
status = "okay";
};
@ -216,6 +250,7 @@
regulator-name = "VUSB+MIPI_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
@ -246,6 +281,7 @@
regulator-name = "VUSB+VDAC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo9_reg: LDO9 {
@ -428,6 +464,29 @@
compatible = "samsung,s5p6440-pwm";
status = "okay";
};
camera {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <>;
fimc_0: fimc@11800000 {
status = "okay";
};
fimc_1: fimc@11810000 {
status = "okay";
};
fimc_2: fimc@11820000 {
status = "okay";
};
fimc_3: fimc@11830000 {
status = "okay";
};
};
};
&mdma1 {

21
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -14,6 +14,7 @@
/dts-v1/;
#include "exynos4412.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Insignal Origen evaluation board based on Exynos4412";
@ -48,6 +49,14 @@
};
};
watchdog@10060000 {
status = "okay";
};
rtc@10070000 {
status = "okay";
};
pinctrl@11000000 {
keypad_rows: keypad-rows {
samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
@ -76,37 +85,37 @@
key_home {
keypad,row = <0>;
keypad,column = <0>;
linux,code = <102>;
linux,code = <KEY_HOME>;
};
key_down {
keypad,row = <0>;
keypad,column = <1>;
linux,code = <108>;
linux,code = <KEY_DOWN>;
};
key_up {
keypad,row = <1>;
keypad,column = <0>;
linux,code = <103>;
linux,code = <KEY_UP>;
};
key_menu {
keypad,row = <1>;
keypad,column = <1>;
linux,code = <139>;
linux,code = <KEY_MENU>;
};
key_back {
keypad,row = <2>;
keypad,column = <0>;
linux,code = <158>;
linux,code = <KEY_BACK>;
};
key_enter {
keypad,row = <2>;
keypad,column = <1>;
linux,code = <28>;
linux,code = <KEY_ENTER>;
};
};

54
arch/arm/boot/dts/exynos4412-trats2.dts
View File

@ -21,6 +21,7 @@
aliases {
i2c9 = &i2c_ak8975;
i2c10 = &i2c_cm36651;
};
memory {
@ -98,38 +99,49 @@
enable-active-high;
regulator-always-on;
};
ps_als_reg: voltage-regulator-5 {
compatible = "regulator-fixed";
regulator-name = "LED_A_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpj0 5 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
key-down {
interrupt-parent = <&gpj1>;
interrupts = <2 0>;
gpios = <&gpj1 2 1>;
gpios = <&gpx3 3 1>;
linux,code = <114>;
label = "volume down";
debounce-interval = <10>;
};
key-up {
interrupt-parent = <&gpj1>;
interrupts = <1 0>;
gpios = <&gpj1 1 1>;
gpios = <&gpx2 2 1>;
linux,code = <115>;
label = "volume up";
debounce-interval = <10>;
};
key-power {
interrupt-parent = <&gpx2>;
interrupts = <7 0>;
gpios = <&gpx2 7 1>;
linux,code = <116>;
label = "power";
debounce-interval = <10>;
gpio-key,wakeup;
};
key-ok {
gpios = <&gpx0 1 1>;
linux,code = <139>;
label = "ok";
debounce-inteval = <10>;
gpio-key,wakeup;
};
};
adc: adc@126C0000 {
@ -558,6 +570,22 @@
};
};
i2c_cm36651: i2c-gpio-2 {
compatible = "i2c-gpio";
gpios = <&gpf0 0 1>, <&gpf0 1 1>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
cm36651@18 {
compatible = "capella,cm36651";
reg = <0x18>;
interrupt-parent = <&gpx0>;
interrupts = <2 2>;
vled-supply = <&ps_als_reg>;
};
};
spi_1: spi@13930000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
@ -732,6 +760,16 @@
};
};
exynos-usbphy@125B0000 {
status = "okay";
};
hsotg@12480000 {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;
status = "okay";
};
thermistor-ap@0 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>; /* VCC_1.8V_AP */

4
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -29,4 +29,8 @@
gic: interrupt-controller@10490000 {
cpu-offset = <0x4000>;
};
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos4412-pmu", "syscon";
};
};

9
arch/arm/boot/dts/exynos4x12.dtsi
View File

@ -137,6 +137,10 @@
interrupts = <0 72 0>;
};
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos4212-pmu", "syscon";
};
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
@ -261,4 +265,9 @@
clock-names = "biu", "ciu";
status = "disabled";
};
exynos-usbphy@125B0000 {
compatible = "samsung,exynos4x12-usb2-phy";
samsung,sysreg-phandle = <&sys_reg>;
};
};

13
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -12,6 +12,7 @@
/dts-v1/;
#include "exynos5250.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
@ -445,42 +446,42 @@
menu {
label = "SW-TACT2";
gpios = <&gpx1 4 1>;
linux,code = <139>;
linux,code = <KEY_MENU>;
gpio-key,wakeup;
};
home {
label = "SW-TACT3";
gpios = <&gpx1 5 1>;
linux,code = <102>;
linux,code = <KEY_HOME>;
gpio-key,wakeup;
};
up {
label = "SW-TACT4";
gpios = <&gpx1 6 1>;
linux,code = <103>;
linux,code = <KEY_UP>;
gpio-key,wakeup;
};
down {
label = "SW-TACT5";
gpios = <&gpx1 7 1>;
linux,code = <108>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
};
back {
label = "SW-TACT6";
gpios = <&gpx2 0 1>;
linux,code = <158>;
linux,code = <KEY_BACK>;
gpio-key,wakeup;
};
wakeup {
label = "SW-TACT7";
gpios = <&gpx2 1 1>;
linux,code = <143>;
linux,code = <KEY_WAKEUP>;
gpio-key,wakeup;
};
};

6
arch/arm/boot/dts/exynos5250-cros-common.dtsi
View File

@ -240,7 +240,7 @@
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
hdmiphy@38 {
hdmiphy: hdmiphy@38 {
compatible = "samsung,exynos4212-hdmiphy";
reg = <0x38>;
};
@ -304,6 +304,10 @@
hdmi {
hpd-gpio = <&gpx3 7 0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
phy = <&hdmiphy>;
ddc = <&i2c_2>;
};
gpio-keys {

28
arch/arm/boot/dts/exynos5250-pinctrl.dtsi
View File

@ -351,6 +351,34 @@
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpb2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpb2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpb2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpb2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c7_bus: i2c7-bus {
samsung,pins = "gpb2-2", "gpb2-3";
samsung,pin-function = <3>;

224
arch/arm/boot/dts/exynos5250-snow.dts
View File

@ -25,6 +25,13 @@
};
pinctrl@11400000 {
ec_irq: ec-irq {
samsung,pins = "gpx1-6";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
sd3_clk: sd3-clk {
samsung,pin-drv = <0>;
};
@ -37,6 +44,50 @@
sd3_bus4: sd3-bus-width4 {
samsung,pin-drv = <0>;
};
max98095_en: max98095-en {
samsung,pins = "gpx1-7";
samsung,pin-function = <0>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
tps65090_irq: tps65090-irq {
samsung,pins = "gpx2-6";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
usb3_vbus_en: usb3-vbus-en {
samsung,pins = "gpx2-7";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
hdmi_hpd_irq: hdmi-hpd-irq {
samsung,pins = "gpx3-7";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
};
pinctrl@13400000 {
arb_their_claim: arb-their-claim {
samsung,pins = "gpe0-4";
samsung,pin-function = <0>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
arb_our_claim: arb-our-claim {
samsung,pins = "gpf0-3";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
gpio-keys {
@ -52,6 +103,12 @@
};
};
vbat: vbat-fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "vbat-supply";
regulator-boot-on;
};
i2c-arbitrator {
compatible = "i2c-arb-gpio-challenge";
#address-cells = <1>;
@ -65,6 +122,9 @@
wait-retry-us = <3000>;
wait-free-us = <50000>;
pinctrl-names = "default";
pinctrl-0 = <&arb_our_claim &arb_their_claim>;
/* Use ID 104 as a hint that we're on physical bus 4 */
i2c_104: i2c@0 {
reg = <0>;
@ -82,6 +142,8 @@
reg = <0x1e>;
interrupts = <6 0>;
interrupt-parent = <&gpx1>;
pinctrl-names = "default";
pinctrl-0 = <&ec_irq>;
wakeup-source;
keyboard-controller {
@ -173,6 +235,83 @@
0x070c0069>; /* LEFT */
};
};
power-regulator {
compatible = "ti,tps65090";
reg = <0x48>;
/*
* Config irq to disable internal pulls
* even though we run in polling mode.
*/
pinctrl-names = "default";
pinctrl-0 = <&tps65090_irq>;
vsys1-supply = <&vbat>;
vsys2-supply = <&vbat>;
vsys3-supply = <&vbat>;
infet1-supply = <&vbat>;
infet2-supply = <&vbat>;
infet3-supply = <&vbat>;
infet4-supply = <&vbat>;
infet5-supply = <&vbat>;
infet6-supply = <&vbat>;
infet7-supply = <&vbat>;
vsys-l1-supply = <&vbat>;
vsys-l2-supply = <&vbat>;
regulators {
dcdc1 {
ti,enable-ext-control;
};
dcdc2 {
ti,enable-ext-control;
};
dcdc3 {
ti,enable-ext-control;
};
fet1 {
regulator-name = "vcd_led";
ti,overcurrent-wait = <3>;
};
tps65090_fet2: fet2 {
regulator-name = "video_mid";
regulator-always-on;
ti,overcurrent-wait = <3>;
};
fet3 {
regulator-name = "wwan_r";
regulator-always-on;
ti,overcurrent-wait = <3>;
};
fet4 {
regulator-name = "sdcard";
ti,overcurrent-wait = <3>;
};
fet5 {
regulator-name = "camout";
regulator-always-on;
ti,overcurrent-wait = <3>;
};
fet6 {
regulator-name = "lcd_vdd";
ti,overcurrent-wait = <3>;
};
tps65090_fet7: fet7 {
regulator-name = "video_mid_1a";
regulator-always-on;
ti,overcurrent-wait = <3>;
};
ldo1 {
};
ldo2 {
};
};
charger {
compatible = "ti,tps65090-charger";
};
};
};
};
@ -196,6 +335,41 @@
};
};
i2c@12CD0000 {
max98095: codec@11 {
compatible = "maxim,max98095";
reg = <0x11>;
pinctrl-0 = <&max98095_en>;
pinctrl-names = "default";
};
};
i2s0: i2s@03830000 {
status = "okay";
};
sound {
compatible = "google,snow-audio-max98095";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98095>;
};
usb3_vbus_reg: regulator-usb3 {
compatible = "regulator-fixed";
regulator-name = "P5.0V_USB3CON";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpx2 7 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_vbus_en>;
enable-active-high;
};
phy@12100000 {
vbus-supply = <&usb3_vbus_reg>;
};
usb@12110000 {
samsung,vbus-gpio = <&gpx1 1 0>;
};
@ -206,4 +380,54 @@
clock-frequency = <24000000>;
};
};
hdmi {
hdmi-en-supply = <&tps65090_fet7>;
vdd-supply = <&ldo8_reg>;
vdd_osc-supply = <&ldo10_reg>;
vdd_pll-supply = <&ldo8_reg>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
fimd@14400000 {
status = "okay";
samsung,invert-vclk;
};
dp-controller@145B0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx0 7 0>;
display-timings {
native-mode = <&timing1>;
timing1: timing@1 {
clock-frequency = <70589280>;
hactive = <1366>;
vactive = <768>;
hfront-porch = <40>;
hback-porch = <40>;
hsync-len = <32>;
vback-porch = <10>;
vfront-porch = <12>;
vsync-len = <6>;
};
};
};
};

52
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -193,6 +193,11 @@
reg = <0x10040000 0x5000>;
};
sysreg_system_controller: syscon@10050000 {
compatible = "samsung,exynos5-sysreg", "syscon";
reg = <0x10050000 0x5000>;
};
watchdog@101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
@ -268,7 +273,7 @@
sata_phy: sata-phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock 287>;
clocks = <&clock CLK_SATA_PHYCTRL>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,syscon-phandle = <&pmu_system_controller>;
@ -551,22 +556,18 @@
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
usb-phy = <&usb2_phy &usb3_phy>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usb3_phy: usbphy@12100000 {
compatible = "samsung,exynos5250-usb3phy";
usbdrd_phy: phy@12100000 {
compatible = "samsung,exynos5250-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
clock-names = "ext_xtal", "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbphy-sys {
reg = <0x10040704 0x8>;
};
clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
usb@12110000 {
@ -576,6 +577,12 @@
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy_gen 1>;
};
};
usb@12120000 {
@ -585,6 +592,12 @@
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy_gen 1>;
};
};
usb2_phy: usbphy@12130000 {
@ -602,6 +615,16 @@
};
};
usb2_phy_gen: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
clock-names = "phy", "ref";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
@ -708,6 +731,7 @@
<&clock CLK_MOUT_HDMI>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
samsung,syscon-phandle = <&pmu_system_controller>;
};
mixer {
@ -751,7 +775,7 @@
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
interrupts = <0 112 0>;
clocks = <&clock 348>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
};

574
arch/arm/boot/dts/exynos5260-pinctrl.dtsi Normal file
View File

@ -0,0 +1,574 @@
/*
* Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
* tree nodes are listed in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define PIN_PULL_NONE 0
#define PIN_PULL_DOWN 1
#define PIN_PULL_UP 3
&pinctrl_0 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb0: gpb0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb1: gpb1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb2: gpb2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb3: gpb3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb4: gpb4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb5: gpb5 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd2: gpd2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk0: gpk0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx1: gpx1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx2: gpx2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx3: gpx3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa1-0", "gpa1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpa1-4", "gpa1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
usb3_vbus0_en: usb3-vbus0-en {
samsung,pins = "gpa2-4";
samsung,pin-function = <1>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
"gpb0-4";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
"gpb0-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
spdif1_bus: spdif1-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c0_hs_bus: i2c0-hs-bus {
samsung,pins = "gpb3-0", "gpb3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c1_hs_bus: i2c1-hs-bus {
samsung,pins = "gpb3-2", "gpb3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c2_hs_bus: i2c2-hs-bus {
samsung,pins = "gpb3-4", "gpb3-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c3_hs_bus: i2c3-hs-bus {
samsung,pins = "gpb3-6", "gpb3-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c4_bus: i2c4-bus {
samsung,pins = "gpb4-0", "gpb4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c5_bus: i2c5-bus {
samsung,pins = "gpb4-2", "gpb4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c6_bus: i2c6-bus {
samsung,pins = "gpb4-4", "gpb4-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c7_bus: i2c7-bus {
samsung,pins = "gpb4-6", "gpb4-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c8_bus: i2c8-bus {
samsung,pins = "gpb5-0", "gpb5-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c9_bus: i2c9-bus {
samsung,pins = "gpb5-2", "gpb5-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c10_bus: i2c10-bus {
samsung,pins = "gpb5-4", "gpb5-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
i2c11_bus: i2c11-bus {
samsung,pins = "gpb5-6", "gpb5-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
cam_gpio_a: cam-gpio-a {
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
"gpe1-0", "gpe1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
cam_gpio_b: cam-gpio-b {
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
cam_i2c1_bus: cam-i2c1-bus {
samsung,pins = "gpf0-2", "gpf0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
cam_i2c0_bus: cam-i2c0-bus {
samsung,pins = "gpf0-0", "gpf0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <0>;
};
cam_spi0_bus: cam-spi0-bus {
samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
cam_spi1_bus: cam-spi1-bus {
samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <0>;
};
};
&pinctrl_1 {
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc4: gpc4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpc0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpc0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpc0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd0_rdqs: sd0-rdqs {
samsung,pins = "gpc0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpc1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpc1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpc1-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd1_bus8: sd1-bus-width8 {
samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpc2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpc2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpc2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
samsung,pin-drv = <3>;
};
};
&pinctrl_2 {
gpz0: gpz0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpz1: gpz1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

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arch/arm/boot/dts/exynos5260-xyref5260.dts Normal file
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/*
* SAMSUNG XYREF5260 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos5260.dtsi"
/ {
model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
memory {
reg = <0x20000000 0x80000000>;
};
chosen {
bootargs = "console=ttySAC2,115200";
};
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
xrtcxti: xrtcxti {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xrtcxti";
#clock-cells = <0>;
};
};
&pinctrl_0 {
hdmi_hpd_irq: hdmi-hpd-irq {
samsung,pins = "gpx3-7";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&mmc_0 {
status = "okay";
num-slots = <1>;
broken-cd;
bypass-smu;
supports-highspeed;
supports-hs200-mode; /* 200 Mhz */
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
&mmc_2 {
status = "okay";
num-slots = <1>;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
};

304
arch/arm/boot/dts/exynos5260.dtsi Normal file
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/*
* SAMSUNG EXYNOS5260 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos5260-clk.h>
/ {
compatible = "samsung,exynos5260", "samsung,exynos5";
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
cci-control-port = <&cci_control1>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
cci-control-port = <&cci_control1>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control0>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control0>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control0>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
cci-control-port = <&cci_control0>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock_top: clock-controller@10010000 {
compatible = "samsung,exynos5260-clock-top";
reg = <0x10010000 0x10000>;
#clock-cells = <1>;
};
clock_peri: clock-controller@10200000 {
compatible = "samsung,exynos5260-clock-peri";
reg = <0x10200000 0x10000>;
#clock-cells = <1>;
};
clock_egl: clock-controller@10600000 {
compatible = "samsung,exynos5260-clock-egl";
reg = <0x10600000 0x10000>;
#clock-cells = <1>;
};
clock_kfc: clock-controller@10700000 {
compatible = "samsung,exynos5260-clock-kfc";
reg = <0x10700000 0x10000>;
#clock-cells = <1>;
};
clock_g2d: clock-controller@10A00000 {
compatible = "samsung,exynos5260-clock-g2d";
reg = <0x10A00000 0x10000>;
#clock-cells = <1>;
};
clock_mif: clock-controller@10CE0000 {
compatible = "samsung,exynos5260-clock-mif";
reg = <0x10CE0000 0x10000>;
#clock-cells = <1>;
};
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
};
clock_g3d: clock-controller@11830000 {
compatible = "samsung,exynos5260-clock-g3d";
reg = <0x11830000 0x10000>;
#clock-cells = <1>;
};
clock_fsys: clock-controller@122E0000 {
compatible = "samsung,exynos5260-clock-fsys";
reg = <0x122E0000 0x10000>;
#clock-cells = <1>;
};
clock_aud: clock-controller@128C0000 {
compatible = "samsung,exynos5260-clock-aud";
reg = <0x128C0000 0x10000>;
#clock-cells = <1>;
};
clock_isp: clock-controller@133C0000 {
compatible = "samsung,exynos5260-clock-isp";
reg = <0x133C0000 0x10000>;
#clock-cells = <1>;
};
clock_gscl: clock-controller@13F00000 {
compatible = "samsung,exynos5260-clock-gscl";
reg = <0x13F00000 0x10000>;
#clock-cells = <1>;
};
clock_disp: clock-controller@14550000 {
compatible = "samsung,exynos5260-clock-disp";
reg = <0x14550000 0x10000>;
#clock-cells = <1>;
};
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
chipid: chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
mct: mct@100B0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
<0 107 0>, <0 122 0>, <0 123 0>,
<0 124 0>, <0 125 0>, <0 126 0>,
<0 127 0>, <0 128 0>, <0 129 0>;
};
cci: cci@10F00000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10F00000 0x1000>;
ranges = <0x0 0x10F00000 0x6000>;
cci_control0: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control1: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
};
pinctrl_0: pinctrl@11600000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x11600000 0x1000>;
interrupts = <0 79 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
pinctrl_1: pinctrl@12290000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x12290000 0x1000>;
interrupts = <0 157 0>;
};
pinctrl_2: pinctrl@128B0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
interrupts = <0 243 0>;
};
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 146 0>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
uart1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 147 0>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
uart2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 148 0>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
uart3: serial@12860000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12860000 0x100>;
interrupts = <0 145 0>;
clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
mmc_0: mmc@12140000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12140000 0x2000>;
interrupts = <0 156 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <64>;
status = "disabled";
};
mmc_1: mmc@12150000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12150000 0x2000>;
interrupts = <0 158 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <64>;
status = "disabled";
};
mmc_2: mmc@12160000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12160000 0x2000>;
interrupts = <0 159 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <64>;
status = "disabled";
};
};
};
#include "exynos5260-pinctrl.dtsi"

82
arch/arm/boot/dts/exynos5410-smdk5410.dts Normal file
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@ -0,0 +1,82 @@
/*
* SAMSUNG SMDK5410 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos5410.dtsi"
/ {
model = "Samsung SMDK5410 board based on EXYNOS5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
bootargs = "console=ttySAC2,115200";
};
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
firmware@02037000 {
compatible = "samsung,secure-firmware";
reg = <0x02037000 0x1000>;
};
};
&mmc_0 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
&mmc_2 {
status = "okay";
num-slots = <1>;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};

206
arch/arm/boot/dts/exynos5410.dtsi Normal file
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@ -0,0 +1,206 @@
/*
* SAMSUNG EXYNOS5410 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
* EXYNOS5410 based board files can include this file and provide
* values for board specfic bindings.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos5410.h>
/ {
compatible = "samsung,exynos5410", "samsung,exynos5";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
combiner: interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
mct: mct@101C0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0xB00>;
interrupt-parent = <&interrupt_map>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&fin_pll>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupt_map: interrupt-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &combiner 23 3>,
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
<7 &gic 0 123 0>,
<8 &gic 0 128 0>,
<9 &gic 0 129 0>,
<10 &gic 0 130 0>,
<11 &gic 0 131 0>;
};
};
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
smp-sysram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
};
clock: clock-controller@10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
status = "disabled";
};
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
uart1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
uart2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
};
};

10
arch/arm/boot/dts/exynos5420-arndale-octa.dts
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@ -26,6 +26,11 @@
bootargs = "console=ttySAC3,115200";
};
firmware@02073000 {
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
fixed-rate-clocks {
oscclk {
compatible = "samsung,exynos5420-oscclk";
@ -37,6 +42,11 @@
status = "okay";
};
codec@11000000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
};
mmc@12200000 {
status = "okay";
broken-cd;

140
arch/arm/boot/dts/exynos5420-peach-pit.dts
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@ -58,9 +58,45 @@
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
sound {
compatible = "google,snow-audio-max98090";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98090>;
};
usb300_vbus_reg: regulator-usb300 {
compatible = "regulator-fixed";
regulator-name = "P5.0V_USB3CON0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gph0 0 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb300_vbus_en>;
enable-active-high;
};
usb301_vbus_reg: regulator-usb301 {
compatible = "regulator-fixed";
regulator-name = "P5.0V_USB3CON1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gph0 1 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb301_vbus_en>;
enable-active-high;
};
};
&pinctrl_0 {
max98090_irq: max98090-irq {
samsung,pins = "gpx0-2";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
tpm_irq: tpm-irq {
samsung,pins = "gpx1-0";
samsung,pin-function = <0>;
@ -74,6 +110,36 @@
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
hdmi_hpd_irq: hdmi-hpd-irq {
samsung,pins = "gpx3-7";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
dp_hpd_gpio: dp_hpd_gpio {
samsung,pins = "gpx2-6";
samsung,pin-function = <0>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_3 {
usb300_vbus_en: usb300-vbus-en {
samsung,pins = "gph0-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
usb301_vbus_en: usb301-vbus-en {
samsung,pins = "gph0-1";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
&rtc {
@ -123,6 +189,19 @@
};
};
&hsi2c_7 {
status = "okay";
max98090: codec@10 {
compatible = "maxim,max98090";
reg = <0x10>;
interrupts = <2 0>;
interrupt-parent = <&gpx0>;
pinctrl-names = "default";
pinctrl-0 = <&max98090_irq>;
};
};
&hsi2c_9 {
status = "okay";
clock-frequency = <400000>;
@ -137,6 +216,29 @@
};
};
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
samsung,i2c-slave-addr = <0x50>;
};
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
ddc = <&i2c_2>;
};
&usbdrd_phy0 {
vbus-supply = <&usb300_vbus_reg>;
};
&usbdrd_phy1 {
vbus-supply = <&usb301_vbus_reg>;
};
/*
* Use longest HW watchdog in SoC (32 seconds) since the hardware
* watchdog provides no debugging information (compared to soft/hard
@ -145,3 +247,41 @@
&watchdog {
timeout-sec = <32>;
};
&i2s0 {
status = "okay";
};
&fimd {
status = "okay";
samsung,invert-vclk;
};
&dp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 0>;
display-timings {
native-mode = <&timing1>;
timing1: timing@1 {
clock-frequency = <70589280>;
hactive = <1366>;
vactive = <768>;
hfront-porch = <40>;
hback-porch = <40>;
hsync-len = <32>;
vback-porch = <10>;
vfront-porch = <12>;
vsync-len = <6>;
};
};
};

51
arch/arm/boot/dts/exynos5420-smdk5420.dts
View File

@ -68,6 +68,11 @@
status = "okay";
};
codec@11000000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
};
mmc@12200000 {
status = "okay";
broken-cd;
@ -140,6 +145,22 @@
};
};
pinctrl@14000000 {
usb300_vbus_en: usb300-vbus-en {
samsung,pins = "gpg0-5";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
usb301_vbus_en: usb301-vbus-en {
samsung,pins = "gpg1-4";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
hdmi@14530000 {
status = "okay";
hpd-gpio = <&gpx3 7 0>;
@ -147,6 +168,36 @@
pinctrl-0 = <&hdmi_hpd_irq>;
};
usb300_vbus_reg: regulator-usb300 {
compatible = "regulator-fixed";
regulator-name = "VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpg0 5 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb300_vbus_en>;
enable-active-high;
};
usb301_vbus_reg: regulator-usb301 {
compatible = "regulator-fixed";
regulator-name = "VBUS1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpg1 4 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb301_vbus_en>;
enable-active-high;
};
phy@12100000 {
vbus-supply = <&usb300_vbus_reg>;
};
phy@12500000 {
vbus-supply = <&usb301_vbus_reg>;
};
i2c_2: i2c@12C80000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;

110
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -47,6 +47,8 @@
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
usbdrdphy0 = &usbdrd_phy0;
usbdrdphy1 = &usbdrd_phy1;
};
cpus {
@ -176,6 +178,7 @@
interrupts = <0 96 0>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
samsung,power-domain = <&mfc_pd>;
};
mmc_0: mmc@12200000 {
@ -675,7 +678,7 @@
};
hdmi: hdmi@14530000 {
compatible = "samsung,exynos4212-hdmi";
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@ -683,9 +686,15 @@
<&clock CLK_MOUT_HDMI>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
phy = <&hdmiphy>;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
hdmiphy: hdmiphy@145D0000 {
reg = <0x145D0000 0x20>;
};
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
@ -717,6 +726,11 @@
reg = <0x10040000 0x5000>;
};
sysreg_system_controller: syscon@10050000 {
compatible = "samsung,exynos5-sysreg", "syscon";
reg = <0x10050000 0x5000>;
};
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
@ -770,7 +784,99 @@
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
interrupts = <0 112 0>;
clocks = <&clock 471>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
usbdrd3_0: usb@12000000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USBD300>;
clock-names = "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dwc3 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy0: phy@12100000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
usbdrd3_1: usb@12400000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USBD301>;
clock-names = "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dwc3 {
compatible = "snps,dwc3";
reg = <0x12400000 0x10000>;
interrupts = <0 73 0>;
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy1: phy@12500000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12500000 0x100>;
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
};
usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
};
usb2_phy: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
};

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