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spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1

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SPI MEM deals with dummy bytes but the controller deals with dummy
cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S
mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses
4S mode then 1 byte will be sent in 2 cycles.

To correctly translate dummy bytes to dummy cycles, the dummy buswidth
also needs to be taken into account. Divide 8 by the buswidth to get the
correct multiplier for getting the number of cycles.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pratyush Yadav 2020-12-23 00:14:22 +05:30 committed by Mark Brown
parent 888d517b99
commit 7512eaf541
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1 changed files with 1 additions and 1 deletions
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2
drivers/spi/spi-cadence-quadspi.c
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@ -294,7 +294,7 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
{
unsigned int dummy_clk;
dummy_clk = op->dummy.nbytes * 8;
dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
return dummy_clk;
}