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net: ll_temac: fix the format of block comments
Cleaning some static warnings of block comments. Signed-off-by: huangjunxian <huangjunxian6@hisilicon.com> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com> Reviewed-by: Harini Katakam <harini.katakam@amd.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
huangjunxian
Jakub Kicinski
parent
d57aae2e05
commit
7512411652
@ -21,36 +21,45 @@
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/* Configuration options */
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/* Accept all incoming packets.
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* This option defaults to disabled (cleared) */
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* This option defaults to disabled (cleared)
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*/
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#define XTE_OPTION_PROMISC (1 << 0)
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/* Jumbo frame support for Tx & Rx.
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* This option defaults to disabled (cleared) */
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* This option defaults to disabled (cleared)
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*/
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#define XTE_OPTION_JUMBO (1 << 1)
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/* VLAN Rx & Tx frame support.
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* This option defaults to disabled (cleared) */
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* This option defaults to disabled (cleared)
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*/
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#define XTE_OPTION_VLAN (1 << 2)
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/* Enable recognition of flow control frames on Rx
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* This option defaults to enabled (set) */
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* This option defaults to enabled (set)
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*/
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#define XTE_OPTION_FLOW_CONTROL (1 << 4)
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/* Strip FCS and PAD from incoming frames.
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* Note: PAD from VLAN frames is not stripped.
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* This option defaults to disabled (set) */
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* This option defaults to disabled (set)
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*/
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#define XTE_OPTION_FCS_STRIP (1 << 5)
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/* Generate FCS field and add PAD automatically for outgoing frames.
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* This option defaults to enabled (set) */
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* This option defaults to enabled (set)
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*/
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#define XTE_OPTION_FCS_INSERT (1 << 6)
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/* Enable Length/Type error checking for incoming frames. When this option is
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set, the MAC will filter frames that have a mismatched type/length field
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and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
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types of frames are encountered. When this option is cleared, the MAC will
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allow these types of frames to be received.
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This option defaults to enabled (set) */
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* set, the MAC will filter frames that have a mismatched type/length field
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* and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
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* types of frames are encountered. When this option is cleared, the MAC will
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* allow these types of frames to be received.
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* This option defaults to enabled (set)
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*/
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#define XTE_OPTION_LENTYPE_ERR (1 << 7)
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/* Enable the transmitter.
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* This option defaults to enabled (set) */
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* This option defaults to enabled (set)
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*/
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#define XTE_OPTION_TXEN (1 << 11)
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/* Enable the receiver
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* This option defaults to enabled (set) */
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* This option defaults to enabled (set)
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*/
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#define XTE_OPTION_RXEN (1 << 12)
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/* Default options set when device is initialized or reset */
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@ -68,18 +77,18 @@ This option defaults to enabled (set) */
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#define TX_TAILDESC_PTR 0x04 /* rw */
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#define TX_CHNL_CTRL 0x05 /* rw */
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/*
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0:7 24:31 IRQTimeout
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8:15 16:23 IRQCount
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16:20 11:15 Reserved
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21 10 0
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22 9 UseIntOnEnd
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23 8 LdIRQCnt
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24 7 IRQEn
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25:28 3:6 Reserved
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29 2 IrqErrEn
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30 1 IrqDlyEn
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31 0 IrqCoalEn
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*/
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* 0:7 24:31 IRQTimeout
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* 8:15 16:23 IRQCount
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* 16:20 11:15 Reserved
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* 21 10 0
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* 22 9 UseIntOnEnd
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* 23 8 LdIRQCnt
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* 24 7 IRQEn
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* 25:28 3:6 Reserved
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* 29 2 IrqErrEn
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* 30 1 IrqDlyEn
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* 31 0 IrqCoalEn
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*/
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#define CHNL_CTRL_IRQ_IOE (1 << 9)
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#define CHNL_CTRL_IRQ_EN (1 << 7)
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#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
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@ -87,35 +96,35 @@ This option defaults to enabled (set) */
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#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
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#define TX_IRQ_REG 0x06 /* rw */
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/*
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0:7 24:31 DltTmrValue
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8:15 16:23 ClscCntrValue
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16:17 14:15 Reserved
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18:21 10:13 ClscCnt
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22:23 8:9 DlyCnt
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24:28 3::7 Reserved
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29 2 ErrIrq
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30 1 DlyIrq
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31 0 CoalIrq
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* 0:7 24:31 DltTmrValue
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* 8:15 16:23 ClscCntrValue
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* 16:17 14:15 Reserved
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* 18:21 10:13 ClscCnt
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* 22:23 8:9 DlyCnt
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* 24:28 3::7 Reserved
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* 29 2 ErrIrq
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* 30 1 DlyIrq
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* 31 0 CoalIrq
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*/
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#define TX_CHNL_STS 0x07 /* r */
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/*
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0:9 22:31 Reserved
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10 21 TailPErr
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11 20 CmpErr
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12 19 AddrErr
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13 18 NxtPErr
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14 17 CurPErr
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15 16 BsyWr
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16:23 8:15 Reserved
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24 7 Error
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25 6 IOE
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26 5 SOE
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27 4 Cmplt
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28 3 SOP
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29 2 EOP
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30 1 EngBusy
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31 0 Reserved
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*/
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* 0:9 22:31 Reserved
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* 10 21 TailPErr
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* 11 20 CmpErr
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* 12 19 AddrErr
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* 13 18 NxtPErr
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* 14 17 CurPErr
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* 15 16 BsyWr
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* 16:23 8:15 Reserved
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* 24 7 Error
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* 25 6 IOE
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* 26 5 SOE
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* 27 4 Cmplt
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* 28 3 SOP
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* 29 2 EOP
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* 30 1 EngBusy
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* 31 0 Reserved
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*/
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#define RX_NXTDESC_PTR 0x08 /* r */
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#define RX_CURBUF_ADDR 0x09 /* r */
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@ -124,17 +133,17 @@ This option defaults to enabled (set) */
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#define RX_TAILDESC_PTR 0x0c /* rw */
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#define RX_CHNL_CTRL 0x0d /* rw */
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/*
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0:7 24:31 IRQTimeout
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8:15 16:23 IRQCount
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16:20 11:15 Reserved
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21 10 0
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22 9 UseIntOnEnd
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23 8 LdIRQCnt
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24 7 IRQEn
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25:28 3:6 Reserved
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29 2 IrqErrEn
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30 1 IrqDlyEn
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31 0 IrqCoalEn
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* 0:7 24:31 IRQTimeout
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* 8:15 16:23 IRQCount
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* 16:20 11:15 Reserved
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* 21 10 0
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* 22 9 UseIntOnEnd
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* 23 8 LdIRQCnt
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* 24 7 IRQEn
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* 25:28 3:6 Reserved
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* 29 2 IrqErrEn
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* 30 1 IrqDlyEn
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* 31 0 IrqCoalEn
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*/
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#define RX_IRQ_REG 0x0e /* rw */
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#define IRQ_COAL (1 << 0)
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@ -142,13 +151,13 @@ This option defaults to enabled (set) */
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#define IRQ_ERR (1 << 2)
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#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
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/*
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0:7 24:31 DltTmrValue
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8:15 16:23 ClscCntrValue
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16:17 14:15 Reserved
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18:21 10:13 ClscCnt
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22:23 8:9 DlyCnt
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24:28 3::7 Reserved
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*/
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* 0:7 24:31 DltTmrValue
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* 8:15 16:23 ClscCntrValue
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* 16:17 14:15 Reserved
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* 18:21 10:13 ClscCnt
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* 22:23 8:9 DlyCnt
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* 24:28 3::7 Reserved
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*/
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#define RX_CHNL_STS 0x0f /* r */
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#define CHNL_STS_ENGBUSY (1 << 1)
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#define CHNL_STS_EOP (1 << 2)
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@ -165,23 +174,23 @@ This option defaults to enabled (set) */
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#define CHNL_STS_CMPERR (1 << 20)
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#define CHNL_STS_TAILERR (1 << 21)
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/*
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0:9 22:31 Reserved
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10 21 TailPErr
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11 20 CmpErr
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12 19 AddrErr
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13 18 NxtPErr
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14 17 CurPErr
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15 16 BsyWr
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16:23 8:15 Reserved
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24 7 Error
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25 6 IOE
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26 5 SOE
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27 4 Cmplt
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28 3 SOP
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29 2 EOP
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30 1 EngBusy
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31 0 Reserved
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*/
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* 0:9 22:31 Reserved
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* 10 21 TailPErr
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* 11 20 CmpErr
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* 12 19 AddrErr
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* 13 18 NxtPErr
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* 14 17 CurPErr
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* 15 16 BsyWr
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* 16:23 8:15 Reserved
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* 24 7 Error
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* 25 6 IOE
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* 26 5 SOE
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* 27 4 Cmplt
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* 28 3 SOP
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* 29 2 EOP
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* 30 1 EngBusy
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* 31 0 Reserved
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*/
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#define DMA_CONTROL_REG 0x10 /* rw */
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#define DMA_CONTROL_RST (1 << 0)
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@ -430,7 +430,8 @@ static void temac_do_set_mac_address(struct net_device *ndev)
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(ndev->dev_addr[2] << 16) |
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(ndev->dev_addr[3] << 24));
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/* There are reserved bits in EUAW1
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* so don't affect them Set MAC bits [47:32] in EUAW1 */
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* so don't affect them Set MAC bits [47:32] in EUAW1
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*/
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temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
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(ndev->dev_addr[4] & 0x000000ff) |
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(ndev->dev_addr[5] << 8));
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@ -691,7 +692,8 @@ static void temac_device_reset(struct net_device *ndev)
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spin_unlock_irqrestore(lp->indirect_lock, flags);
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/* Sync default options with HW
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* but leave receiver and transmitter disabled. */
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* but leave receiver and transmitter disabled.
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*/
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temac_setoptions(ndev,
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lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
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@ -29,7 +29,8 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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/* Write the PHY address to the MIIM Access Initiator register.
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* When the transfer completes, the PHY register value will appear
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* in the LSW0 register */
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* in the LSW0 register
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*/
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spin_lock_irqsave(lp->indirect_lock, flags);
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temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
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rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET);
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@ -88,7 +89,8 @@ int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev)
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}
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/* Enable the MDIO bus by asserting the enable bit and writing
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* in the clock config */
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* in the clock config
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*/
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temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
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bus = devm_mdiobus_alloc(&pdev->dev);
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