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ath9k_hw: Add function to configure tx status ring buffer
Also reset tx status ring suring chip reset. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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cc610ac055
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@ -347,3 +347,33 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
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return 0;
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}
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EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
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void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
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{
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ah->ts_tail = 0;
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memset((void *) ah->ts_ring, 0,
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ah->ts_size * sizeof(struct ar9003_txs));
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ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
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"TS Start 0x%x End 0x%x Virt %p, Size %d\n",
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ah->ts_paddr_start, ah->ts_paddr_end,
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ah->ts_ring, ah->ts_size);
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REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
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REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
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}
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void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
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u32 ts_paddr_start,
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u8 size)
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{
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ah->ts_paddr_start = ts_paddr_start;
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ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
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ah->ts_size = size;
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ah->ts_ring = (struct ar9003_txs *) ts_start;
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ath9k_hw_reset_txstatus_ring(ah);
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}
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EXPORT_SYMBOL(ath9k_hw_setup_statusring);
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@ -73,6 +73,18 @@ struct ar9003_txc {
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u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
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} __packed;
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struct ar9003_txs {
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u32 ds_info;
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u32 status1;
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u32 status2;
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u32 status3;
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u32 status4;
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u32 status5;
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u32 status6;
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u32 status7;
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u32 status8;
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} __packed;
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void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
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void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
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void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
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@ -81,5 +93,8 @@ void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
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int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
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struct ath_rx_status *rxs,
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void *buf_addr);
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void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
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void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
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u32 ts_paddr_start,
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u8 size);
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#endif
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@ -895,6 +895,9 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
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AR_PCU_TXBUF_CTRL_USABLE_SIZE);
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}
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if (AR_SREV_9300_20_OR_LATER(ah))
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ath9k_hw_reset_txstatus_ring(ah);
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}
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static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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@ -761,6 +761,13 @@ struct ath_hw {
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u32 intr_gen_timer_trigger;
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u32 intr_gen_timer_thresh;
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struct ath_gen_timer_table hw_gen_timers;
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struct ar9003_txs *ts_ring;
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void *ts_start;
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u32 ts_paddr_start;
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u32 ts_paddr_end;
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u16 ts_tail;
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u8 ts_size;
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};
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static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
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@ -383,6 +383,9 @@
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#define AR_Q9_TXDP 0x0824
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#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
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#define AR_Q_STATUS_RING_START 0x830
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#define AR_Q_STATUS_RING_END 0x834
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#define AR_Q_TXE 0x0840
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#define AR_Q_TXE_M 0x000003FF
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