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media: platform: mtk-mdp3: introduce more MDP3 components
Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Moudy Ho
Mauro Carvalho Chehab
parent
d9b52f7356
commit
73e00953c3
25
drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
Normal file
25
drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
Normal file
@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_AAL_H__
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#define __MDP_REG_AAL_H__
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#define MDP_AAL_EN (0x000)
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#define MDP_AAL_CFG (0x020)
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#define MDP_AAL_SIZE (0x030)
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#define MDP_AAL_OUTPUT_SIZE (0x034)
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#define MDP_AAL_OUTPUT_OFFSET (0x038)
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#define MDP_AAL_CFG_MAIN (0x200)
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/* MASK */
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#define MDP_AAL_EN_MASK (0x01)
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#define MDP_AAL_CFG_MASK (0x70FF00B3)
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#define MDP_AAL_SIZE_MASK (0x1FFF1FFF)
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#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF)
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#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF)
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#define MDP_AAL_CFG_MAIN_MASK (0x0FE)
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#endif // __MDP_REG_AAL_H__
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31
drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
Normal file
31
drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
Normal file
@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_COLOR_H__
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#define __MDP_REG_COLOR_H__
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#define MDP_COLOR_WIN_X_MAIN (0x40C)
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#define MDP_COLOR_WIN_Y_MAIN (0x410)
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#define MDP_COLOR_START (0xC00)
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#define MDP_COLOR_INTEN (0xC04)
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#define MDP_COLOR_OUT_SEL (0xC0C)
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#define MDP_COLOR_INTERNAL_IP_WIDTH (0xC50)
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#define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54)
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#define MDP_COLOR_CM1_EN (0xC60)
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#define MDP_COLOR_CM2_EN (0xCA0)
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/* MASK */
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#define MDP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF)
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#define MDP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF)
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#define MDP_COLOR_START_MASK (0x0FF013F)
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#define MDP_COLOR_INTEN_MASK (0x07)
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#define MDP_COLOR_OUT_SEL_MASK (0x0777)
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#define MDP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF)
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#define MDP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF)
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#define MDP_COLOR_CM1_EN_MASK (0x03)
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#define MDP_COLOR_CM2_EN_MASK (0x017)
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#endif // __MDP_REG_COLOR_H__
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23
drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
Normal file
23
drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
Normal file
@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_FG_H__
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#define __MDP_REG_FG_H__
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#define MDP_FG_TRIGGER (0x0)
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#define MDP_FG_FG_CTRL_0 (0x20)
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#define MDP_FG_FG_CK_EN (0x24)
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#define MDP_FG_TILE_INFO_0 (0x418)
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#define MDP_FG_TILE_INFO_1 (0x41c)
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/* MASK */
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#define MDP_FG_TRIGGER_MASK (0x00000007)
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#define MDP_FG_FG_CTRL_0_MASK (0x00000033)
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#define MDP_FG_FG_CK_EN_MASK (0x0000000F)
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#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF)
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#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF)
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#endif //__MDP_REG_FG_H__
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31
drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
Normal file
31
drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
Normal file
@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_HDR_H__
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#define __MDP_REG_HDR_H__
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#define MDP_HDR_TOP (0x000)
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#define MDP_HDR_RELAY (0x004)
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#define MDP_HDR_SIZE_0 (0x014)
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#define MDP_HDR_SIZE_1 (0x018)
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#define MDP_HDR_SIZE_2 (0x01C)
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#define MDP_HDR_HIST_CTRL_0 (0x020)
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#define MDP_HDR_HIST_CTRL_1 (0x024)
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#define MDP_HDR_HIST_ADDR (0x0DC)
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#define MDP_HDR_TILE_POS (0x118)
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/* MASK */
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#define MDP_HDR_RELAY_MASK (0x01)
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#define MDP_HDR_TOP_MASK (0xFF0FEB6D)
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#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)
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#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)
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#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)
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#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)
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#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)
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#endif // __MDP_REG_HDR_H__
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25
drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
Normal file
25
drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
Normal file
@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_MERGE_H__
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#define __MDP_REG_MERGE_H__
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#define MDP_MERGE_ENABLE (0x000)
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#define MDP_MERGE_CFG_0 (0x010)
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#define MDP_MERGE_CFG_4 (0x020)
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#define MDP_MERGE_CFG_12 (0x040)
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#define MDP_MERGE_CFG_24 (0x070)
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#define MDP_MERGE_CFG_25 (0x074)
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/* MASK */
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#define MDP_MERGE_ENABLE_MASK (0xFFFFFFFF)
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#define MDP_MERGE_CFG_0_MASK (0xFFFFFFFF)
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#define MDP_MERGE_CFG_4_MASK (0xFFFFFFFF)
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#define MDP_MERGE_CFG_12_MASK (0xFFFFFFFF)
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#define MDP_MERGE_CFG_24_MASK (0xFFFFFFFF)
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#define MDP_MERGE_CFG_25_MASK (0xFFFFFFFF)
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#endif //__MDP_REG_MERGE_H__
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25
drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
Normal file
25
drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
Normal file
@ -0,0 +1,25 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_OVL_H__
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#define __MDP_REG_OVL_H__
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#define MDP_OVL_EN (0x00c)
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#define MDP_OVL_ROI_SIZE (0x020)
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#define MDP_OVL_DP_CON (0x024)
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#define MDP_OVL_SRC_CON (0x02c)
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#define MDP_OVL_L0_CON (0x030)
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#define MDP_OVL_L0_SRC_SIZE (0x038)
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/* MASK */
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#define MDP_OVL_DP_CON_MASK (0x0FFFFFFF)
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#define MDP_OVL_EN_MASK (0xB07D07B1)
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#define MDP_OVL_L0_CON_MASK (0xFFFFFFFF)
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#define MDP_OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF)
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#define MDP_OVL_ROI_SIZE_MASK (0x1FFF1FFF)
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#define MDP_OVL_SRC_CON_MASK (0x0000031F)
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#endif //__MDP_REG_OVL_H__
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21
drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
Normal file
21
drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
Normal file
@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_PAD_H__
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#define __MDP_REG_PAD_H__
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#define MDP_PAD_CON (0x000)
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#define MDP_PAD_PIC_SIZE (0x004)
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#define MDP_PAD_W_SIZE (0x008)
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#define MDP_PAD_H_SIZE (0x00c)
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/* MASK */
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#define MDP_PAD_CON_MASK (0x00000007)
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#define MDP_PAD_PIC_SIZE_MASK (0xFFFFFFFF)
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#define MDP_PAD_W_SIZE_MASK (0x1FFF1FFF)
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#define MDP_PAD_H_SIZE_MASK (0x1FFF1FFF)
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#endif // __MDP_REG_PAD_H__
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@ -26,6 +26,18 @@
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#define MDP_RDMA_SRC_OFFSET_2 0x128
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#define MDP_RDMA_SRC_OFFSET_0_P 0x148
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#define MDP_RDMA_TRANSFORM_0 0x200
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#define MDP_RDMA_DMABUF_CON_0 0x240
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248
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#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250
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#define MDP_RDMA_DMABUF_CON_1 0x258
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
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#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
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#define MDP_RDMA_DMABUF_CON_2 0x270
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278
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#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
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#define MDP_RDMA_DMABUF_CON_3 0x288
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290
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#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
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#define MDP_RDMA_RESV_DUMMY_0 0x2a0
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#define MDP_RDMA_MON_STA_1 0x408
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#define MDP_RDMA_SRC_BASE_0 0xf00
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@ -54,6 +66,18 @@
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#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
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#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
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#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
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#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff
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#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff
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#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff
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#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff
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#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff
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#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff
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#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f
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#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff
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#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff
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#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
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#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
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#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
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@ -20,6 +20,7 @@
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#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
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#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
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#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034
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#define RSZ_ETC_CONTROL 0x22c
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/* MASK */
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#define PRZ_ENABLE_MASK 0x00010001
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@ -35,5 +36,6 @@
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#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
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#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
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#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
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#define RSZ_ETC_CONTROL_MASK 0xff770000
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#endif // __MDP_REG_RSZ_H__
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34
drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
Normal file
34
drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_TDSHP_H__
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#define __MDP_REG_TDSHP_H__
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#define MDP_HIST_CFG_00 (0x064)
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#define MDP_HIST_CFG_01 (0x068)
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#define MDP_TDSHP_CTRL (0x100)
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#define MDP_TDSHP_CFG (0x110)
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#define MDP_TDSHP_INPUT_SIZE (0x120)
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#define MDP_TDSHP_OUTPUT_OFFSET (0x124)
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#define MDP_TDSHP_OUTPUT_SIZE (0x128)
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#define MDP_LUMA_HIST_INIT (0x200)
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#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
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#define MDP_CONTOUR_HIST_INIT (0x398)
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/* MASK */
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#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF)
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#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF)
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#define MDP_LUMA_HIST_MASK (0xFFFFFFFF)
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#define MDP_TDSHP_CTRL_MASK (0x07)
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#define MDP_TDSHP_CFG_MASK (0x03F7)
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#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF)
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#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF)
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#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF)
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#define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF)
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#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF)
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#define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF)
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#endif // __MDP_REG_TDSHP_H__
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@ -17,14 +17,18 @@
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#define VIDO_STRIDE 0x030
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#define VIDO_OFST_ADDR_C 0x038
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#define VIDO_STRIDE_C 0x03c
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#define VIDO_CTRL_2 0x048
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#define VIDO_DITHER 0x054
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#define VIDO_STRIDE_V 0x06c
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#define VIDO_OFST_ADDR_V 0x068
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#define VIDO_RSV_1 0x070
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#define VIDO_DMA_PREULTRA 0x074
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#define VIDO_IN_SIZE 0x078
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#define VIDO_ROT_EN 0x07c
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#define VIDO_FIFO_TEST 0x080
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#define VIDO_MAT_CTRL 0x084
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#define VIDO_SCAN_10BIT 0x0dc
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#define VIDO_PENDING_ZERO 0x0e0
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#define VIDO_BASE_ADDR 0xf00
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#define VIDO_BASE_ADDR_C 0xf04
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#define VIDO_BASE_ADDR_V 0xf08
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@ -40,14 +44,18 @@
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#define VIDO_STRIDE_MASK 0x0000ffff
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#define VIDO_OFST_ADDR_C_MASK 0x0fffffff
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#define VIDO_STRIDE_C_MASK 0x0000ffff
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#define VIDO_CTRL_2_MASK 0x0000000f
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#define VIDO_DITHER_MASK 0xff000001
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#define VIDO_STRIDE_V_MASK 0x0000ffff
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#define VIDO_OFST_ADDR_V_MASK 0x0fffffff
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#define VIDO_RSV_1_MASK 0xffffffff
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#define VIDO_DMA_PREULTRA_MASK 0x00ffffff
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#define VIDO_IN_SIZE_MASK 0x1fff1fff
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#define VIDO_ROT_EN_MASK 0x00000001
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#define VIDO_FIFO_TEST_MASK 0x00000fff
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#define VIDO_MAT_CTRL_MASK 0x000000f3
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#define VIDO_SCAN_10BIT_MASK 0x0000000f
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#define VIDO_PENDING_ZERO_MASK 0x07ffffff
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#define VIDO_BASE_ADDR_MASK 0xffffffff
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#define VIDO_BASE_ADDR_C_MASK 0xffffffff
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#define VIDO_BASE_ADDR_V_MASK 0xffffffff
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@ -84,22 +84,66 @@ enum mtk_mdp_comp_id {
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MDP_COMP_CAMIN, /* 9 */
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MDP_COMP_CAMIN2, /* 10 */
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MDP_COMP_RDMA0, /* 11 */
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MDP_COMP_AAL0, /* 12 */
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MDP_COMP_CCORR0, /* 13 */
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MDP_COMP_RSZ0, /* 14 */
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MDP_COMP_RSZ1, /* 15 */
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MDP_COMP_TDSHP0, /* 16 */
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MDP_COMP_COLOR0, /* 17 */
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MDP_COMP_PATH0_SOUT, /* 18 */
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MDP_COMP_PATH1_SOUT, /* 19 */
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||||
MDP_COMP_WROT0, /* 20 */
|
||||
MDP_COMP_WDMA, /* 21 */
|
||||
|
||||
/* Dummy Engine */
|
||||
MDP_COMP_RDMA1, /* 22 */
|
||||
MDP_COMP_RSZ2, /* 23 */
|
||||
MDP_COMP_TDSHP1, /* 24 */
|
||||
MDP_COMP_WROT1, /* 25 */
|
||||
MDP_COMP_RDMA1, /* 12 */
|
||||
MDP_COMP_RDMA2, /* 13 */
|
||||
MDP_COMP_RDMA3, /* 14 */
|
||||
MDP_COMP_AAL0, /* 15 */
|
||||
MDP_COMP_AAL1, /* 16 */
|
||||
MDP_COMP_AAL2, /* 17 */
|
||||
MDP_COMP_AAL3, /* 18 */
|
||||
MDP_COMP_CCORR0, /* 19 */
|
||||
MDP_COMP_RSZ0, /* 20 */
|
||||
MDP_COMP_RSZ1, /* 21 */
|
||||
MDP_COMP_RSZ2, /* 22 */
|
||||
MDP_COMP_RSZ3, /* 23 */
|
||||
MDP_COMP_TDSHP0, /* 24 */
|
||||
MDP_COMP_TDSHP1, /* 25 */
|
||||
MDP_COMP_TDSHP2, /* 26 */
|
||||
MDP_COMP_TDSHP3, /* 27 */
|
||||
MDP_COMP_COLOR0, /* 28 */
|
||||
MDP_COMP_COLOR1, /* 29 */
|
||||
MDP_COMP_COLOR2, /* 30 */
|
||||
MDP_COMP_COLOR3, /* 31 */
|
||||
MDP_COMP_PATH0_SOUT, /* 32 */
|
||||
MDP_COMP_PATH1_SOUT, /* 33 */
|
||||
MDP_COMP_WROT0, /* 34 */
|
||||
MDP_COMP_WROT1, /* 35 */
|
||||
MDP_COMP_WROT2, /* 36 */
|
||||
MDP_COMP_WROT3, /* 37 */
|
||||
MDP_COMP_WDMA, /* 38 */
|
||||
MDP_COMP_SPLIT, /* 39 */
|
||||
MDP_COMP_SPLIT2, /* 40 */
|
||||
MDP_COMP_STITCH, /* 41 */
|
||||
MDP_COMP_FG0, /* 42 */
|
||||
MDP_COMP_FG1, /* 43 */
|
||||
MDP_COMP_FG2, /* 44 */
|
||||
MDP_COMP_FG3, /* 45 */
|
||||
MDP_COMP_TO_SVPP2MOUT, /* 46 */
|
||||
MDP_COMP_TO_SVPP3MOUT, /* 47 */
|
||||
MDP_COMP_TO_WARP0MOUT, /* 48 */
|
||||
MDP_COMP_TO_WARP1MOUT, /* 49 */
|
||||
MDP_COMP_VPP0_SOUT, /* 50 */
|
||||
MDP_COMP_VPP1_SOUT, /* 51 */
|
||||
MDP_COMP_PQ0_SOUT, /* 52 */
|
||||
MDP_COMP_PQ1_SOUT, /* 53 */
|
||||
MDP_COMP_HDR0, /* 54 */
|
||||
MDP_COMP_HDR1, /* 55 */
|
||||
MDP_COMP_HDR2, /* 56 */
|
||||
MDP_COMP_HDR3, /* 57 */
|
||||
MDP_COMP_OVL0, /* 58 */
|
||||
MDP_COMP_OVL1, /* 59 */
|
||||
MDP_COMP_PAD0, /* 60 */
|
||||
MDP_COMP_PAD1, /* 61 */
|
||||
MDP_COMP_PAD2, /* 62 */
|
||||
MDP_COMP_PAD3, /* 63 */
|
||||
MDP_COMP_TCC0, /* 64 */
|
||||
MDP_COMP_TCC1, /* 65 */
|
||||
MDP_COMP_MERGE2, /* 66 */
|
||||
MDP_COMP_MERGE3, /* 67 */
|
||||
MDP_COMP_VDO0DL0, /* 68 */
|
||||
MDP_COMP_VDO1DL0, /* 69 */
|
||||
MDP_COMP_VDO0DL1, /* 70 */
|
||||
MDP_COMP_VDO1DL1, /* 71 */
|
||||
|
||||
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
|
||||
};
|
||||
@ -117,12 +161,21 @@ enum mdp_comp_type {
|
||||
MDP_COMP_TYPE_COLOR,
|
||||
MDP_COMP_TYPE_DRE,
|
||||
MDP_COMP_TYPE_CCORR,
|
||||
MDP_COMP_TYPE_AAL,
|
||||
MDP_COMP_TYPE_TCC,
|
||||
MDP_COMP_TYPE_HDR,
|
||||
MDP_COMP_TYPE_SPLIT,
|
||||
MDP_COMP_TYPE_STITCH,
|
||||
MDP_COMP_TYPE_FG,
|
||||
MDP_COMP_TYPE_OVL,
|
||||
MDP_COMP_TYPE_PAD,
|
||||
MDP_COMP_TYPE_MERGE,
|
||||
|
||||
MDP_COMP_TYPE_IMGI,
|
||||
MDP_COMP_TYPE_WPEI,
|
||||
MDP_COMP_TYPE_EXTO, /* External path */
|
||||
MDP_COMP_TYPE_DL_PATH, /* Direct-link path */
|
||||
MDP_COMP_TYPE_DUMMY,
|
||||
|
||||
MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user