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msm:disp:dpu1: setup display datapath for SC7180 target
Add changes to setup display datapath on SC7180 target. Changes in v1: - Add changes to support ctl_active on SC7180 target. - While selecting the number of mixers in the topology consider the interface width. Changes in v2: - Spawn topology mixer selection into separate patch (Rob Clark). - Add co-developed-by tags in the commit msg (Stephen Boyd). Changes in v3: - Fix kernel checkpatch errors in v2. This patch has dependency on the below series https://patchwork.kernel.org/patch/11253747/ Co-developed-by: Shubhashree Dhar <dhar@codeaurora.org> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org> Co-developed-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Kalyan Thota
Rob Clark
parent
7bdc0c4b81
commit
73bfb790ac
@ -280,6 +280,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
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phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
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&timing_params, fmt);
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phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
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/* setup which pp blk will connect to this intf */
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if (phys_enc->hw_intf->ops.bind_pingpong_blk)
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phys_enc->hw_intf->ops.bind_pingpong_blk(
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phys_enc->hw_intf,
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true,
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phys_enc->hw_pp->idx);
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spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
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programmable_fetch_config(phys_enc, &timing_params);
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@ -435,6 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_hw_ctl *ctl;
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u32 flush_mask = 0;
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u32 intf_flush_mask = 0;
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ctl = phys_enc->hw_ctl;
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@ -459,10 +468,18 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
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ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
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ctl->ops.update_pending_flush(ctl, flush_mask);
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if (ctl->ops.get_bitmask_active_intf)
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ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
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phys_enc->hw_intf->idx);
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if (ctl->ops.update_pending_intf_flush)
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ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
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skip_flush:
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DPU_DEBUG_VIDENC(phys_enc,
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"update pending flush ctl %d flush_mask %x\n",
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ctl->idx - CTL_0, flush_mask);
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"update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
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ctl->idx - CTL_0, flush_mask, intf_flush_mask);
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/* ctl_flush & timing engine enable will be triggered by framework */
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if (phys_enc->enable_state == DPU_ENC_DISABLED)
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@ -374,6 +374,7 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
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{\
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.name = _name, .id = _id, \
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.base = _base, .len = 0x280, \
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.features = BIT(DPU_CTL_ACTIVE_CFG), \
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.type = _type, \
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.controller_id = _ctrl_id, \
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.prog_fetch_lines_worst_case = 24 \
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@ -22,11 +22,15 @@
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#define CTL_PREPARE 0x0d0
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#define CTL_SW_RESET 0x030
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#define CTL_LAYER_EXTN_OFFSET 0x40
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#define CTL_INTF_ACTIVE 0x0F4
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#define CTL_INTF_FLUSH 0x110
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#define CTL_INTF_MASTER 0x134
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#define CTL_MIXER_BORDER_OUT BIT(24)
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#define CTL_FLUSH_MASK_CTL BIT(17)
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#define DPU_REG_RESET_TIMEOUT_US 2000
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#define INTF_IDX 31
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static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
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const struct dpu_mdss_cfg *m,
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@ -100,11 +104,27 @@ static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
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ctx->pending_flush_mask |= flushbits;
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}
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static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx,
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u32 flushbits)
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{
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ctx->pending_intf_flush_mask |= flushbits;
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}
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static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
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{
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return ctx->pending_flush_mask;
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}
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static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
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{
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if (ctx->pending_flush_mask & BIT(INTF_IDX))
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DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
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ctx->pending_intf_flush_mask);
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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}
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static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
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{
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trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
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@ -222,6 +242,36 @@ static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
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return 0;
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}
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static int dpu_hw_ctl_get_bitmask_intf_v1(struct dpu_hw_ctl *ctx,
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u32 *flushbits, enum dpu_intf intf)
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{
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switch (intf) {
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case INTF_0:
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case INTF_1:
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*flushbits |= BIT(31);
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break;
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default:
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return 0;
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}
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return 0;
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}
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static int dpu_hw_ctl_active_get_bitmask_intf(struct dpu_hw_ctl *ctx,
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u32 *flushbits, enum dpu_intf intf)
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{
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switch (intf) {
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case INTF_0:
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*flushbits |= BIT(0);
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break;
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case INTF_1:
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*flushbits |= BIT(1);
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break;
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default:
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return 0;
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}
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return 0;
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}
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static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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@ -422,6 +472,24 @@ exit:
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DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
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}
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static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 intf_active = 0;
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u32 mode_sel = 0;
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if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
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mode_sel |= BIT(17);
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intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
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intf_active |= BIT(cfg->intf - INTF_0);
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DPU_REG_WRITE(c, CTL_TOP, mode_sel);
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DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
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}
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static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg)
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{
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@ -455,21 +523,31 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
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unsigned long cap)
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{
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if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
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ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
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ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf_v1;
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ops->get_bitmask_active_intf =
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dpu_hw_ctl_active_get_bitmask_intf;
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ops->update_pending_intf_flush =
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dpu_hw_ctl_update_pending_intf_flush;
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} else {
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ops->trigger_flush = dpu_hw_ctl_trigger_flush;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
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ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
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}
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ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
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ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
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ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
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ops->trigger_flush = dpu_hw_ctl_trigger_flush;
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ops->get_flush_register = dpu_hw_ctl_get_flush_register;
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ops->trigger_start = dpu_hw_ctl_trigger_start;
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ops->trigger_pending = dpu_hw_ctl_trigger_pending;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
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ops->reset = dpu_hw_ctl_reset_control;
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ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
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ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
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ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
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ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
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ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
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ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
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};
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static struct dpu_hw_blk_ops dpu_hw_ops;
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@ -90,6 +90,15 @@ struct dpu_hw_ctl_ops {
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void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
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u32 flushbits);
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/**
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* OR in the given flushbits to the cached pending_intf_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @flushbits : module flushmask
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*/
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void (*update_pending_intf_flush)(struct dpu_hw_ctl *ctx,
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u32 flushbits);
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/**
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* Write the value of the pending_flush_mask to hardware
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* @ctx : ctl path ctx pointer
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@ -130,10 +139,23 @@ struct dpu_hw_ctl_ops {
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uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
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enum dpu_lm blk);
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/**
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* Query the value of the intf flush mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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*/
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int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx,
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u32 *flushbits,
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enum dpu_intf blk);
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/**
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* Query the value of the intf active flush mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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*/
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int (*get_bitmask_active_intf)(struct dpu_hw_ctl *ctx,
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u32 *flushbits, enum dpu_intf blk);
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/**
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* Set all blend stages to disabled
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* @ctx : ctl path ctx pointer
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@ -159,6 +181,7 @@ struct dpu_hw_ctl_ops {
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* @mixer_count: number of mixers
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* @mixer_hw_caps: mixer hardware capabilities
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* @pending_flush_mask: storage for pending ctl_flush managed via ops
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* @pending_intf_flush_mask: pending INTF flush
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* @ops: operation list
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*/
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struct dpu_hw_ctl {
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@ -171,6 +194,7 @@ struct dpu_hw_ctl {
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int mixer_count;
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const struct dpu_lm_cfg *mixer_hw_caps;
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u32 pending_flush_mask;
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u32 pending_intf_flush_mask;
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/* ops */
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struct dpu_hw_ctl_ops ops;
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@ -56,6 +56,8 @@
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#define INTF_FRAME_COUNT 0x0AC
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#define INTF_LINE_COUNT 0x0B0
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#define INTF_MUX 0x25C
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static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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@ -218,6 +220,30 @@ static void dpu_hw_intf_setup_prg_fetch(
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DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
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}
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static void dpu_hw_intf_bind_pingpong_blk(
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struct dpu_hw_intf *intf,
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bool enable,
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const enum dpu_pingpong pp)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 mux_cfg;
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if (!intf)
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return;
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c = &intf->hw;
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mux_cfg = DPU_REG_READ(c, INTF_MUX);
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mux_cfg &= ~0xf;
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if (enable)
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mux_cfg |= (pp - PINGPONG_0) & 0x7;
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else
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mux_cfg |= 0xf;
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DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
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}
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static void dpu_hw_intf_get_status(
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struct dpu_hw_intf *intf,
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struct intf_status *s)
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@ -254,6 +280,8 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
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ops->get_status = dpu_hw_intf_get_status;
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ops->enable_timing = dpu_hw_intf_enable_timing_engine;
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ops->get_line_count = dpu_hw_intf_get_line_count;
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if (cap & BIT(DPU_CTL_ACTIVE_CFG))
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ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
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}
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static struct dpu_hw_blk_ops dpu_hw_ops;
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@ -52,6 +52,8 @@ struct intf_status {
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* @ enable_timing: enable/disable timing engine
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* @ get_status: returns if timing engine is enabled or not
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* @ get_line_count: reads current vertical line counter
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* @bind_pingpong_blk: enable/disable the connection with pingpong which will
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* feed pixels to this interface
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*/
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struct dpu_hw_intf_ops {
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void (*setup_timing_gen)(struct dpu_hw_intf *intf,
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@ -68,6 +70,10 @@ struct dpu_hw_intf_ops {
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struct intf_status *status);
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u32 (*get_line_count)(struct dpu_hw_intf *intf);
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void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
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bool enable,
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const enum dpu_pingpong pp);
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};
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struct dpu_hw_intf {
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