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ath9k: move hw code to its own module
hw code for Atheros 802.11n hardware is commmon between different chipsets. This moves this code into a separate module, the next expected user of this code will be the ath9k_htc module. The ath9k/ dir is now selected by ATH9K_HW, an option which gets selected by either ath9k or ath9k_htc, but remains invisible for user menuconfig configuration. If either ath9k or ath9k_htc will be compiled into the kernel ath9k_hw will also be compiled in. Cc: Jouni Malinen <jouni.malinen@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
475a6e4d39
commit
7322fd1929
@ -1,5 +1,5 @@
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obj-$(CONFIG_ATH5K) += ath5k/
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obj-$(CONFIG_ATH9K) += ath9k/
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obj-$(CONFIG_ATH9K_HW) += ath9k/
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obj-$(CONFIG_AR9170_USB) += ar9170/
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obj-$(CONFIG_ATH_COMMON) += ath.o
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@ -1,6 +1,10 @@
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config ATH9K_HW
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tristate
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config ATH9K
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tristate "Atheros 802.11n wireless cards support"
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depends on PCI && MAC80211 && WLAN_80211
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select ATH9K_HW
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select MAC80211_LEDS
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select LEDS_CLASS
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select NEW_LEDS
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@ -1,16 +1,4 @@
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ATH9K_HW += hw.o \
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eeprom.o \
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eeprom_def.o \
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eeprom_4k.o \
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eeprom_9287.o \
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calib.o \
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ani.o \
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phy.o \
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btcoex.o \
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mac.o \
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ath9k-y += $(ATH9K_HW) \
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beacon.o \
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ath9k-y += beacon.o \
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main.o \
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recv.o \
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xmit.o \
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@ -22,3 +10,16 @@ ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
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ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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ath9k_hw-y:= hw.o \
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eeprom.o \
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eeprom_def.o \
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eeprom_4k.o \
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eeprom_9287.o \
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calib.o \
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ani.o \
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phy.o \
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btcoex.o \
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mac.o \
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obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
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@ -629,6 +629,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
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}
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}
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}
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EXPORT_SYMBOL(ath9k_hw_ani_monitor);
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void ath9k_enable_mib_counters(struct ath_hw *ah)
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{
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@ -756,6 +757,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah)
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ath9k_ani_restart(ah);
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}
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}
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EXPORT_SYMBOL(ath9k_hw_procmibevent);
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void ath9k_hw_ani_setup(struct ath_hw *ah)
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{
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@ -95,6 +95,7 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
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for (i = 0; i < 32; i++)
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ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
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}
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EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
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void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
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{
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@ -116,6 +117,7 @@ void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
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/* Configure the desired gpio port for input */
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
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void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
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{
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@ -141,6 +143,7 @@ void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
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static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
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{
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@ -160,6 +163,7 @@ void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
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btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
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SM(wlan_weight, AR_BTCOEX_WL_WGHT);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
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static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
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{
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@ -201,6 +205,7 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah)
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ah->btcoex_hw.enabled = true;
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
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void ath9k_hw_btcoex_disable(struct ath_hw *ah)
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{
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@ -219,3 +224,4 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah)
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ah->btcoex_hw.enabled = false;
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
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@ -594,6 +594,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
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return false;
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}
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EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
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void ath9k_hw_start_nfcal(struct ath_hw *ah)
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{
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@ -746,6 +747,7 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
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return nf;
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}
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EXPORT_SYMBOL(ath9k_hw_getchan_noise);
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static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
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{
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@ -1066,6 +1068,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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return iscaldone;
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}
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EXPORT_SYMBOL(ath9k_hw_calibrate);
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static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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@ -33,6 +33,23 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
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static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
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static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
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MODULE_AUTHOR("Atheros Communications");
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MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
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MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
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MODULE_LICENSE("Dual BSD/GPL");
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static int __init ath9k_init(void)
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{
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return 0;
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}
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module_init(ath9k_init);
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static void __exit ath9k_exit(void)
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{
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return;
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}
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module_exit(ath9k_exit);
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/********************/
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/* Helper Functions */
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/********************/
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@ -99,6 +116,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
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{
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@ -186,6 +204,7 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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return txTime;
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}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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struct ath9k_channel *chan,
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@ -402,6 +421,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
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if (num_possible_cpus() > 1)
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ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}
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EXPORT_SYMBOL(ath9k_hw_init);
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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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@ -1223,6 +1243,7 @@ void ath9k_hw_detach(struct ath_hw *ah)
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kfree(ah);
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ah = NULL;
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}
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EXPORT_SYMBOL(ath9k_hw_detach);
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/*******/
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/* INI */
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@ -2561,6 +2582,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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return 0;
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}
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EXPORT_SYMBOL(ath9k_hw_reset);
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/************************/
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/* Key Cache Management */
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@ -2599,6 +2621,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_keyreset);
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bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
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{
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@ -2627,6 +2650,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_keysetmac);
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bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
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const struct ath9k_keyval *k,
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@ -2825,6 +2849,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
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bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
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{
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@ -2835,6 +2860,7 @@ bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
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}
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return false;
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}
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EXPORT_SYMBOL(ath9k_hw_keyisvalid);
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/******************************/
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/* Power Management (Chipset) */
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@ -2951,6 +2977,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
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return status;
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}
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EXPORT_SYMBOL(ath9k_hw_setpower);
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/*
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* Helper for ASPM support.
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@ -3083,6 +3110,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
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}
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}
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}
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EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
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/**********************/
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/* Interrupt Handling */
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@ -3106,6 +3134,7 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
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return false;
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}
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EXPORT_SYMBOL(ath9k_hw_intrpend);
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bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
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{
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@ -3258,6 +3287,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_getisr);
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enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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{
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@ -3365,6 +3395,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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return omask;
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}
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EXPORT_SYMBOL(ath9k_hw_set_interrupts);
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/*******************/
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/* Beacon Handling */
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@ -3426,6 +3457,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
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REG_SET_BIT(ah, AR_TIMER_MODE, flags);
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}
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EXPORT_SYMBOL(ath9k_hw_beaconinit);
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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const struct ath9k_beacon_state *bs)
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@ -3489,6 +3521,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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/* TSF Out of Range Threshold */
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REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
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}
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EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
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/*******************/
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/* HW Capabilities */
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@ -3756,6 +3789,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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return false;
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}
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}
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EXPORT_SYMBOL(ath9k_hw_getcapability);
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bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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u32 capability, u32 setting, int *status)
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@ -3789,6 +3823,7 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
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return false;
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}
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}
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EXPORT_SYMBOL(ath9k_hw_setcapability);
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/****************************/
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/* GPIO / RFKILL / Antennae */
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@ -3835,6 +3870,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
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(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
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(AR_GPIO_OE_OUT_DRV << gpio_shift));
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}
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EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
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u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
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{
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@ -3853,6 +3889,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
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else
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return MS_REG_READ(AR, gpio) != 0;
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}
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EXPORT_SYMBOL(ath9k_hw_gpio_get);
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void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
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u32 ah_signal_type)
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@ -3868,22 +3905,26 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
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(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
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(AR_GPIO_OE_OUT_DRV << gpio_shift));
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}
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EXPORT_SYMBOL(ath9k_hw_cfg_output);
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void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
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{
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REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
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AR_GPIO_BIT(gpio));
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}
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EXPORT_SYMBOL(ath9k_hw_set_gpio);
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u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
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{
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return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
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}
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EXPORT_SYMBOL(ath9k_hw_getdefantenna);
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void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
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{
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REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
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}
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EXPORT_SYMBOL(ath9k_hw_setantenna);
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bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
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enum ath9k_ant_setting settings,
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@ -3946,6 +3987,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
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return bits;
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}
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EXPORT_SYMBOL(ath9k_hw_getrxfilter);
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void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
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{
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@ -3967,6 +4009,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
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REG_WRITE(ah, AR_RXCFG,
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REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
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}
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EXPORT_SYMBOL(ath9k_hw_setrxfilter);
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bool ath9k_hw_phy_disable(struct ath_hw *ah)
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{
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@ -3976,6 +4019,7 @@ bool ath9k_hw_phy_disable(struct ath_hw *ah)
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ath9k_hw_init_pll(ah, NULL);
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_phy_disable);
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bool ath9k_hw_disable(struct ath_hw *ah)
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{
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@ -3988,6 +4032,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
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ath9k_hw_init_pll(ah, NULL);
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return true;
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}
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EXPORT_SYMBOL(ath9k_hw_disable);
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void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
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{
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@ -4004,22 +4049,26 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
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min((u32) MAX_RATE_POWER,
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(u32) regulatory->power_limit));
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}
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EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
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void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
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{
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memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
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}
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EXPORT_SYMBOL(ath9k_hw_setmac);
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void ath9k_hw_setopmode(struct ath_hw *ah)
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{
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ath9k_hw_set_operating_mode(ah, ah->opmode);
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}
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EXPORT_SYMBOL(ath9k_hw_setopmode);
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void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
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{
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REG_WRITE(ah, AR_MCAST_FIL0, filter0);
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REG_WRITE(ah, AR_MCAST_FIL1, filter1);
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}
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EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
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void ath9k_hw_write_associd(struct ath_hw *ah)
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{
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@ -4029,6 +4078,7 @@ void ath9k_hw_write_associd(struct ath_hw *ah)
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REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
|
||||
((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_write_associd);
|
||||
|
||||
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
|
||||
{
|
||||
@ -4039,12 +4089,14 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah)
|
||||
|
||||
return tsf;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gettsf64);
|
||||
|
||||
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
|
||||
{
|
||||
REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
|
||||
REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_settsf64);
|
||||
|
||||
void ath9k_hw_reset_tsf(struct ath_hw *ah)
|
||||
{
|
||||
@ -4055,6 +4107,7 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
|
||||
|
||||
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
|
||||
|
||||
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
||||
{
|
||||
@ -4063,6 +4116,7 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
||||
else
|
||||
ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
|
||||
|
||||
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
||||
{
|
||||
@ -4077,6 +4131,7 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_setslottime);
|
||||
|
||||
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
|
||||
{
|
||||
@ -4140,6 +4195,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
|
||||
{
|
||||
return REG_READ(ah, AR_TSF_L32);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gettsf32);
|
||||
|
||||
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
||||
void (*trigger)(void *),
|
||||
@ -4168,6 +4224,7 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
||||
|
||||
return timer;
|
||||
}
|
||||
EXPORT_SYMBOL(ath_gen_timer_alloc);
|
||||
|
||||
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
|
||||
struct ath_gen_timer *timer,
|
||||
@ -4209,6 +4266,7 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
|
||||
(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
|
||||
SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
|
||||
|
||||
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
|
||||
{
|
||||
@ -4230,6 +4288,7 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
|
||||
|
||||
clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
|
||||
|
||||
void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
|
||||
{
|
||||
@ -4239,6 +4298,7 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
|
||||
timer_table->timers[timer->index] = NULL;
|
||||
kfree(timer);
|
||||
}
|
||||
EXPORT_SYMBOL(ath_gen_timer_free);
|
||||
|
||||
/*
|
||||
* Generic Timer Interrupts handling
|
||||
@ -4276,3 +4336,4 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
||||
timer->trigger(timer->arg);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath_gen_timer_isr);
|
||||
|
||||
@ -39,11 +39,13 @@ u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
return REG_READ(ah, AR_QTXDP(q));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gettxbuf);
|
||||
|
||||
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
|
||||
{
|
||||
REG_WRITE(ah, AR_QTXDP(q), txdp);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_puttxbuf);
|
||||
|
||||
void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
@ -51,6 +53,7 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
|
||||
"Enable TXE on queue: %u\n", q);
|
||||
REG_WRITE(ah, AR_Q_TXE, 1 << q);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_txstart);
|
||||
|
||||
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
@ -65,6 +68,7 @@ u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
|
||||
|
||||
return npend;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_numtxpending);
|
||||
|
||||
bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
|
||||
{
|
||||
@ -94,6 +98,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
|
||||
|
||||
return newLevel != curLevel;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
|
||||
|
||||
bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
@ -173,6 +178,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
|
||||
#undef ATH9K_TX_STOP_DMA_TIMEOUT
|
||||
#undef ATH9K_TIME_QUANTUM
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_stoptxdma);
|
||||
|
||||
void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 segLen, bool firstSeg,
|
||||
@ -199,6 +205,7 @@ void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
|
||||
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_filltxdesc);
|
||||
|
||||
void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
|
||||
{
|
||||
@ -210,6 +217,7 @@ void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
|
||||
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
|
||||
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
|
||||
|
||||
int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
|
||||
{
|
||||
@ -285,6 +293,7 @@ int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_txprocdesc);
|
||||
|
||||
void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
|
||||
@ -320,6 +329,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
ads->ds_ctl11 = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
|
||||
|
||||
void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
|
||||
struct ath_desc *lastds,
|
||||
@ -375,6 +385,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
|
||||
last_ads->ds_ctl2 = ads->ds_ctl2;
|
||||
last_ads->ds_ctl3 = ads->ds_ctl3;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
|
||||
|
||||
void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 aggrLen)
|
||||
@ -385,6 +396,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
|
||||
ads->ds_ctl6 &= ~AR_AggrLen;
|
||||
ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
|
||||
|
||||
void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 numDelims)
|
||||
@ -399,6 +411,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
|
||||
ctl6 |= SM(numDelims, AR_PadDelim);
|
||||
ads->ds_ctl6 = ctl6;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
|
||||
|
||||
void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
|
||||
{
|
||||
@ -408,6 +421,7 @@ void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
|
||||
ads->ds_ctl1 &= ~AR_MoreAggr;
|
||||
ads->ds_ctl6 &= ~AR_PadDelim;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
|
||||
|
||||
void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
|
||||
{
|
||||
@ -415,6 +429,7 @@ void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
|
||||
|
||||
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
|
||||
|
||||
void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 burstDuration)
|
||||
@ -424,6 +439,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
|
||||
ads->ds_ctl2 &= ~AR_BurstDur;
|
||||
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
|
||||
|
||||
void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 vmf)
|
||||
@ -441,6 +457,7 @@ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
|
||||
*txqs &= ah->intr_txqs;
|
||||
ah->intr_txqs &= ~(*txqs);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
|
||||
|
||||
bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
|
||||
const struct ath9k_tx_queue_info *qinfo)
|
||||
@ -512,6 +529,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
|
||||
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_set_txq_props);
|
||||
|
||||
bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
|
||||
struct ath9k_tx_queue_info *qinfo)
|
||||
@ -550,6 +568,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
|
||||
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_get_txq_props);
|
||||
|
||||
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
||||
const struct ath9k_tx_queue_info *qinfo)
|
||||
@ -617,6 +636,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
||||
|
||||
return q;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
|
||||
|
||||
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
@ -648,6 +668,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
|
||||
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
|
||||
|
||||
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
|
||||
{
|
||||
@ -805,6 +826,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
|
||||
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_resettxqueue);
|
||||
|
||||
int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 pa, struct ath_desc *nds, u64 tsf)
|
||||
@ -886,6 +908,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
|
||||
|
||||
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
u32 size, u32 flags)
|
||||
@ -901,6 +924,7 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||||
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
|
||||
memset(&(ads->u), 0, sizeof(ads->u));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
|
||||
|
||||
bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
|
||||
{
|
||||
@ -930,16 +954,19 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
|
||||
|
||||
return true;
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_setrxabort);
|
||||
|
||||
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
|
||||
{
|
||||
REG_WRITE(ah, AR_RXDP, rxdp);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_putrxbuf);
|
||||
|
||||
void ath9k_hw_rxena(struct ath_hw *ah)
|
||||
{
|
||||
REG_WRITE(ah, AR_CR, AR_CR_RXE);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_rxena);
|
||||
|
||||
void ath9k_hw_startpcureceive(struct ath_hw *ah)
|
||||
{
|
||||
@ -949,6 +976,7 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah)
|
||||
|
||||
REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_startpcureceive);
|
||||
|
||||
void ath9k_hw_stoppcurecv(struct ath_hw *ah)
|
||||
{
|
||||
@ -956,6 +984,7 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
|
||||
|
||||
ath9k_hw_disable_mib_counters(ah);
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
|
||||
|
||||
bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
|
||||
{
|
||||
@ -988,3 +1017,4 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
|
||||
#undef AH_RX_TIME_QUANTUM
|
||||
#undef AH_RX_STOP_DMA_TIMEOUT
|
||||
}
|
||||
EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user