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pinctrl: renesas: sh7722: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 396 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
aa9c0a767f
commit
72db29175f
@ -1255,14 +1255,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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HPD49, PTB1_OUT, 0, PTB1_IN,
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HPD48, PTB0_OUT, 0, PTB0_IN ))
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},
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{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
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{ PINMUX_CFG_REG_VAR("PCCR", 0xa4050104, 16,
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GROUP(2, -2, 2, 2, 2, 2, -2, 2),
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GROUP(
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0, 0, 0, PTC7_IN,
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0, 0, 0, 0,
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/* RESERVED [2] */
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IOIS16, 0, 0, PTC5_IN,
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HPDQM7, PTC4_OUT, 0, PTC4_IN,
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HPDQM6, PTC3_OUT, 0, PTC3_IN,
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HPDQM5, PTC2_OUT, 0, PTC2_IN,
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0, 0, 0, 0,
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/* RESERVED [2] */
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HPDQM4, PTC0_OUT, 0, PTC0_IN ))
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},
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{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
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@ -1275,13 +1277,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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SDHICMD, PTD1_OUT, 0, PTD1_IN,
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SDHICLK, PTD0_OUT, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
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{ PINMUX_CFG_REG_VAR("PECR", 0xa4050108, 16,
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GROUP(2, 2, 2, 2, -4, 2, 2),
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GROUP(
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A25, PTE7_OUT, 0, PTE7_IN,
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A24, PTE6_OUT, 0, PTE6_IN,
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A23, PTE5_OUT, 0, PTE5_IN,
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A22, PTE4_OUT, 0, PTE4_IN,
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0, 0, 0, 0,
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0, 0, 0, 0,
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/* RESERVED [4] */
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IRQ5, PTE1_OUT, 0, PTE1_IN,
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IRQ4_BS, PTE0_OUT, 0, PTE0_IN ))
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},
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@ -1295,10 +1298,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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SIORXD_SIUBISLD, 0, 0, PTF1_IN,
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SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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AUDSYNC, PTG4_OUT, 0, 0,
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AUDATA3, PTG3_OUT, 0, 0,
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AUDATA2, PTG2_OUT, 0, 0,
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@ -1315,13 +1318,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
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LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN ))
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},
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{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
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{ PINMUX_CFG_REG_VAR("PJCR", 0xa4050110, 16,
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GROUP(2, 2, 2, -6, 2, 2),
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GROUP(
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STATUS0, PTJ7_OUT, 0, 0,
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0, PTJ6_OUT, 0, 0,
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PDSTATUS, PTJ5_OUT, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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/* RESERVED [6] */
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IRQ1, PTJ1_OUT, 0, PTJ1_IN,
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IRQ0, PTJ0_OUT, 0, PTJ0_IN ))
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},
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@ -1375,50 +1378,50 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PTQ1, PTQ1_OUT, 0, 0,
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PTQ0, PTQ0_OUT, 0, PTQ0_IN ))
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},
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{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PRCR", 0xa405011c, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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LCDRD, PTR4_OUT, 0, 0,
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CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
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WAIT, 0, 0, PTR2_IN,
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LCDDCK_LCDWR, PTR1_OUT, 0, 0,
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LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PSCR", 0xa405011e, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN,
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SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
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SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
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SCIF0_RXD, 0, 0, PTS1_IN,
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SCIF0_TXD, PTS0_OUT, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PTCR", 0xa4050140, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN,
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FWE, PTT3_OUT, 0, PTT3_IN,
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FSC, PTT2_OUT, 0, PTT2_IN,
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DREQ0, 0, 0, PTT1_IN,
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FCDE, PTT0_OUT, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PUCR", 0xa4050142, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN,
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NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
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NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
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FRB_VIO_CLK2, 0, 0, PTU1_IN,
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FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN ))
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},
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{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PVCR", 0xa4050144, 16,
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GROUP(-6, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [6] */
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NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN,
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NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
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NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
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@ -1445,9 +1448,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
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LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN ))
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},
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{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PYCR", 0xa405014a, 16,
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GROUP(-4, 2, 2, 2, 2, 2, 2),
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GROUP(
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/* RESERVED [4] */
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KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
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KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN,
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KEYOUT3, PTY3_OUT, 0, PTY3_IN,
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@ -1455,33 +1459,27 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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KEYOUT1, PTY1_OUT, 0, 0,
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KEYOUT0, PTY0_OUT, 0, PTY0_IN ))
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},
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{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
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0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PZCR", 0xa405014c, 16,
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GROUP(-4, 2, 2, 2, 2, 2, -2),
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GROUP(
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/* RESERVED [4] */
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KEYIN4_IRQ7, 0, 0, PTZ5_IN,
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KEYIN3, 0, 0, PTZ4_IN,
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KEYIN2, 0, 0, PTZ3_IN,
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KEYIN1, 0, 0, PTZ2_IN,
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KEYIN0_IRQ6, 0, 0, PTZ1_IN,
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0, 0, 0, 0 ))
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/* RESERVED [2] */ ))
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},
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{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSELA", 0xa405014e, 16,
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GROUP(1, 1, -4, 1, -4, 1, -4),
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GROUP(
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PSA15_KEYIN0, PSA15_IRQ6,
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PSA14_KEYIN4, PSA14_IRQ7,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [4] */
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PSA9_IRQ4, PSA9_BS,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [4] */
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PSA4_IRQ2, PSA4_SDHID2,
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0, 0,
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0, 0,
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0, 0,
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0, 0 ))
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/* RESERVED [4] */ ))
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},
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{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
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PSB15_SIOTXD, PSB15_SIUBOSLD,
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@ -1501,22 +1499,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PSB1_SIUMCKA, PSB1_SIOF1_MCK,
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PSB0_SIUAOSLD, PSB0_SIOF1_TXD ))
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},
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{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSELC", 0xa4050152, 16,
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GROUP(1, 1, 1, 1, 1, -10, 1),
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GROUP(
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PSC15_SIUAISLD, PSC15_SIOF1_RXD,
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PSC14_SIUAOBT, PSC14_SIOF1_SCK,
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PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
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PSC12_SIUAIBT, PSC12_SIOF1_SS1,
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PSC11_SIUAILR, PSC11_SIOF1_SS2,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [10] */
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PSC0_NAF, PSC0_VIO ))
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},
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{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
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@ -1537,61 +1528,45 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0,
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PSD0_LCDD19_LCDD0, PSD0_DV ))
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},
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{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("PSELE", 0xa4050156, 16,
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GROUP(1, 1, 1, 1, 1, -7, 1, 1, 1, 1),
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GROUP(
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PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
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PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
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PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
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PSE12_LCDVSYN2, PSE12_DACK,
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PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [7] */
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PSE3_FLCTL, PSE3_VIO,
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PSE2_NAF2, PSE2_VIO_D10,
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PSE1_NAF1, PSE1_VIO_D9,
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PSE0_NAF0, PSE0_VIO_D8 ))
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},
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{ PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1, GROUP(
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0, 0,
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{ PINMUX_CFG_REG_VAR("HIZCRA", 0xa4050158, 16,
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GROUP(-1, 1, -3, 1, 1, 1, 1, 1, -6),
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GROUP(
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/* RESERVED [1] */
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HIZA14_KEYSC, HIZA14_HIZ,
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0, 0,
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0, 0,
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0, 0,
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/* RESERVED [3] */
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HIZA10_NAF, HIZA10_HIZ,
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HIZA9_VIO, HIZA9_HIZ,
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HIZA8_LCDC, HIZA8_HIZ,
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HIZA7_LCDC, HIZA7_HIZ,
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HIZA6_LCDC, HIZA6_HIZ,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0 ))
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/* RESERVED [6] */ ))
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},
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{ PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("HIZCRB", 0xa405015a, 16,
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GROUP(-11, 1, -2, 1, 1),
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GROUP(
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/* RESERVED [11] */
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HIZB4_SIUA, HIZB4_HIZ,
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0, 0,
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0, 0,
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/* RESERVED [2] */
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HIZB1_VIO, HIZB1_HIZ,
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HIZB0_VIO, HIZB0_HIZ ))
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},
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{ PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1, GROUP(
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{ PINMUX_CFG_REG_VAR("HIZCRC", 0xa405015c, 16,
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GROUP(1, 1, 1, 1, 1, 1, 1, 1, -8),
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GROUP(
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HIZC15_IRQ7, HIZC15_HIZ,
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HIZC14_IRQ6, HIZC14_HIZ,
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HIZC13_IRQ5, HIZC13_HIZ,
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@ -1600,32 +1575,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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HIZC10_IRQ2, HIZC10_HIZ,
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HIZC9_IRQ1, HIZC9_HIZ,
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HIZC8_IRQ0, HIZC8_HIZ,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0 ))
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/* RESERVED [8] */ ))
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},
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{ PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("MSELCRB", 0xa4050182, 16,
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GROUP(-6, 1, 1, -8),
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GROUP(
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/* RESERVED [6] */
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MSELB9_VIO, MSELB9_VIO2,
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MSELB8_RGB, MSELB8_SYS,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0 ))
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/* RESERVED [8] */ ))
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},
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{}
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};
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