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media: qcom: camss: Split testgen, RDI and RX for CSID 170
Split the RAW interface (RDI), the CSID receiver (RX) and test pattern generator (testgen), configurations for CSID on Titan 170 Signed-off-by: Milen Mitkov <quic_mmitkov@quicinc.com> Signed-off-by: Gjorgji Rosikopulos <quic_grosikop@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # sc8280xp/sm8250/sdm845/apq8016 Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> [hverkuil: folded https://lore.kernel.org/linux-media/20240626074730.85-1-quic_grosikop@quicinc.com/ into this patch]
This commit is contained in:
Milen Mitkov
Hans Verkuil
parent
ad458cb90f
commit
729fc005c8
@ -176,128 +176,18 @@
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#define TPG_COLOR_BOX_CFG_MODE 0
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#define TPG_COLOR_BOX_PATTERN_SEL 2
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static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc)
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static void __csid_configure_rx(struct csid_device *csid,
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struct csid_phy_config *phy, int vc)
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{
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struct csid_testgen_config *tg = &csid->testgen;
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u32 val;
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u32 phy_sel = 0;
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u8 lane_cnt = csid->phy.lane_cnt;
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/* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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int val;
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if (!lane_cnt)
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lane_cnt = 4;
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if (!tg->enabled)
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phy_sel = csid->phy.csiphy_id;
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if (enable) {
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/*
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* DT_ID is a two bit bitfield that is concatenated with
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* the four least significant bits of the five bit VC
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* bitfield to generate an internal CID value.
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*
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* CSID_RDI_CFG0(vc)
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* DT_ID : 28:27
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* VC : 26:22
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* DT : 21:16
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*
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* CID : VC 3:0 << 2 | DT_ID 1:0
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*/
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u8 dt_id = vc & 0x03;
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if (tg->enabled) {
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/* configure one DT, infinite frames */
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val = vc << TPG_VC_CFG0_VC_NUM;
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val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
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val |= 0 << TPG_VC_CFG0_NUM_FRAMES;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
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val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;
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val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
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writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
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val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
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val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
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val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
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val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
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val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
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val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
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}
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val = 1 << RDI_CFG0_BYTE_CNTR_EN;
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val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;
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val |= 1 << RDI_CFG0_TIMESTAMP_EN;
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/* note: for non-RDI path, this should be format->decode_format */
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val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
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val |= format->data_type << RDI_CFG0_DATA_TYPE;
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val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
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val |= dt_id << RDI_CFG0_DT_ID;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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/* CSID_TIMESTAMP_STB_POST_IRQ */
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val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;
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writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
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val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));
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val |= 1 << RDI_CFG0_ENABLE;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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}
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if (tg->enabled) {
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val = enable << TPG_CTRL_TEST_EN;
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val |= 1 << TPG_CTRL_FS_PKT_EN;
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val |= 1 << TPG_CTRL_FE_PKT_EN;
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val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;
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val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;
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val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;
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writel_relaxed(val, csid->base + CSID_TPG_CTRL);
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}
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val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
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val |= csid->phy.lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
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val |= phy_sel << CSI2_RX_CFG0_PHY_NUM_SEL;
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val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
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val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
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val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
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@ -305,21 +195,152 @@ static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc)
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val |= 1 << CSI2_RX_CFG1_VC_MODE;
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val |= 1 << CSI2_RX_CFG1_MISR_EN;
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
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}
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static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
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{
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int val;
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if (enable)
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val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
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else
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val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
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writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi));
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}
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static void __csid_configure_testgen(struct csid_device *csid, u8 enable, u8 vc)
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{
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struct csid_testgen_config *tg = &csid->testgen;
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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u8 lane_cnt = csid->phy.lane_cnt;
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u32 val;
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if (!lane_cnt)
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lane_cnt = 4;
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/* configure one DT, infinite frames */
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val = vc << TPG_VC_CFG0_VC_NUM;
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val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
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val |= 0 << TPG_VC_CFG0_NUM_FRAMES;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
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val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;
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val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
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writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
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val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
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val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
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val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
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val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
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val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
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val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
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val = enable << TPG_CTRL_TEST_EN;
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val |= 1 << TPG_CTRL_FS_PKT_EN;
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val |= 1 << TPG_CTRL_FE_PKT_EN;
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val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;
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val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;
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val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;
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writel_relaxed(val, csid->base + CSID_TPG_CTRL);
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}
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static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
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{
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/* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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u32 val;
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/*
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* DT_ID is a two bit bitfield that is concatenated with
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* the four least significant bits of the five bit VC
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* bitfield to generate an internal CID value.
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*
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* CSID_RDI_CFG0(vc)
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* DT_ID : 28:27
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* VC : 26:22
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* DT : 21:16
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*
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* CID : VC 3:0 << 2 | DT_ID 1:0
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*/
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u8 dt_id = vc & 0x03;
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val = 1 << RDI_CFG0_BYTE_CNTR_EN;
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val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;
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val |= 1 << RDI_CFG0_TIMESTAMP_EN;
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/* note: for non-RDI path, this should be format->decode_format */
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val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
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val |= format->data_type << RDI_CFG0_DATA_TYPE;
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val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
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val |= dt_id << RDI_CFG0_DT_ID;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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/* CSID_TIMESTAMP_STB_POST_IRQ */
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val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;
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writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
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val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));
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val |= enable << RDI_CFG0_ENABLE;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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}
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static void csid_configure_stream(struct csid_device *csid, u8 enable)
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{
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struct csid_testgen_config *tg = &csid->testgen;
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u8 i;
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/* Loop through all enabled VCs and configure stream for each */
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for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
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if (csid->phy.en_vc & BIT(i))
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__csid_configure_stream(csid, enable, i);
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if (csid->phy.en_vc & BIT(i)) {
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if (tg->enabled)
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__csid_configure_testgen(csid, enable, i);
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__csid_configure_rdi_stream(csid, enable, i);
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__csid_configure_rx(csid, &csid->phy, i);
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__csid_ctrl_rdi(csid, enable, i);
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}
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}
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static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
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