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arm64: dts: qcom: qcs404: Add sdcc1 node
Add the sdcc1 node and enable it for the QCS404-EVB. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -109,3 +109,67 @@
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};
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};
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};
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&sdcc1 {
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status = "ok";
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mmc-ddr-1_8v;
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_on>;
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pinctrl-1 = <&sdc1_off>;
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};
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&tlmm {
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sdc1_on: sdc1-on {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <16>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <10>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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dreive-strength = <10>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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sdc1_off: sdc1-off {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <2>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <2>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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dreive-strength = <2>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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};
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@ -181,6 +181,23 @@
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reg = <0x01905000 0x20000>;
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};
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sdcc1: sdcc@7804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
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reg-names = "hc_mem", "cmdq_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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blsp1_uart2: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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