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staging: brcm80211: removal of inactive d11 code
Code cleanup. Removed code that was never invoked because the mac core revision supported is always higher than 22. Signed-off-by: Roland Vossen <rvossen@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Reviewed-by: Brett Rudley <brudley@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
aba0586c8a
commit
7234592364
@ -254,9 +254,6 @@ static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
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ASSERT(wlc_hw->clk);
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if (D11REV_LT(wlc_hw->corerev, 17))
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tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
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wlc_bmac_core_phy_clk(wlc_hw, OFF);
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wlc_setxband(wlc_hw, bandunit);
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@ -467,9 +464,6 @@ void wlc_bmac_watchdog(void *arg)
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/* make sure RX dma has buffers */
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dma_rxfill(wlc->hw->di[RX_FIFO]);
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if (D11REV_IS(wlc_hw->corerev, 4)) {
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dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
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}
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wlc_phy_watchdog(wlc_hw->band->pi);
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}
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@ -606,23 +600,11 @@ static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
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*/
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ASSERT(TX_AC_VO_FIFO == 3);
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ASSERT(TX_CTL_FIFO == 3);
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if (D11REV_IS(wlc_hw->corerev, 4)) {
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ASSERT(RX_TXSTATUS_FIFO == 3);
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wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
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DMAREG(wlc_hw, DMA_TX, 3),
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DMAREG(wlc_hw, DMA_RX, 3),
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tune->ntxd, tune->nrxd,
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sizeof(tx_status_t), -1,
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tune->nrxbufpost, 0,
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&wl_msg_level);
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dma_attach_err |= (NULL == wlc_hw->di[3]);
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} else {
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wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
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DMAREG(wlc_hw, DMA_TX, 3),
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NULL, tune->ntxd, 0, 0, -1,
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0, 0, &wl_msg_level);
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dma_attach_err |= (NULL == wlc_hw->di[3]);
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}
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wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
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DMAREG(wlc_hw, DMA_TX, 3),
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NULL, tune->ntxd, 0, 0, -1,
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0, 0, &wl_msg_level);
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dma_attach_err |= (NULL == wlc_hw->di[3]);
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/* Cleaner to leave this as if with AP defined */
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if (dma_attach_err) {
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@ -792,8 +774,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
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wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
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wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
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if (D11REV_LE(wlc_hw->corerev, 4)
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|| (wlc_hw->boardflags & BFL_NOPLLDOWN))
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if (wlc_hw->boardflags & BFL_NOPLLDOWN)
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wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
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if ((wlc_hw->sih->bustype == PCI_BUS)
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@ -879,10 +860,8 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
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wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
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wlc->core->coreidx = si_coreidx(wlc_hw->sih);
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if (D11REV_GE(wlc_hw->corerev, 13)) {
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wlc_hw->machwcap = R_REG(wlc_hw->osh, ®s->machwcap);
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wlc_hw->machwcap_backup = wlc_hw->machwcap;
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}
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wlc_hw->machwcap = R_REG(wlc_hw->osh, ®s->machwcap);
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wlc_hw->machwcap_backup = wlc_hw->machwcap;
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/* init tx fifo size */
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ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
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@ -1288,16 +1267,12 @@ int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
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void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
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{
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if (D11REV_IS(wlc_hw->corerev, 4)) /* no slowclock */
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udelay(5);
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else {
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/* delay before first read of ucode state */
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udelay(40);
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/* delay before first read of ucode state */
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udelay(40);
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/* wait until ucode is no longer asleep */
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SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
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DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
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}
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/* wait until ucode is no longer asleep */
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SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
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DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
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ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
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}
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@ -1362,7 +1337,7 @@ static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
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* then use FCA to verify mac is running fast clock
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*/
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wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
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wakeup_ucode = false;
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if (wlc_hw->up && wakeup_ucode)
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wlc_ucode_wake_override_set(wlc_hw,
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@ -1370,19 +1345,8 @@ static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
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wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
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if (D11REV_LT(wlc_hw->corerev, 11)) {
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/* ucode WAR for old chips */
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if (wlc_hw->forcefastclk)
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wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
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MHF1_FORCEFASTCLK, WLC_BAND_ALL);
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else
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wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
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WLC_BAND_ALL);
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}
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/* check fast clock is available (if core is not in reset) */
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if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
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&& wlc_hw->clk)
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if (wlc_hw->forcefastclk && wlc_hw->clk)
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ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
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/* keep the ucode wake bit on if forcefastclk is on
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@ -1803,8 +1767,6 @@ void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
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wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
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ASSERT(wlc_hw->clk);
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if (D11REV_LT(wlc_hw->corerev, 17))
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tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
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wlc_bmac_phy_reset(wlc_hw);
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wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
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@ -2170,15 +2132,11 @@ bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
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/* may need to take core out of reset first */
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clk = wlc_hw->clk;
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if (!clk) {
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if (D11REV_LE(wlc_hw->corerev, 11))
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resetbits |= SICF_PCLKE;
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/*
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* corerev >= 18, mac no longer enables phyclk automatically when driver accesses
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* phyreg throughput mac. This can be skipped since only mac reg is accessed below
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*/
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if (D11REV_GE(wlc_hw->corerev, 18))
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flags |= SICF_PCLKE;
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flags |= SICF_PCLKE;
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/* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
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if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
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@ -2249,26 +2207,6 @@ void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
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static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
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{
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struct hnddma_pub *di = wlc_hw->di[fifo];
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struct osl_info *osh;
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if (D11REV_LT(wlc_hw->corerev, 12)) {
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bool rxidle = true;
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u16 rcv_frm_cnt = 0;
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osh = wlc_hw->osh;
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W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
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SPINWAIT((!(rxidle = dma_rxidle(di))) &&
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((rcv_frm_cnt =
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R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
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50000);
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if (!rxidle && (rcv_frm_cnt != 0))
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WL_ERROR("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n",
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wlc_hw->unit, __func__, fifo, rcv_frm_cnt);
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mdelay(2);
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}
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return dma_rxreset(di);
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}
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@ -2312,12 +2250,6 @@ void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
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WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
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wlc_hw->unit, __func__, RX_FIFO);
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}
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if (D11REV_IS(wlc_hw->corerev, 4)
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&& wlc_hw->di[RX_TXSTATUS_FIFO]
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&& (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
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WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
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wlc_hw->unit, __func__, RX_TXSTATUS_FIFO);
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}
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}
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/* if noreset, just stop the psm and return */
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if (wlc_hw->noreset) {
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@ -2326,16 +2258,12 @@ void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
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return;
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}
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if (D11REV_LE(wlc_hw->corerev, 11))
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resetbits |= SICF_PCLKE;
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/*
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* corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
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* throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
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* need to enable PHY CLK
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* mac no longer enables phyclk automatically when driver accesses
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* phyreg throughput mac, AND phy_reset is skipped at early stage when
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* band->pi is invalid. need to enable PHY CLK
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*/
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if (D11REV_GE(wlc_hw->corerev, 18))
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flags |= SICF_PCLKE;
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flags |= SICF_PCLKE;
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/* reset the core
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* In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
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@ -2381,9 +2309,6 @@ static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
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u16 txfifo_cmd;
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struct osl_info *osh;
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if (D11REV_LT(wlc_hw->corerev, 9))
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goto exit;
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/* tx fifos start at TXFIFO_START_BLK from the Base address */
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txfifo_startblk = TXFIFO_START_BLK;
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@ -2403,8 +2328,7 @@ static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
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W_REG(osh, ®s->xmtfifocmd, txfifo_cmd);
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W_REG(osh, ®s->xmtfifodef, txfifo_def);
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if (D11REV_GE(wlc_hw->corerev, 16))
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W_REG(osh, ®s->xmtfifodef1, txfifo_def1);
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W_REG(osh, ®s->xmtfifodef1, txfifo_def1);
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W_REG(osh, ®s->xmtfifocmd, txfifo_cmd);
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@ -2454,12 +2378,9 @@ static void wlc_coreinit(struct wlc_info *wlc)
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wlc_ucode_download(wlc_hw);
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/*
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* FIFOSZ fixup
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* 1) core5-9 use ucode 5 to save space since the PSM is the same
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* 2) newer chips, driver wants to controls the fifo allocation
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* FIFOSZ fixup. driver wants to controls the fifo allocation.
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*/
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if (D11REV_GE(wlc_hw->corerev, 4))
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fifosz_fixup = true;
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fifosz_fixup = true;
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/* let the PSM run to the suspended state, set mode to BSS STA */
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W_REG(osh, ®s->macintstatus, -1);
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@ -2536,12 +2457,7 @@ static void wlc_coreinit(struct wlc_info *wlc)
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if (err != 0) {
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WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
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buf[i], wlc_hw->xmtfifo_sz[i], i);
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/* DO NOT ASSERT corerev < 4 even there is a mismatch
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* shmem, since driver don't overwrite those chip and
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* ucode initialize data will be used.
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*/
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if (D11REV_GE(wlc_hw->corerev, 4))
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ASSERT(0);
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ASSERT(0);
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}
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/* make sure we can still talk to the mac */
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@ -2555,8 +2471,6 @@ static void wlc_coreinit(struct wlc_info *wlc)
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/* enable one rx interrupt per received frame */
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W_REG(osh, ®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
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if (D11REV_IS(wlc_hw->corerev, 4))
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W_REG(osh, ®s->intrcvlazy[3], (1 << IRL_FC_SHIFT));
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/* set the station mode (BSS STA) */
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wlc_bmac_mctrl(wlc_hw,
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@ -2571,30 +2485,23 @@ static void wlc_coreinit(struct wlc_info *wlc)
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/* write interrupt mask */
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W_REG(osh, ®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
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if (D11REV_IS(wlc_hw->corerev, 4))
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W_REG(osh, ®s->intctrlregs[RX_TXSTATUS_FIFO].intmask,
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DEF_RXINTMASK);
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/* allow the MAC to control the PHY clock (dynamic on/off) */
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wlc_bmac_macphyclk_set(wlc_hw, ON);
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/* program dynamic clock control fast powerup delay register */
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if (D11REV_GT(wlc_hw->corerev, 4)) {
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wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
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W_REG(osh, ®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
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}
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wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
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W_REG(osh, ®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
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/* tell the ucode the corerev */
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wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
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/* tell the ucode MAC capabilities */
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if (D11REV_GE(wlc_hw->corerev, 13)) {
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wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
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(u16) (wlc_hw->machwcap & 0xffff));
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wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
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(u16) ((wlc_hw->
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machwcap >> 16) & 0xffff));
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}
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wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
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(u16) (wlc_hw->machwcap & 0xffff));
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wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
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(u16) ((wlc_hw->
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machwcap >> 16) & 0xffff));
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/* write retry limits to SCR, this done after PSM init */
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W_REG(osh, ®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
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@ -2608,10 +2515,8 @@ static void wlc_coreinit(struct wlc_info *wlc)
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wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
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wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
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if (D11REV_GE(wlc_hw->corerev, 16)) {
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AND_REG(osh, ®s->ifs_ctl, 0x0FFF);
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W_REG(osh, ®s->ifs_aifsn, EDCF_AIFSN_MIN);
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}
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AND_REG(osh, ®s->ifs_ctl, 0x0FFF);
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W_REG(osh, ®s->ifs_aifsn, EDCF_AIFSN_MIN);
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/* dma initializations */
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wlc->txpend16165war = 0;
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@ -2625,10 +2530,6 @@ static void wlc_coreinit(struct wlc_info *wlc)
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/* init the rx dma engine(s) and post receive buffers */
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dma_rxinit(wlc_hw->di[RX_FIFO]);
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dma_rxfill(wlc_hw->di[RX_FIFO]);
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if (D11REV_IS(wlc_hw->corerev, 4)) {
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dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
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dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
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}
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}
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/* This function is used for changing the tsf frac register
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@ -3160,45 +3061,12 @@ static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
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/* MI_DMAINT is indication of non-zero intstatus */
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if (macintstatus & MI_DMAINT) {
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if (D11REV_IS(wlc_hw->corerev, 4)) {
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intstatus_rxfifo =
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R_REG(osh, ®s->intctrlregs[RX_FIFO].intstatus);
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intstatus_txsfifo =
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R_REG(osh,
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®s->intctrlregs[RX_TXSTATUS_FIFO].
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intstatus);
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WL_TRACE("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n",
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wlc_hw->unit,
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intstatus_rxfifo, intstatus_txsfifo);
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/* defer unsolicited interrupt hints */
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intstatus_rxfifo &= DEF_RXINTMASK;
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intstatus_txsfifo &= DEF_RXINTMASK;
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/* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
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/* clear interrupt hints */
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||||
if (intstatus_rxfifo)
|
||||
W_REG(osh,
|
||||
®s->intctrlregs[RX_FIFO].intstatus,
|
||||
intstatus_rxfifo);
|
||||
else
|
||||
macintstatus &= ~MI_DMAINT;
|
||||
|
||||
/* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
|
||||
if (intstatus_txsfifo) {
|
||||
W_REG(osh,
|
||||
®s->intctrlregs[RX_TXSTATUS_FIFO].
|
||||
intstatus, intstatus_txsfifo);
|
||||
macintstatus |= MI_TFS;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
|
||||
* If MI_DMAINT is set, assume it is set and clear the interrupt.
|
||||
*/
|
||||
W_REG(osh, ®s->intctrlregs[RX_FIFO].intstatus,
|
||||
DEF_RXINTMASK);
|
||||
}
|
||||
/*
|
||||
* only fifo interrupt enabled is I_RI in RX_FIFO. If
|
||||
* MI_DMAINT is set, assume it is set and clear the interrupt.
|
||||
*/
|
||||
W_REG(osh, ®s->intctrlregs[RX_FIFO].intstatus,
|
||||
DEF_RXINTMASK);
|
||||
}
|
||||
|
||||
return macintstatus;
|
||||
@ -3324,14 +3192,7 @@ wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
|
||||
|
||||
WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
|
||||
|
||||
if (D11REV_IS(wlc_hw->corerev, 4)) {
|
||||
/* to retire soon */
|
||||
*fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
|
||||
|
||||
if (*fatal)
|
||||
return 0;
|
||||
} else {
|
||||
/* corerev >= 5 */
|
||||
{
|
||||
d11regs_t *regs;
|
||||
struct osl_info *osh;
|
||||
tx_status_t txstatus, *txs;
|
||||
@ -3624,41 +3485,6 @@ bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
|
||||
(void)R_REG(osh, ®s->objaddr);
|
||||
W_REG(osh, ®s->objdata, w);
|
||||
|
||||
if (D11REV_LT(wlc_hw->corerev, 11)) {
|
||||
/* if 32 bit writes are split into 16 bit writes, are they in the correct order
|
||||
* for our interface, low to high
|
||||
*/
|
||||
reg16 = (volatile u16 *)®s->tsf_cfpstart;
|
||||
|
||||
/* write the CFPStart register low half explicitly, starting a buffered write */
|
||||
W_REG(osh, reg16, 0xAAAA);
|
||||
|
||||
/* Write a 32 bit value to CFPStart to test the 16 bit split order.
|
||||
* If the low 16 bits are written first, followed by the high 16 bits then the
|
||||
* 32 bit value 0xCCCCBBBB should end up in the register.
|
||||
* If the order is reversed, then the write to the high half will trigger a buffered
|
||||
* write of 0xCCCCAAAA.
|
||||
* If the bus is 32 bits, then this is not much of a test, and the reg should
|
||||
* have the correct value 0xCCCCBBBB.
|
||||
*/
|
||||
W_REG(osh, ®s->tsf_cfpstart, 0xCCCCBBBB);
|
||||
|
||||
/* verify with the 16 bit registers that have no side effects */
|
||||
val = R_REG(osh, ®s->tsf_cfpstrt_l);
|
||||
if (val != (uint) 0xBBBB) {
|
||||
WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected 0x%x\n",
|
||||
wlc_hw->unit, val, 0xBBBB);
|
||||
return false;
|
||||
}
|
||||
val = R_REG(osh, ®s->tsf_cfpstrt_h);
|
||||
if (val != (uint) 0xCCCC) {
|
||||
WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected 0x%x\n",
|
||||
wlc_hw->unit, val, 0xCCCC);
|
||||
return false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* clear CFPStart */
|
||||
W_REG(osh, ®s->tsf_cfpstart, 0);
|
||||
|
||||
@ -3689,9 +3515,6 @@ void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
|
||||
regs = wlc_hw->regs;
|
||||
osh = wlc_hw->osh;
|
||||
|
||||
if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
|
||||
return;
|
||||
|
||||
if (on) {
|
||||
if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
|
||||
OR_REG(osh, ®s->clk_ctl_st,
|
||||
@ -3813,8 +3636,6 @@ static void wlc_flushqueues(struct wlc_info *wlc)
|
||||
|
||||
/* free any posted rx packets */
|
||||
dma_rxreclaim(wlc_hw->di[RX_FIFO]);
|
||||
if (D11REV_IS(wlc_hw->corerev, 4))
|
||||
dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
|
||||
}
|
||||
|
||||
u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
|
||||
|
@ -45,11 +45,10 @@ struct wlc_bsscfg;
|
||||
#define WLC_MAX_WSEC_HW_KEYS(wlc) WSEC_MAX_RCMTA_KEYS
|
||||
|
||||
/* Max # of hardware TKIP MIC keys supported */
|
||||
#define WLC_MAX_TKMIC_HW_KEYS(wlc) ((D11REV_GE((wlc)->pub->corerev, 13)) ? \
|
||||
WSEC_MAX_TKMIC_ENGINE_KEYS : 0)
|
||||
#define WLC_MAX_TKMIC_HW_KEYS(wlc) (WSEC_MAX_TKMIC_ENGINE_KEYS)
|
||||
|
||||
#define WSEC_HW_TKMIC_KEY(wlc, key, bsscfg) \
|
||||
(((D11REV_GE((wlc)->pub->corerev, 13)) && ((wlc)->machwcap & MCAP_TKIPMIC)) && \
|
||||
((((wlc)->machwcap & MCAP_TKIPMIC)) && \
|
||||
(key) && ((key)->algo == CRYPTO_ALGO_TKIP) && \
|
||||
!WSEC_SOFTKEY(wlc, key, bsscfg) && \
|
||||
WSEC_KEY_INDEX(wlc, key) >= WLC_DEFAULT_KEYS && \
|
||||
|
@ -457,7 +457,7 @@ void wlc_init(struct wlc_info *wlc)
|
||||
wlc_bmac_init(wlc->hw, chanspec, mute);
|
||||
|
||||
wlc->seckeys = wlc_bmac_read_shm(wlc->hw, M_SECRXKEYS_PTR) * 2;
|
||||
if (D11REV_GE(wlc->pub->corerev, 15) && (wlc->machwcap & MCAP_TKIPMIC))
|
||||
if (wlc->machwcap & MCAP_TKIPMIC)
|
||||
wlc->tkmickeys =
|
||||
wlc_bmac_read_shm(wlc->hw, M_TKMICKEYS_PTR) * 2;
|
||||
|
||||
@ -547,8 +547,7 @@ void wlc_init(struct wlc_info *wlc)
|
||||
wlc->tx_suspended = false;
|
||||
|
||||
/* enable the RF Disable Delay timer */
|
||||
if (D11REV_GE(wlc->pub->corerev, 10))
|
||||
W_REG(wlc->osh, &wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
|
||||
W_REG(wlc->osh, &wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
|
||||
|
||||
/* initialize mpc delay */
|
||||
wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
|
||||
@ -3486,15 +3485,8 @@ _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
|
||||
break;
|
||||
}
|
||||
|
||||
/* 4322 supports antdiv in phy, no need to set it to ucode */
|
||||
if (WLCISNPHY(wlc->band)
|
||||
&& D11REV_IS(wlc->pub->corerev, 16)) {
|
||||
WL_ERROR("wl%d: can't set ucantdiv for 4322\n",
|
||||
wlc->pub->unit);
|
||||
bcmerror = BCME_UNSUPPORTED;
|
||||
} else
|
||||
wlc_mhf(wlc, MHF1, MHF1_ANTDIV,
|
||||
(val ? MHF1_ANTDIV : 0), WLC_BAND_AUTO);
|
||||
wlc_mhf(wlc, MHF1, MHF1_ANTDIV,
|
||||
(val ? MHF1_ANTDIV : 0), WLC_BAND_AUTO);
|
||||
break;
|
||||
}
|
||||
#endif /* defined(BCMDBG) */
|
||||
@ -6162,16 +6154,13 @@ wlc_d11hdrs_mac80211(struct wlc_info *wlc, struct ieee80211_hw *hw,
|
||||
*/
|
||||
txh->TxStatus = htol16(status);
|
||||
|
||||
if (D11REV_GE(wlc->pub->corerev, 16)) {
|
||||
/* extra fields for ucode AMPDU aggregation, the new fields are added to
|
||||
* the END of previous structure so that it's compatible in driver.
|
||||
* In old rev ucode, these fields should be ignored
|
||||
*/
|
||||
txh->MaxNMpdus = htol16(0);
|
||||
txh->MaxABytes_MRT = htol16(0);
|
||||
txh->MaxABytes_FBR = htol16(0);
|
||||
txh->MinMBytes = htol16(0);
|
||||
}
|
||||
/* extra fields for ucode AMPDU aggregation, the new fields are added to
|
||||
* the END of previous structure so that it's compatible in driver.
|
||||
*/
|
||||
txh->MaxNMpdus = htol16(0);
|
||||
txh->MaxABytes_MRT = htol16(0);
|
||||
txh->MaxABytes_FBR = htol16(0);
|
||||
txh->MinMBytes = htol16(0);
|
||||
|
||||
/* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, furnish d11txh_t */
|
||||
/* RTS PLCP header and RTS frame */
|
||||
@ -6597,28 +6586,7 @@ static void *wlc_15420war(struct wlc_info *wlc, uint queue)
|
||||
|
||||
ASSERT(queue < NFIFO);
|
||||
|
||||
if ((D11REV_IS(wlc->pub->corerev, 4))
|
||||
|| (D11REV_GT(wlc->pub->corerev, 6)))
|
||||
return NULL;
|
||||
|
||||
di = wlc->hw->di[queue];
|
||||
ASSERT(di != NULL);
|
||||
|
||||
/* get next packet, ignoring XmtStatus.Curr */
|
||||
p = dma_getnexttxp(di, HNDDMA_RANGE_ALL);
|
||||
|
||||
/* sw block tx dma */
|
||||
dma_txblock(di);
|
||||
|
||||
/* if tx ring is now empty, reset and re-init the tx dma channel */
|
||||
if (dma_txactive(wlc->hw->di[queue]) == 0) {
|
||||
wlc->pub->_cnt->txdmawar++;
|
||||
if (!dma_txreset(di))
|
||||
WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
|
||||
wlc->pub->unit, __func__, queue);
|
||||
dma_txinit(di);
|
||||
}
|
||||
return p;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void wlc_war16165(struct wlc_info *wlc, bool tx)
|
||||
|
Loading…
Reference in New Issue
Block a user