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clk: sunxi-ng: div: Add support for fixed post-divider
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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@ -21,10 +21,18 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
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{
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struct ccu_div *cd = data;
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return divider_round_rate_parent(&cd->common.hw, parent,
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if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate *= cd->fixed_post_div;
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rate = divider_round_rate_parent(&cd->common.hw, parent,
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rate, parent_rate,
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cd->div.table, cd->div.width,
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cd->div.flags);
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if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= cd->fixed_post_div;
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return rate;
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}
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static void ccu_div_disable(struct clk_hw *hw)
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@ -62,8 +70,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
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parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
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parent_rate);
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return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
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cd->div.flags);
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val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
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cd->div.flags);
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if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
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val /= cd->fixed_post_div;
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return val;
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}
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static int ccu_div_determine_rate(struct clk_hw *hw,
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@ -86,6 +99,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
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parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
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parent_rate);
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if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate *= cd->fixed_post_div;
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val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
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cd->div.flags);
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@ -86,9 +86,10 @@ struct ccu_div_internal {
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struct ccu_div {
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u32 enable;
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struct ccu_div_internal div;
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struct ccu_div_internal div;
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struct ccu_mux_internal mux;
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struct ccu_common common;
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unsigned int fixed_post_div;
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};
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#define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
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