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agp/intel: Fix missed cached memory flags setting in i965_write_entry()

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This fixes regression from a6963596a1,
that missed to set cached memory type in GTT entry.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-12-14 11:29:23 +00:00
parent 63abf3edaf
commit 71f4566084
1 changed files with 9 additions and 2 deletions
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11
drivers/char/agp/intel-gtt.c
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@ -1192,12 +1192,19 @@ static void i9xx_chipset_flush(void)
writel(1, intel_private.i9xx_flush_page);
}
static void i965_write_entry(dma_addr_t addr, unsigned int entry,
static void i965_write_entry(dma_addr_t addr,
unsigned int entry,
unsigned int flags)
{
u32 pte_flags;
pte_flags = I810_PTE_VALID;
if (flags == AGP_USER_CACHED_MEMORY)
pte_flags |= I830_PTE_SYSTEM_CACHED;
/* Shift high bits down */
addr |= (addr >> 28) & 0xf0;
writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
writel(addr | pte_flags, intel_private.gtt + entry);
}
static bool gen6_check_flags(unsigned int flags)