mirror of
https://github.com/torvalds/linux.git
synced 2024-12-06 11:01:43 +00:00
Merge branch 'bnxt_en-RTC'
Michael Chan says: ==================== bnxt_en: Add RTC mode for PTP This series adds Real Time Clock (RTC) mode for PTP timestamping. In RTC mode, the 64-bit time value is programmed into the NIC's PTP hardware clock (PHC). Prior to this, the PHC is running as a free counter. For example, in multi-function environment, we need to run PTP in RTC mode. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
71f390f57c
@ -233,6 +233,7 @@ static const u16 bnxt_async_events_arr[] = {
|
||||
ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
|
||||
ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP,
|
||||
ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT,
|
||||
ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE,
|
||||
};
|
||||
|
||||
static struct workqueue_struct *bnxt_pf_wq;
|
||||
@ -2079,6 +2080,16 @@ static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2)
|
||||
(BNXT_EVENT_RING_TYPE(data2) == \
|
||||
ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
|
||||
|
||||
#define BNXT_EVENT_PHC_EVENT_TYPE(data1) \
|
||||
(((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\
|
||||
ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT)
|
||||
|
||||
#define BNXT_EVENT_PHC_RTC_UPDATE(data1) \
|
||||
(((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\
|
||||
ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT)
|
||||
|
||||
#define BNXT_PHC_BITS 48
|
||||
|
||||
static int bnxt_async_event_process(struct bnxt *bp,
|
||||
struct hwrm_async_event_cmpl *cmpl)
|
||||
{
|
||||
@ -2258,6 +2269,24 @@ static int bnxt_async_event_process(struct bnxt *bp,
|
||||
bnxt_event_error_report(bp, data1, data2);
|
||||
goto async_event_process_exit;
|
||||
}
|
||||
case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: {
|
||||
switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) {
|
||||
case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE:
|
||||
if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
u64 ns;
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
bnxt_ptp_update_current_time(bp);
|
||||
ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) <<
|
||||
BNXT_PHC_BITS) | ptp->current_time);
|
||||
bnxt_ptp_rtc_timecounter_init(ptp, ns);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
}
|
||||
break;
|
||||
}
|
||||
goto async_event_process_exit;
|
||||
}
|
||||
case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: {
|
||||
u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
|
||||
|
||||
@ -7414,6 +7443,7 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
|
||||
struct hwrm_port_mac_ptp_qcfg_output *resp;
|
||||
struct hwrm_port_mac_ptp_qcfg_input *req;
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
bool phc_cfg;
|
||||
u8 flags;
|
||||
int rc;
|
||||
|
||||
@ -7456,7 +7486,8 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
|
||||
rc = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
rc = bnxt_ptp_init(bp);
|
||||
phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0;
|
||||
rc = bnxt_ptp_init(bp, phc_cfg);
|
||||
if (rc)
|
||||
netdev_warn(bp->dev, "PTP initialization failed.\n");
|
||||
exit:
|
||||
@ -7514,6 +7545,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
|
||||
bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
|
||||
if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED))
|
||||
bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
|
||||
if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED)
|
||||
bp->fw_cap |= BNXT_FW_CAP_PTP_RTC;
|
||||
if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT))
|
||||
bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;
|
||||
if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED))
|
||||
@ -10288,6 +10321,7 @@ static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
|
||||
/* VF-reps may need to be re-opened after the PF is re-opened */
|
||||
if (BNXT_PF(bp))
|
||||
bnxt_vf_reps_open(bp);
|
||||
bnxt_ptp_init_rtc(bp, true);
|
||||
return 0;
|
||||
|
||||
open_err_irq:
|
||||
|
@ -1957,6 +1957,7 @@ struct bnxt {
|
||||
#define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
|
||||
#define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
|
||||
#define BNXT_FW_CAP_HOT_RESET 0x00200000
|
||||
#define BNXT_FW_CAP_PTP_RTC 0x00400000
|
||||
#define BNXT_FW_CAP_VLAN_RX_STRIP 0x01000000
|
||||
#define BNXT_FW_CAP_VLAN_TX_INSERT 0x02000000
|
||||
#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED 0x04000000
|
||||
|
@ -369,6 +369,12 @@ struct cmd_nums {
|
||||
#define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL
|
||||
#define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL
|
||||
#define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL
|
||||
#define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL
|
||||
#define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL
|
||||
#define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL
|
||||
#define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL
|
||||
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL
|
||||
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL
|
||||
#define HWRM_SELFTEST_QLIST 0x200UL
|
||||
#define HWRM_SELFTEST_EXEC 0x201UL
|
||||
#define HWRM_SELFTEST_IRQ 0x202UL
|
||||
@ -390,6 +396,9 @@ struct cmd_nums {
|
||||
#define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL
|
||||
#define HWRM_MFG_PRVSN_GET_STATE 0x213UL
|
||||
#define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL
|
||||
#define HWRM_MFG_PSOC_QSTATUS 0x215UL
|
||||
#define HWRM_MFG_SELFTEST_QLIST 0x216UL
|
||||
#define HWRM_MFG_SELFTEST_EXEC 0x217UL
|
||||
#define HWRM_TF 0x2bcUL
|
||||
#define HWRM_TF_VERSION_GET 0x2bdUL
|
||||
#define HWRM_TF_SESSION_OPEN 0x2c6UL
|
||||
@ -532,8 +541,8 @@ struct hwrm_err_output {
|
||||
#define HWRM_VERSION_MAJOR 1
|
||||
#define HWRM_VERSION_MINOR 10
|
||||
#define HWRM_VERSION_UPDATE 2
|
||||
#define HWRM_VERSION_RSVD 63
|
||||
#define HWRM_VERSION_STR "1.10.2.63"
|
||||
#define HWRM_VERSION_RSVD 73
|
||||
#define HWRM_VERSION_STR "1.10.2.73"
|
||||
|
||||
/* hwrm_ver_get_input (size:192b/24B) */
|
||||
struct hwrm_ver_get_input {
|
||||
@ -757,10 +766,11 @@ struct hwrm_async_event_cmpl {
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x47UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
|
||||
@ -1112,34 +1122,37 @@ struct hwrm_async_event_cmpl_echo_request {
|
||||
__le32 event_data1;
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_phc_master {
|
||||
/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_phc_update {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
|
||||
__le32 event_data2;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL
|
||||
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
|
||||
@ -1330,6 +1343,30 @@ struct hwrm_async_event_cmpl_error_report_nvm {
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
|
||||
};
|
||||
|
||||
/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
|
||||
struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
|
||||
__le16 type;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
|
||||
__le16 event_id;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
|
||||
__le32 event_data2;
|
||||
u8 opaque_v;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
|
||||
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
|
||||
};
|
||||
|
||||
/* hwrm_func_reset_input (size:192b/24B) */
|
||||
struct hwrm_func_reset_input {
|
||||
__le16 req_type;
|
||||
@ -1589,6 +1626,10 @@ struct hwrm_func_qcaps_output {
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL
|
||||
u8 max_schqs;
|
||||
u8 mpc_chnls_cap;
|
||||
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
|
||||
@ -2455,7 +2496,7 @@ struct hwrm_func_backing_store_qcaps_output {
|
||||
__le16 rkc_entry_size;
|
||||
__le32 tkc_max_entries;
|
||||
__le32 rkc_max_entries;
|
||||
u8 rsvd[7];
|
||||
u8 rsvd1[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -3164,7 +3205,7 @@ struct hwrm_func_ptp_pin_cfg_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_cfg_input (size:320b/40B) */
|
||||
/* hwrm_func_ptp_cfg_input (size:384b/48B) */
|
||||
struct hwrm_func_ptp_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -3178,6 +3219,7 @@ struct hwrm_func_ptp_cfg_input {
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL
|
||||
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL
|
||||
u8 ptp_pps_event;
|
||||
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL
|
||||
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL
|
||||
@ -3204,6 +3246,7 @@ struct hwrm_func_ptp_cfg_input {
|
||||
__le32 ptp_freq_adj_ext_up;
|
||||
__le32 ptp_freq_adj_ext_phase_lower;
|
||||
__le32 ptp_freq_adj_ext_phase_upper;
|
||||
__le64 ptp_set_time;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_cfg_output (size:128b/16B) */
|
||||
@ -3243,6 +3286,308 @@ struct hwrm_func_ptp_ts_query_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
|
||||
struct hwrm_func_ptp_ext_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 enables;
|
||||
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL
|
||||
__le16 phc_master_fid;
|
||||
__le16 phc_sec_fid;
|
||||
u8 phc_sec_mode;
|
||||
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL
|
||||
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY
|
||||
u8 unused_0;
|
||||
__le32 failover_timer;
|
||||
u8 unused_1[4];
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
|
||||
struct hwrm_func_ptp_ext_cfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 unused_0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
|
||||
struct hwrm_func_ptp_ext_qcfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
u8 unused_0[8];
|
||||
};
|
||||
|
||||
/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
|
||||
struct hwrm_func_ptp_ext_qcfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le16 phc_master_fid;
|
||||
__le16 phc_sec_fid;
|
||||
__le16 phc_active_fid0;
|
||||
__le16 phc_active_fid1;
|
||||
__le32 last_failover_event;
|
||||
__le16 from_fid;
|
||||
__le16 to_fid;
|
||||
u8 unused_0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
|
||||
struct hwrm_func_backing_store_cfg_v2_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 type;
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
|
||||
__le16 instance;
|
||||
__le32 flags;
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL
|
||||
__le64 page_dir;
|
||||
__le32 num_entries;
|
||||
__le16 entry_size;
|
||||
u8 page_size_pbl_level;
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4)
|
||||
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G
|
||||
u8 subtype_valid_cnt;
|
||||
__le32 split_entry_0;
|
||||
__le32 split_entry_1;
|
||||
__le32 split_entry_2;
|
||||
__le32 split_entry_3;
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
|
||||
struct hwrm_func_backing_store_cfg_v2_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 rsvd0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
|
||||
struct hwrm_func_backing_store_qcfg_v2_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 type;
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
|
||||
__le16 instance;
|
||||
u8 rsvd[4];
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
|
||||
struct hwrm_func_backing_store_qcfg_v2_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le16 type;
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID
|
||||
__le16 instance;
|
||||
__le32 flags;
|
||||
__le64 page_dir;
|
||||
__le32 num_entries;
|
||||
u8 page_size_pbl_level;
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4)
|
||||
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G
|
||||
u8 subtype_valid_cnt;
|
||||
u8 rsvd[2];
|
||||
__le32 split_entry_0;
|
||||
__le32 split_entry_1;
|
||||
__le32 split_entry_2;
|
||||
__le32 split_entry_3;
|
||||
u8 rsvd2[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* qpc_split_entries (size:128b/16B) */
|
||||
struct qpc_split_entries {
|
||||
__le32 qp_num_l2_entries;
|
||||
__le32 qp_num_qp1_entries;
|
||||
__le32 rsvd[2];
|
||||
};
|
||||
|
||||
/* srq_split_entries (size:128b/16B) */
|
||||
struct srq_split_entries {
|
||||
__le32 srq_num_l2_entries;
|
||||
__le32 rsvd;
|
||||
__le32 rsvd2[2];
|
||||
};
|
||||
|
||||
/* cq_split_entries (size:128b/16B) */
|
||||
struct cq_split_entries {
|
||||
__le32 cq_num_l2_entries;
|
||||
__le32 rsvd;
|
||||
__le32 rsvd2[2];
|
||||
};
|
||||
|
||||
/* vnic_split_entries (size:128b/16B) */
|
||||
struct vnic_split_entries {
|
||||
__le32 vnic_num_vnic_entries;
|
||||
__le32 rsvd;
|
||||
__le32 rsvd2[2];
|
||||
};
|
||||
|
||||
/* mrav_split_entries (size:128b/16B) */
|
||||
struct mrav_split_entries {
|
||||
__le32 mrav_num_av_entries;
|
||||
__le32 rsvd;
|
||||
__le32 rsvd2[2];
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
|
||||
struct hwrm_func_backing_store_qcaps_v2_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 type;
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
|
||||
u8 rsvd[6];
|
||||
};
|
||||
|
||||
/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
|
||||
struct hwrm_func_backing_store_qcaps_v2_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le16 type;
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
|
||||
__le16 entry_size;
|
||||
__le32 flags;
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL
|
||||
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL
|
||||
__le32 instance_bit_map;
|
||||
u8 ctx_init_value;
|
||||
u8 ctx_init_offset;
|
||||
u8 entry_multiple;
|
||||
u8 rsvd;
|
||||
__le32 max_num_entries;
|
||||
__le32 min_num_entries;
|
||||
__le16 next_valid_type;
|
||||
u8 subtype_valid_cnt;
|
||||
u8 rsvd2;
|
||||
__le32 split_entry_0;
|
||||
__le32 split_entry_1;
|
||||
__le32 split_entry_2;
|
||||
__le32 split_entry_3;
|
||||
u8 rsvd3[3];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_func_drv_if_change_input (size:192b/24B) */
|
||||
struct hwrm_func_drv_if_change_input {
|
||||
__le16 req_type;
|
||||
@ -3741,7 +4086,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_port_mac_cfg_input (size:384b/48B) */
|
||||
/* hwrm_port_mac_cfg_input (size:448b/56B) */
|
||||
struct hwrm_port_mac_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -3807,7 +4152,8 @@ struct hwrm_port_mac_cfg_input {
|
||||
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
|
||||
u8 unused_0[3];
|
||||
__le32 ptp_freq_adj_ppb;
|
||||
__le32 ptp_adj_phase;
|
||||
u8 unused_1[4];
|
||||
__le64 ptp_adj_phase;
|
||||
};
|
||||
|
||||
/* hwrm_port_mac_cfg_output (size:128b/16B) */
|
||||
@ -3850,6 +4196,7 @@ struct hwrm_port_mac_ptp_qcfg_output {
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL
|
||||
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL
|
||||
u8 unused_0[3];
|
||||
__le32 rx_ts_reg_off_lower;
|
||||
__le32 rx_ts_reg_off_upper;
|
||||
@ -4339,7 +4686,8 @@ struct hwrm_port_phy_qcaps_output {
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL
|
||||
#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12
|
||||
__le16 supported_speeds_force_mode;
|
||||
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
|
||||
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
|
||||
@ -4399,7 +4747,7 @@ struct hwrm_port_phy_qcaps_output {
|
||||
__le16 flags2;
|
||||
#define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
|
||||
#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
|
||||
u8 unused_0[1];
|
||||
u8 internal_port_cnt;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -6221,12 +6569,13 @@ struct hwrm_vnic_rss_cfg_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 hash_type;
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
|
||||
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
|
||||
__le16 vnic_id;
|
||||
u8 ring_table_pair_index;
|
||||
u8 hash_mode_flags;
|
||||
@ -7898,6 +8247,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
|
||||
struct hwrm_tunnel_dst_port_query_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -8909,6 +9259,50 @@ struct hwrm_dbg_qcfg_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */
|
||||
struct hwrm_dbg_crashdump_medium_cfg_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 output_dest_flags;
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL
|
||||
__le16 pg_size_lvl;
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2)
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5
|
||||
__le32 size;
|
||||
__le32 coredump_component_disable_flags;
|
||||
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL
|
||||
__le32 unused_0;
|
||||
__le64 pbl;
|
||||
};
|
||||
|
||||
/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */
|
||||
struct hwrm_dbg_crashdump_medium_cfg_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 unused_1[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* coredump_segment_record (size:128b/16B) */
|
||||
struct coredump_segment_record {
|
||||
__le16 component_id;
|
||||
@ -9372,8 +9766,35 @@ struct hwrm_nvm_install_update_output {
|
||||
__le16 resp_len;
|
||||
__le64 installed_items;
|
||||
u8 result;
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED
|
||||
u8 problem_item;
|
||||
#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
|
||||
#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
|
||||
|
@ -19,6 +19,20 @@
|
||||
#include "bnxt_hwrm.h"
|
||||
#include "bnxt_ptp.h"
|
||||
|
||||
static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
|
||||
{
|
||||
struct hwrm_func_ptp_cfg_input *req;
|
||||
int rc;
|
||||
|
||||
rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
|
||||
req->ptp_set_time = cpu_to_le64(time);
|
||||
return hwrm_req_send(bp, req);
|
||||
}
|
||||
|
||||
int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
|
||||
{
|
||||
unsigned int ptp_class;
|
||||
@ -48,6 +62,9 @@ static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
|
||||
ptp_info);
|
||||
u64 ns = timespec64_to_ns(ts);
|
||||
|
||||
if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
|
||||
return bnxt_ptp_cfg_settime(ptp->bp, ns);
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ns);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
@ -131,11 +148,47 @@ static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Caller holds ptp_lock */
|
||||
void bnxt_ptp_update_current_time(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
|
||||
WRITE_ONCE(ptp->old_time, ptp->current_time);
|
||||
}
|
||||
|
||||
static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
|
||||
{
|
||||
struct hwrm_port_mac_cfg_input *req;
|
||||
int rc;
|
||||
|
||||
rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
|
||||
req->ptp_adj_phase = cpu_to_le64(delta);
|
||||
|
||||
rc = hwrm_req_send(ptp->bp, req);
|
||||
if (rc) {
|
||||
netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
|
||||
} else {
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
bnxt_ptp_update_current_time(ptp->bp);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
|
||||
ptp_info);
|
||||
|
||||
if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
|
||||
return bnxt_ptp_adjphc(ptp, delta);
|
||||
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
timecounter_adjtime(&ptp->tc, delta);
|
||||
spin_unlock_bh(&ptp->ptp_lock);
|
||||
@ -714,7 +767,70 @@ static bool bnxt_pps_config_ok(struct bnxt *bp)
|
||||
return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
|
||||
}
|
||||
|
||||
int bnxt_ptp_init(struct bnxt *bp)
|
||||
static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (!ptp->ptp_clock) {
|
||||
memset(&ptp->cc, 0, sizeof(ptp->cc));
|
||||
ptp->cc.read = bnxt_cc_read;
|
||||
ptp->cc.mask = CYCLECOUNTER_MASK(48);
|
||||
ptp->cc.shift = 0;
|
||||
ptp->cc.mult = 1;
|
||||
ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
|
||||
}
|
||||
if (init_tc)
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
|
||||
}
|
||||
|
||||
/* Caller holds ptp_lock */
|
||||
void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
|
||||
{
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ns);
|
||||
/* For RTC, cycle_last must be in sync with the timecounter value. */
|
||||
ptp->tc.cycle_last = ns & ptp->cc.mask;
|
||||
}
|
||||
|
||||
int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
|
||||
{
|
||||
struct timespec64 tsp;
|
||||
u64 ns;
|
||||
int rc;
|
||||
|
||||
if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC))
|
||||
return -ENODEV;
|
||||
|
||||
if (!phc_cfg) {
|
||||
ktime_get_real_ts64(&tsp);
|
||||
ns = timespec64_to_ns(&tsp);
|
||||
rc = bnxt_ptp_cfg_settime(bp, ns);
|
||||
if (rc)
|
||||
return rc;
|
||||
} else {
|
||||
rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns);
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
spin_lock_bh(&bp->ptp_cfg->ptp_lock);
|
||||
bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
|
||||
spin_unlock_bh(&bp->ptp_cfg->ptp_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bnxt_ptp_free(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
|
||||
if (ptp->ptp_clock) {
|
||||
ptp_clock_unregister(ptp->ptp_clock);
|
||||
ptp->ptp_clock = NULL;
|
||||
kfree(ptp->ptp_info.pin_config);
|
||||
ptp->ptp_info.pin_config = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
|
||||
{
|
||||
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
|
||||
int rc;
|
||||
@ -726,26 +842,23 @@ int bnxt_ptp_init(struct bnxt *bp)
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
|
||||
bnxt_ptp_timecounter_init(bp, false);
|
||||
rc = bnxt_ptp_init_rtc(bp, phc_cfg);
|
||||
if (rc)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
|
||||
return 0;
|
||||
|
||||
if (ptp->ptp_clock) {
|
||||
ptp_clock_unregister(ptp->ptp_clock);
|
||||
ptp->ptp_clock = NULL;
|
||||
kfree(ptp->ptp_info.pin_config);
|
||||
ptp->ptp_info.pin_config = NULL;
|
||||
}
|
||||
bnxt_ptp_free(bp);
|
||||
|
||||
atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
|
||||
spin_lock_init(&ptp->ptp_lock);
|
||||
|
||||
memset(&ptp->cc, 0, sizeof(ptp->cc));
|
||||
ptp->cc.read = bnxt_cc_read;
|
||||
ptp->cc.mask = CYCLECOUNTER_MASK(48);
|
||||
ptp->cc.shift = 0;
|
||||
ptp->cc.mult = 1;
|
||||
|
||||
ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
|
||||
timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
|
||||
if (!(bp->fw_cap & BNXT_FW_CAP_PTP_RTC))
|
||||
bnxt_ptp_timecounter_init(bp, true);
|
||||
|
||||
ptp->ptp_info = bnxt_ptp_caps;
|
||||
if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
|
||||
@ -757,8 +870,8 @@ int bnxt_ptp_init(struct bnxt *bp)
|
||||
int err = PTR_ERR(ptp->ptp_clock);
|
||||
|
||||
ptp->ptp_clock = NULL;
|
||||
bnxt_unmap_ptp_regs(bp);
|
||||
return err;
|
||||
rc = err;
|
||||
goto out;
|
||||
}
|
||||
if (bp->flags & BNXT_FLAG_CHIP_P5) {
|
||||
spin_lock_bh(&ptp->ptp_lock);
|
||||
@ -768,6 +881,11 @@ int bnxt_ptp_init(struct bnxt *bp)
|
||||
ptp_schedule_worker(ptp->ptp_clock, 0);
|
||||
}
|
||||
return 0;
|
||||
|
||||
out:
|
||||
bnxt_ptp_free(bp);
|
||||
bnxt_unmap_ptp_regs(bp);
|
||||
return rc;
|
||||
}
|
||||
|
||||
void bnxt_ptp_clear(struct bnxt *bp)
|
||||
|
@ -131,12 +131,15 @@ do { \
|
||||
#endif
|
||||
|
||||
int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off);
|
||||
void bnxt_ptp_update_current_time(struct bnxt *bp);
|
||||
void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);
|
||||
void bnxt_ptp_reapply_pps(struct bnxt *bp);
|
||||
int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
|
||||
int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
|
||||
int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
|
||||
int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
|
||||
int bnxt_ptp_init(struct bnxt *bp);
|
||||
void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns);
|
||||
int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg);
|
||||
int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg);
|
||||
void bnxt_ptp_clear(struct bnxt *bp);
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user