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gpio: 104-dio-48e: Implement and utilize register structures
Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. The 104-DIO-48E device features an Intel 8255 compatible GPIO interface, so the i8255 GPIO module is selected and utilized as well. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: John Hentges <jhentges@accesio.com> Cc: Jay Dolan <jay.dolan@accesio.com> Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
parent
fb38af4a3a
commit
71b7b39725
@ -841,6 +841,7 @@ config GPIO_104_DIO_48E
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depends on PC104
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select ISA_BUS_API
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select GPIOLIB_IRQCHIP
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select GPIO_I8255
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help
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Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E,
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104-DIO-24E). The base port addresses for the devices may be
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@ -6,8 +6,7 @@
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* This driver supports the following ACCES devices: 104-DIO-48E and
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* 104-DIO-24E.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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@ -20,6 +19,11 @@
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "gpio-i8255.h"
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MODULE_IMPORT_NS(I8255);
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#define DIO48E_EXTENT 16
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#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
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@ -33,34 +37,54 @@ static unsigned int irq[MAX_NUM_DIO48E];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
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#define DIO48E_NUM_PPI 2
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/**
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* struct dio48e_reg - device register structure
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* @ppi: Programmable Peripheral Interface groups
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* @enable_buffer: Enable/Disable Buffer groups
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* @unused1: Unused
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* @enable_interrupt: Write: Enable Interrupt
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* Read: Disable Interrupt
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* @unused2: Unused
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* @enable_counter: Write: Enable Counter/Timer Addressing
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* Read: Disable Counter/Timer Addressing
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* @unused3: Unused
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* @clear_interrupt: Clear Interrupt
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*/
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struct dio48e_reg {
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struct i8255 ppi[DIO48E_NUM_PPI];
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u8 enable_buffer[DIO48E_NUM_PPI];
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u8 unused1;
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u8 enable_interrupt;
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u8 unused2;
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u8 enable_counter;
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u8 unused3;
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u8 clear_interrupt;
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};
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/**
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* struct dio48e_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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* @irq_mask: I/O bits affected by interrupts
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* @chip: instance of the gpio_chip
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* @ppi_state: PPI device states
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* @lock: synchronization lock to prevent I/O race conditions
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* @reg: I/O address offset for the device registers
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct dio48e_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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struct i8255_state ppi_state[DIO48E_NUM_PPI];
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raw_spinlock_t lock;
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void __iomem *base;
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struct dio48e_reg __iomem *reg;
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unsigned char irq_mask;
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};
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static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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if (dio48egpio->io_state[port] & mask)
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return GPIO_LINE_DIRECTION_IN;
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if (i8255_get_direction(dio48egpio->ppi_state, offset))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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@ -68,38 +92,9 @@ static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset
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static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4;
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unsigned long flags;
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unsigned int control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] |= 0xF0;
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dio48egpio->control[control_port] |= BIT(3);
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} else {
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dio48egpio->io_state[io_port] |= 0x0F;
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dio48egpio->control[control_port] |= BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] |= BIT(4);
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else
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dio48egpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | dio48egpio->control[control_port];
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iowrite8(control, control_addr);
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control &= ~BIT(7);
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iowrite8(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state,
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offset);
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return 0;
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}
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@ -108,48 +103,9 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int off
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int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int mask = BIT(offset % 8);
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void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4;
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const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned int control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] &= 0x0F;
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dio48egpio->control[control_port] &= ~BIT(3);
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} else {
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dio48egpio->io_state[io_port] &= 0xF0;
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dio48egpio->control[control_port] &= ~BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] &= ~BIT(4);
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else
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dio48egpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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dio48egpio->out_state[io_port] |= mask;
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else
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dio48egpio->out_state[io_port] &= ~mask;
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control = BIT(7) | dio48egpio->control[control_port];
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iowrite8(control, control_addr);
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iowrite8(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
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control &= ~BIT(7);
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iowrite8(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state,
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offset, value);
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return 0;
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}
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@ -157,47 +113,16 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int off
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static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned int port_state;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(dio48egpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return -EINVAL;
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}
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port_state = ioread8(dio48egpio->base + in_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return !!(port_state & mask);
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return i8255_get(dio48egpio->reg->ppi, offset);
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}
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static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
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static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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void __iomem *port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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port_addr = dio48egpio->base + ports[offset / 8];
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio);
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return 0;
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}
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@ -205,49 +130,17 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (value)
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dio48egpio->out_state[port] |= mask;
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else
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dio48egpio->out_state[port] &= ~mask;
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iowrite8(dio48egpio->out_state[port], dio48egpio->base + out_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value);
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}
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static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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void __iomem *port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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port_addr = dio48egpio->base + ports[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* update output state data and set device gpio register */
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dio48egpio->out_state[index] &= ~gpio_mask;
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dio48egpio->out_state[index] |= bitmask;
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iowrite8(dio48egpio->out_state[index], port_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask,
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bits, chip->ngpio);
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}
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static void dio48e_irq_ack(struct irq_data *data)
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@ -274,7 +167,7 @@ static void dio48e_irq_mask(struct irq_data *data)
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if (!dio48egpio->irq_mask)
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/* disable interrupts */
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ioread8(dio48egpio->base + 0xB);
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ioread8(&dio48egpio->reg->enable_interrupt);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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@ -294,8 +187,8 @@ static void dio48e_irq_unmask(struct irq_data *data)
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if (!dio48egpio->irq_mask) {
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/* enable interrupts */
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iowrite8(0x00, dio48egpio->base + 0xF);
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iowrite8(0x00, dio48egpio->base + 0xB);
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iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
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iowrite8(0x00, &dio48egpio->reg->enable_interrupt);
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}
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if (offset == 19)
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@ -341,7 +234,7 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
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raw_spin_lock(&dio48egpio->lock);
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iowrite8(0x00, dio48egpio->base + 0xF);
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iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
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raw_spin_unlock(&dio48egpio->lock);
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@ -373,11 +266,26 @@ static int dio48e_irq_init_hw(struct gpio_chip *gc)
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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ioread8(dio48egpio->base + 0xB);
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ioread8(&dio48egpio->reg->enable_interrupt);
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return 0;
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}
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static void dio48e_init_ppi(struct i8255 __iomem *const ppi,
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struct i8255_state *const ppi_state)
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{
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const unsigned long ngpio = 24;
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const unsigned long mask = GENMASK(ngpio - 1, 0);
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const unsigned long bits = 0;
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unsigned long i;
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/* Initialize all GPIO to output 0 */
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for (i = 0; i < DIO48E_NUM_PPI; i++) {
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i8255_mode0_output(&ppi[i]);
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i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
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}
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}
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static int dio48e_probe(struct device *dev, unsigned int id)
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{
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struct dio48e_gpio *dio48egpio;
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@ -395,8 +303,8 @@ static int dio48e_probe(struct device *dev, unsigned int id)
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return -EBUSY;
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}
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dio48egpio->base = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
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if (!dio48egpio->base)
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dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
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if (!dio48egpio->reg)
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return -ENOMEM;
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dio48egpio->chip.label = name;
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@ -425,17 +333,8 @@ static int dio48e_probe(struct device *dev, unsigned int id)
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raw_spin_lock_init(&dio48egpio->lock);
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/* initialize all GPIO as output */
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iowrite8(0x80, dio48egpio->base + 3);
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iowrite8(0x00, dio48egpio->base);
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iowrite8(0x00, dio48egpio->base + 1);
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iowrite8(0x00, dio48egpio->base + 2);
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iowrite8(0x00, dio48egpio->base + 3);
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iowrite8(0x80, dio48egpio->base + 7);
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iowrite8(0x00, dio48egpio->base + 4);
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iowrite8(0x00, dio48egpio->base + 5);
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iowrite8(0x00, dio48egpio->base + 6);
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iowrite8(0x00, dio48egpio->base + 7);
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i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI);
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dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state);
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err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
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if (err) {
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