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phy: qcom-qmp: Add missing register definitions for PCS V5

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Add missing register offsets for PCS V5 registers.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
devi priya 2024-05-16 08:54:35 +05:30 committed by Vinod Koul
parent f1aaa788b9
commit 71ae2acf1d
1 changed files with 14 additions and 0 deletions
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14
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
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@ -11,8 +11,22 @@
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0
#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4
#endif