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ASoC: sun4i-i2s: Move the format configuration to a callback
The two main generations of our I2S controller require a slightly different
format configuration, mostly because of a quite different register layout
and some additional registers being needed on the newer generation.
This used to be controlled through a bunch of booleans, however this proved
to be quite impractical, especially since a bunch of SoCs forgot to set
those parameters and therefore were broken from that point of view.
Fixes: 21faaea134 ("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://lore.kernel.org/r/dc818644c3e40734e7a97247c994b1fca1c3c047.1566242458.git-series.maxime.ripard@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Maxime Ripard
Mark Brown
parent
d70be625f2
commit
71137bcd0a
@ -93,6 +93,11 @@
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#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
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#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
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#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
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#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
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#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
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#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
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#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
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#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
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@ -121,9 +126,7 @@ struct sun4i_i2s;
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* struct sun4i_i2s_quirks - Differences between SoC variants.
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*
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* @has_reset: SoC needs reset deasserted.
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* @has_slave_select_bit: SoC has a bit to enable slave mode.
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* @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
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* @has_chsel_offset: SoC uses offset for selecting dai operational mode.
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* @reg_offset_txdata: offset of the tx fifo.
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* @sun4i_i2s_regmap: regmap config to use.
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* @mclk_offset: Value by which mclkdiv needs to be adjusted.
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@ -133,13 +136,10 @@ struct sun4i_i2s;
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* @field_fmt_sr: regmap field to set sample resolution.
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* @field_fmt_bclk: regmap field to set clk polarity.
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* @field_fmt_lrclk: regmap field to set frame polarity.
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* @field_fmt_mode: regmap field to set the operational mode.
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*/
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struct sun4i_i2s_quirks {
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bool has_reset;
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bool has_slave_select_bit;
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bool has_fmt_set_lrck_period;
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bool has_chsel_offset;
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unsigned int reg_offset_txdata; /* TX FIFO */
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const struct regmap_config *sun4i_i2s_regmap;
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unsigned int mclk_offset;
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@ -151,12 +151,12 @@ struct sun4i_i2s_quirks {
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struct reg_field field_fmt_sr;
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struct reg_field field_fmt_bclk;
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struct reg_field field_fmt_lrclk;
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struct reg_field field_fmt_mode;
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s8 (*get_sr)(const struct sun4i_i2s *, int);
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s8 (*get_wss)(const struct sun4i_i2s *, int);
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int (*set_chan_cfg)(const struct sun4i_i2s *,
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const struct snd_pcm_hw_params *);
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int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
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};
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struct sun4i_i2s {
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@ -176,7 +176,6 @@ struct sun4i_i2s {
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struct regmap_field *field_fmt_sr;
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struct regmap_field *field_fmt_bclk;
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struct regmap_field *field_fmt_lrclk;
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struct regmap_field *field_fmt_mode;
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const struct sun4i_i2s_quirks *variant;
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};
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@ -465,52 +464,117 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
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params_width(params));
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}
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static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
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unsigned int fmt)
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{
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struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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u32 val;
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u32 offset = 0;
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u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
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u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
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/* DAI Mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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val = SUN4I_I2S_FMT0_FMT_I2S;
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offset = 1;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val = SUN4I_I2S_FMT0_FMT_LEFT_J;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
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break;
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default:
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dev_err(dai->dev, "Unsupported format: %d\n",
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fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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}
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if (i2s->variant->has_chsel_offset) {
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/*
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* offset being set indicates that we're connected to an i2s
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* device, however offset is only used on the sun8i block and
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* i2s shares the same setting with the LJ format. Increment
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* val so that the bit to value to write is correct.
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*/
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if (offset > 0)
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val++;
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/* blck offset determines whether i2s or LJ */
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regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
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SUN8I_I2S_TX_CHAN_OFFSET_MASK,
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SUN8I_I2S_TX_CHAN_OFFSET(offset));
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regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
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SUN4I_I2S_FMT0_FMT_MASK, val);
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regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
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SUN8I_I2S_TX_CHAN_OFFSET_MASK,
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SUN8I_I2S_TX_CHAN_OFFSET(offset));
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* BCLK and LRCLK master */
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val = SUN4I_I2S_CTRL_MODE_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* BCLK and LRCLK slave */
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val = SUN4I_I2S_CTRL_MODE_SLAVE;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN4I_I2S_CTRL_MODE_MASK, val);
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return 0;
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}
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static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
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unsigned int fmt)
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{
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u32 mode, val;
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u8 offset;
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/* DAI Mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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mode = SUN8I_I2S_CTRL_MODE_LEFT;
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offset = 1;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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mode = SUN8I_I2S_CTRL_MODE_LEFT;
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offset = 0;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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mode = SUN8I_I2S_CTRL_MODE_RIGHT;
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offset = 0;
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break;
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default:
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return -EINVAL;
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}
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regmap_field_write(i2s->field_fmt_mode, val);
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN8I_I2S_CTRL_MODE_MASK, mode);
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regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
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SUN8I_I2S_TX_CHAN_OFFSET_MASK,
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SUN8I_I2S_TX_CHAN_OFFSET(offset));
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regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
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SUN8I_I2S_TX_CHAN_OFFSET_MASK,
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SUN8I_I2S_TX_CHAN_OFFSET(offset));
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* BCLK and LRCLK master */
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val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* BCLK and LRCLK slave */
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val = 0;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
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val);
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return 0;
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}
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static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
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u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
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int ret;
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/* DAI clock polarity */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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@ -538,50 +602,10 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
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regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
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if (i2s->variant->has_slave_select_bit) {
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* BCLK and LRCLK master */
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val = SUN4I_I2S_CTRL_MODE_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* BCLK and LRCLK slave */
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val = SUN4I_I2S_CTRL_MODE_SLAVE;
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break;
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default:
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dev_err(dai->dev, "Unsupported slave setting: %d\n",
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fmt & SND_SOC_DAIFMT_MASTER_MASK);
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN4I_I2S_CTRL_MODE_MASK,
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val);
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} else {
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/*
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* The newer i2s block does not have a slave select bit,
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* instead the clk pins are configured as inputs.
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*/
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* BCLK and LRCLK master */
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val = SUN8I_I2S_CTRL_BCLK_OUT |
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SUN8I_I2S_CTRL_LRCK_OUT;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* BCLK and LRCLK slave */
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val = 0;
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break;
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default:
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dev_err(dai->dev, "Unsupported slave setting: %d\n",
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fmt & SND_SOC_DAIFMT_MASTER_MASK);
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN8I_I2S_CTRL_BCLK_OUT |
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SUN8I_I2S_CTRL_LRCK_OUT,
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val);
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ret = i2s->variant->set_fmt(i2s, fmt);
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if (ret) {
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dev_err(dai->dev, "Unsupported format configuration\n");
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return ret;
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}
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/* Set significant bits in our FIFOs */
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@ -933,11 +957,10 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.has_slave_select_bit = true,
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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.get_sr = sun4i_i2s_get_sr,
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.get_wss = sun4i_i2s_get_wss,
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.set_chan_cfg = sun4i_i2s_set_chan_cfg,
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.set_fmt = sun4i_i2s_set_soc_fmt,
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};
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static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
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@ -949,11 +972,10 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.has_slave_select_bit = true,
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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.get_sr = sun4i_i2s_get_sr,
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.get_wss = sun4i_i2s_get_wss,
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.set_chan_cfg = sun4i_i2s_set_chan_cfg,
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.set_fmt = sun4i_i2s_set_soc_fmt,
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};
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static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
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@ -965,11 +987,10 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.has_slave_select_bit = true,
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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.get_sr = sun8i_i2s_get_sr_wss,
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.get_wss = sun8i_i2s_get_sr_wss,
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.set_chan_cfg = sun8i_i2s_set_chan_cfg,
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.set_fmt = sun8i_i2s_set_soc_fmt,
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};
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static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
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@ -979,32 +1000,30 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
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.mclk_offset = 1,
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.bclk_offset = 2,
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.has_fmt_set_lrck_period = true,
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.has_chsel_offset = true,
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.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
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.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
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.get_sr = sun8i_i2s_get_sr_wss,
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.get_wss = sun8i_i2s_get_sr_wss,
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.set_chan_cfg = sun8i_i2s_set_chan_cfg,
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.set_fmt = sun8i_i2s_set_soc_fmt,
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};
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static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
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.has_reset = true,
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.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
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.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
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.has_slave_select_bit = true,
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.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
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.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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.get_sr = sun4i_i2s_get_sr,
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.get_wss = sun4i_i2s_get_wss,
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.set_chan_cfg = sun4i_i2s_set_chan_cfg,
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.set_fmt = sun4i_i2s_set_soc_fmt,
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};
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static int sun4i_i2s_init_regmap_fields(struct device *dev,
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@ -1040,12 +1059,6 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
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if (IS_ERR(i2s->field_fmt_lrclk))
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return PTR_ERR(i2s->field_fmt_lrclk);
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i2s->field_fmt_mode =
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devm_regmap_field_alloc(dev, i2s->regmap,
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i2s->variant->field_fmt_mode);
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if (IS_ERR(i2s->field_fmt_mode))
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return PTR_ERR(i2s->field_fmt_mode);
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return 0;
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}
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