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KVM: x86: Bug the VM if an accelerated x2APIC trap occurs on a "bad" reg

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Bug the VM if retrieving the x2APIC MSR/register while processing an
accelerated vAPIC trap VM-Exit fails.  In theory it's impossible for the
lookup to fail as hardware has already validated the register, but bugs
happen, and not checking the result of kvm_lapic_msr_read() would result
in consuming the uninitialized "val" if a KVM or hardware bug occurs.

Fixes: 1bd9dfec9f ("KVM: x86: Do not block APIC write for non ICR registers")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220804235028.1766253-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson 2022-08-04 23:50:28 +00:00 committed by Paolo Bonzini
parent c3c28d24d9
commit 70c8327c11
1 changed files with 5 additions and 3 deletions
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8
arch/x86/kvm/lapic.c
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@ -2284,10 +2284,12 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
struct kvm_lapic *apic = vcpu->arch.apic; struct kvm_lapic *apic = vcpu->arch.apic;
u64 val; u64 val;
if (apic_x2apic_mode(apic)) if (apic_x2apic_mode(apic)) {
kvm_lapic_msr_read(apic, offset, &val); if (KVM_BUG_ON(kvm_lapic_msr_read(apic, offset, &val), vcpu->kvm))
else return;
} else {
val = kvm_lapic_get_reg(apic, offset); val = kvm_lapic_get_reg(apic, offset);
}
/* /*
* ICR is a single 64-bit register when x2APIC is enabled. For legacy * ICR is a single 64-bit register when x2APIC is enabled. For legacy