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[IA64] Reschedule __kernel_syscall_via_epc().
Avoid some stalls, which is good for about 2 cycles when invoking a light-weight handler. When invoking a heavy-weight handler, this helps by about 7 cycles, with most of the improvement coming from the improved branch-prediction achieved by splitting the BBB bundle into two MIB bundles. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -79,31 +79,34 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
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;;
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rsm psr.be // note: on McKinley "rsm psr.be/srlz.d" is slightly faster than "rum psr.be"
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LOAD_FSYSCALL_TABLE(r14)
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;;
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mov r16=IA64_KR(CURRENT) // 12 cycle read latency
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tnat.nz p10,p9=r15
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shladd r18=r17,3,r14
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mov r19=NR_syscalls-1
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;;
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shladd r18=r17,3,r14
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srlz.d
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cmp.ne p8,p0=r0,r0 // p8 <- FALSE
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lfetch [r18] // M0|1
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mov r29=psr // read psr (12 cyc load latency)
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/* Note: if r17 is a NaT, p6 will be set to zero. */
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cmp.geu p6,p7=r19,r17 // (syscall > 0 && syscall < 1024+NR_syscalls)?
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;;
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(p6) ld8 r18=[r18]
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mov r21=ar.fpsr
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add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
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;;
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(p6) mov b7=r18
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(p6) tbit.z p8,p0=r18,0
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(p8) br.dptk.many b7
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(p6) rsm psr.i
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mov r27=ar.rsc
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tnat.nz p10,p9=r15
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mov r26=ar.pfs
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;;
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mov r29=psr // read psr (12 cyc load latency)
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srlz.d
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(p6) ld8 r18=[r18]
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nop.i 0
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;;
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nop.m 0
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(p6) mov b7=r18
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(p6) tbit.z.unc p8,p0=r18,0
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nop.m 0
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nop.i 0
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(p8) br.dptk.many b7
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mov r27=ar.rsc
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(p6) rsm psr.i
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/*
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* brl.cond doesn't work as intended because the linker would convert this branch
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* into a branch to a PLT. Perhaps there will be a way to avoid this with some
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@ -111,6 +114,8 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
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* instead.
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*/
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#ifdef CONFIG_ITANIUM
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add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
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;;
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(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down
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;;
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(p6) mov b7=r14
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