mirror of
https://github.com/torvalds/linux.git
synced 2024-11-23 20:51:44 +00:00
[BNX2]: Refine tx coalescing setup.
Make the tx coalescing setup code independent of the MSIX vector. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
f3014c0cb6
commit
6f743ca052
@ -4438,18 +4438,21 @@ bnx2_init_chip(struct bnx2 *bp)
|
||||
}
|
||||
|
||||
if (bp->flags & BNX2_FLAG_USING_MSIX) {
|
||||
u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
|
||||
BNX2_HC_SB_CONFIG_1;
|
||||
|
||||
REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
|
||||
BNX2_HC_MSIX_BIT_VECTOR_VAL);
|
||||
|
||||
REG_WR(bp, BNX2_HC_SB_CONFIG_1,
|
||||
REG_WR(bp, base,
|
||||
BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
|
||||
BNX2_HC_SB_CONFIG_1_ONE_SHOT);
|
||||
|
||||
REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1,
|
||||
REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
|
||||
(bp->tx_quick_cons_trip_int << 16) |
|
||||
bp->tx_quick_cons_trip);
|
||||
|
||||
REG_WR(bp, BNX2_HC_TX_TICKS_1,
|
||||
REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
|
||||
(bp->tx_ticks_int << 16) | bp->tx_ticks);
|
||||
|
||||
val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
|
||||
|
@ -5510,6 +5510,15 @@ struct l2_fhdr {
|
||||
#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
|
||||
#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
|
||||
|
||||
#define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)
|
||||
#define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \
|
||||
BNX2_HC_SB_CONFIG_1)
|
||||
#define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)
|
||||
#define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)
|
||||
#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
|
||||
BNX2_HC_SB_CONFIG_1)
|
||||
#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
|
||||
|
||||
|
||||
/*
|
||||
* txp_reg definition
|
||||
|
Loading…
Reference in New Issue
Block a user