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arm64 fixes for -rc4
- Disable software tag-based KASAN when compiling with GCC, as functions are incorrectly instrumented leading to a crash early during boot. - Fix pkey configuration for kernel threads when POE is enabled. - Fix invalid memory accesses in uprobes when targetting load-literal instructions. -----BEGIN PGP SIGNATURE----- iQFEBAABCgAuFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAmcPrzQQHHdpbGxAa2Vy bmVsLm9yZwAKCRC3rHDchMFjNIr6B/wN+o1xI7Fv/QdlaTuKYLvOOg/XTl6sbUDj YssxtjhpKuaFVG4zJHNsWvgUqO+YCM7m3F1L8LVPMF7l2xoKtRTIB1Ye315hTjYm dW5Te6xBMVKF8SVxE8sBbZobdokIW1JNPBrvGvHO3d5ujmofzwHU8RNMXuTUItRw z85Qy75FkEDTEbsWhS3VL5HOgEr+k0TYDRa8SXwKWVj7/rYna3tO39kIdS5dt9VX wDJbnxtWJMhiHmDnevFFhBkSZrips12P1Rb6HUSmhpUJh0Rk4TAZntSl2f/lr+jA PuboBbSG68UOCwAHoNmTcLdFhkiNaiyw4w2F7hk2A6aNRtme+bT0 =M/ug -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: - Disable software tag-based KASAN when compiling with GCC, as functions are incorrectly instrumented leading to a crash early during boot - Fix pkey configuration for kernel threads when POE is enabled - Fix invalid memory accesses in uprobes when targetting load-literal instructions * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: kasan: Disable Software Tag-Based KASAN with GCC Documentation/protection-keys: add AArch64 to documentation arm64: set POR_EL0 for kernel threads arm64: probes: Fix uprobes for big-endian kernels arm64: probes: Fix simulate_ldr*_literal() arm64: probes: Remove broken LDR (literal) uprobe support
This commit is contained in:
Linus Torvalds
commit
6efbea77b3
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@ -12,7 +12,10 @@ Pkeys Userspace (PKU) is a feature which can be found on:
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* Intel server CPUs, Skylake and later
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* Intel client CPUs, Tiger Lake (11th Gen Core) and later
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* Future AMD CPUs
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* arm64 CPUs implementing the Permission Overlay Extension (FEAT_S1POE)
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x86_64
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======
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Pkeys work by dedicating 4 previously Reserved bits in each page table entry to
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a "protection key", giving 16 possible keys.
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@ -28,6 +31,22 @@ register. The feature is only available in 64-bit mode, even though there is
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theoretically space in the PAE PTEs. These permissions are enforced on data
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access only and have no effect on instruction fetches.
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arm64
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=====
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Pkeys use 3 bits in each page table entry, to encode a "protection key index",
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giving 8 possible keys.
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Protections for each key are defined with a per-CPU user-writable system
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register (POR_EL0). This is a 64-bit register encoding read, write and execute
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overlay permissions for each protection key index.
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Being a CPU register, POR_EL0 is inherently thread-local, potentially giving
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each thread a different set of protections from every other thread.
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Unlike x86_64, the protection key permissions also apply to instruction
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fetches.
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Syscalls
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========
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@ -38,11 +57,10 @@ There are 3 system calls which directly interact with pkeys::
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int pkey_mprotect(unsigned long start, size_t len,
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unsigned long prot, int pkey);
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Before a pkey can be used, it must first be allocated with
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pkey_alloc(). An application calls the WRPKRU instruction
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directly in order to change access permissions to memory covered
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with a key. In this example WRPKRU is wrapped by a C function
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called pkey_set().
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Before a pkey can be used, it must first be allocated with pkey_alloc(). An
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application writes to the architecture specific CPU register directly in order
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to change access permissions to memory covered with a key. In this example
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this is wrapped by a C function called pkey_set().
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::
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int real_prot = PROT_READ|PROT_WRITE;
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@ -64,9 +82,9 @@ is no longer in use::
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munmap(ptr, PAGE_SIZE);
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pkey_free(pkey);
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.. note:: pkey_set() is a wrapper for the RDPKRU and WRPKRU instructions.
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An example implementation can be found in
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tools/testing/selftests/x86/protection_keys.c.
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.. note:: pkey_set() is a wrapper around writing to the CPU register.
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Example implementations can be found in
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tools/testing/selftests/mm/pkey-{arm64,powerpc,x86}.h
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Behavior
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========
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@ -96,3 +114,7 @@ with a read()::
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The kernel will send a SIGSEGV in both cases, but si_code will be set
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to SEGV_PKERR when violating protection keys versus SEGV_ACCERR when
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the plain mprotect() permissions are violated.
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Note that kernel accesses from a kthread (such as io_uring) will use a default
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value for the protection key register and so will not be consistent with
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userspace's value of the register or mprotect().
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@ -10,11 +10,9 @@
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#include <asm/insn.h>
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#include <asm/probes.h>
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#define MAX_UINSN_BYTES AARCH64_INSN_SIZE
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#define UPROBE_SWBP_INSN cpu_to_le32(BRK64_OPCODE_UPROBES)
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#define UPROBE_SWBP_INSN_SIZE AARCH64_INSN_SIZE
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#define UPROBE_XOL_SLOT_BYTES MAX_UINSN_BYTES
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#define UPROBE_XOL_SLOT_BYTES AARCH64_INSN_SIZE
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typedef __le32 uprobe_opcode_t;
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@ -23,8 +21,8 @@ struct arch_uprobe_task {
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struct arch_uprobe {
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union {
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u8 insn[MAX_UINSN_BYTES];
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u8 ixol[MAX_UINSN_BYTES];
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__le32 insn;
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__le32 ixol;
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};
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struct arch_probe_insn api;
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bool simulate;
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@ -99,10 +99,6 @@ arm_probe_decode_insn(probe_opcode_t insn, struct arch_probe_insn *api)
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aarch64_insn_is_blr(insn) ||
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aarch64_insn_is_ret(insn)) {
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api->handler = simulate_br_blr_ret;
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} else if (aarch64_insn_is_ldr_lit(insn)) {
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api->handler = simulate_ldr_literal;
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} else if (aarch64_insn_is_ldrsw_lit(insn)) {
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api->handler = simulate_ldrsw_literal;
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} else {
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/*
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* Instruction cannot be stepped out-of-line and we don't
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@ -140,6 +136,17 @@ arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
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probe_opcode_t insn = le32_to_cpu(*addr);
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probe_opcode_t *scan_end = NULL;
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unsigned long size = 0, offset = 0;
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struct arch_probe_insn *api = &asi->api;
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if (aarch64_insn_is_ldr_lit(insn)) {
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api->handler = simulate_ldr_literal;
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decoded = INSN_GOOD_NO_SLOT;
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} else if (aarch64_insn_is_ldrsw_lit(insn)) {
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api->handler = simulate_ldrsw_literal;
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decoded = INSN_GOOD_NO_SLOT;
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} else {
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decoded = arm_probe_decode_insn(insn, &asi->api);
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}
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/*
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* If there's a symbol defined in front of and near enough to
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@ -157,7 +164,6 @@ arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
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else
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scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
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}
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decoded = arm_probe_decode_insn(insn, &asi->api);
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if (decoded != INSN_REJECTED && scan_end)
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if (is_probed_address_atomic(addr - 1, scan_end))
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@ -171,17 +171,15 @@ simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs)
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void __kprobes
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simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
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{
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u64 *load_addr;
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unsigned long load_addr;
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int xn = opcode & 0x1f;
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int disp;
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disp = ldr_displacement(opcode);
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load_addr = (u64 *) (addr + disp);
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load_addr = addr + ldr_displacement(opcode);
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if (opcode & (1 << 30)) /* x0-x30 */
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set_x_reg(regs, xn, *load_addr);
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set_x_reg(regs, xn, READ_ONCE(*(u64 *)load_addr));
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else /* w0-w30 */
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set_w_reg(regs, xn, *load_addr);
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set_w_reg(regs, xn, READ_ONCE(*(u32 *)load_addr));
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instruction_pointer_set(regs, instruction_pointer(regs) + 4);
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}
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@ -189,14 +187,12 @@ simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
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void __kprobes
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simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs)
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{
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s32 *load_addr;
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unsigned long load_addr;
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int xn = opcode & 0x1f;
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int disp;
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disp = ldr_displacement(opcode);
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load_addr = (s32 *) (addr + disp);
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load_addr = addr + ldr_displacement(opcode);
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set_x_reg(regs, xn, *load_addr);
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set_x_reg(regs, xn, READ_ONCE(*(s32 *)load_addr));
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instruction_pointer_set(regs, instruction_pointer(regs) + 4);
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}
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@ -42,7 +42,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
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else if (!IS_ALIGNED(addr, AARCH64_INSN_SIZE))
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return -EINVAL;
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insn = *(probe_opcode_t *)(&auprobe->insn[0]);
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insn = le32_to_cpu(auprobe->insn);
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switch (arm_probe_decode_insn(insn, &auprobe->api)) {
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case INSN_REJECTED:
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@ -108,7 +108,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
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if (!auprobe->simulate)
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return false;
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insn = *(probe_opcode_t *)(&auprobe->insn[0]);
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insn = le32_to_cpu(auprobe->insn);
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addr = instruction_pointer(regs);
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if (auprobe->api.handler)
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@ -412,6 +412,9 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
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p->thread.cpu_context.x19 = (unsigned long)args->fn;
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p->thread.cpu_context.x20 = (unsigned long)args->fn_arg;
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if (system_supports_poe())
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p->thread.por_el0 = POR_EL0_INIT;
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}
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p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
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p->thread.cpu_context.sp = (unsigned long)childregs;
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@ -22,8 +22,11 @@ config ARCH_DISABLE_KASAN_INLINE
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config CC_HAS_KASAN_GENERIC
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def_bool $(cc-option, -fsanitize=kernel-address)
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# GCC appears to ignore no_sanitize_address when -fsanitize=kernel-hwaddress
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# is passed. See https://bugzilla.kernel.org/show_bug.cgi?id=218854 (and
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# the linked LKML thread) for more details.
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config CC_HAS_KASAN_SW_TAGS
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def_bool $(cc-option, -fsanitize=kernel-hwaddress)
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def_bool !CC_IS_GCC && $(cc-option, -fsanitize=kernel-hwaddress)
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# This option is only required for software KASAN modes.
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# Old GCC versions do not have proper support for no_sanitize_address.
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@ -98,7 +101,7 @@ config KASAN_SW_TAGS
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help
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Enables Software Tag-Based KASAN.
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Requires GCC 11+ or Clang.
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Requires Clang.
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Supported only on arm64 CPUs and relies on Top Byte Ignore.
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