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[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.
Signed-off-by: Graf Yang <graf.yang@analog.com> Cc: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Graf Yang
Bryan Wu
parent
db68254f06
commit
6ed8394230
@ -95,14 +95,14 @@ enum {
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AWA_data_clear = SYSCR,
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AWA_data_set = SYSCR,
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AWA_toggle = SYSCR,
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AWA_maska = UART_SCR,
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AWA_maska_clear = UART_SCR,
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AWA_maska_set = UART_SCR,
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AWA_maska_toggle = UART_SCR,
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AWA_maskb = UART_GCTL,
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AWA_maskb_clear = UART_GCTL,
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AWA_maskb_set = UART_GCTL,
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AWA_maskb_toggle = UART_GCTL,
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AWA_maska = BFIN_UART_SCR,
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AWA_maska_clear = BFIN_UART_SCR,
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AWA_maska_set = BFIN_UART_SCR,
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AWA_maska_toggle = BFIN_UART_SCR,
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AWA_maskb = BFIN_UART_GCTL,
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AWA_maskb_clear = BFIN_UART_GCTL,
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AWA_maskb_set = BFIN_UART_GCTL,
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AWA_maskb_toggle = BFIN_UART_GCTL,
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AWA_dir = SPORT1_STAT,
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AWA_polar = SPORT1_STAT,
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AWA_edge = SPORT1_STAT,
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@ -151,26 +151,26 @@ ENTRY(__start)
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/* Initialise UART - when booting from u-boot, the UART is not disabled
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* so if we dont initalize here, our serial console gets hosed */
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p0.h = hi(UART_LCR);
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p0.l = lo(UART_LCR);
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p0.h = hi(BFIN_UART_LCR);
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p0.l = lo(BFIN_UART_LCR);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable DLL writes */
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ssync;
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p0.h = hi(UART_DLL);
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p0.l = lo(UART_DLL);
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p0.h = hi(BFIN_UART_DLL);
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p0.l = lo(BFIN_UART_DLL);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_DLH);
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p0.l = lo(UART_DLH);
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p0.h = hi(BFIN_UART_DLH);
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p0.l = lo(BFIN_UART_DLH);
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r0 = 0x00(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_GCTL);
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p0.l = lo(UART_GCTL);
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p0.h = hi(BFIN_UART_GCTL);
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p0.l = lo(BFIN_UART_GCTL);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable UART clock */
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ssync;
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@ -182,26 +182,26 @@ ENTRY(__start)
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/* Initialise UART - when booting from u-boot, the UART is not disabled
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* so if we dont initalize here, our serial console gets hosed */
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p0.h = hi(UART_LCR);
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p0.l = lo(UART_LCR);
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p0.h = hi(BFIN_UART_LCR);
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p0.l = lo(BFIN_UART_LCR);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable DLL writes */
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ssync;
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p0.h = hi(UART_DLL);
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p0.l = lo(UART_DLL);
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p0.h = hi(BFIN_UART_DLL);
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p0.l = lo(BFIN_UART_DLL);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_DLH);
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p0.l = lo(UART_DLH);
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p0.h = hi(BFIN_UART_DLH);
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p0.l = lo(BFIN_UART_DLH);
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r0 = 0x00(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_GCTL);
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p0.l = lo(UART_GCTL);
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p0.h = hi(BFIN_UART_GCTL);
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p0.l = lo(BFIN_UART_GCTL);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable UART clock */
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ssync;
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@ -139,26 +139,26 @@ ENTRY(__start)
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/* Initialise UART - when booting from u-boot, the UART is not disabled
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* so if we dont initalize here, our serial console gets hosed */
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p0.h = hi(UART_LCR);
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p0.l = lo(UART_LCR);
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p0.h = hi(BFIN_UART_LCR);
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p0.l = lo(BFIN_UART_LCR);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable DLL writes */
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ssync;
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p0.h = hi(UART_DLL);
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p0.l = lo(UART_DLL);
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p0.h = hi(BFIN_UART_DLL);
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p0.l = lo(BFIN_UART_DLL);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_DLH);
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p0.l = lo(UART_DLH);
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p0.h = hi(BFIN_UART_DLH);
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p0.l = lo(BFIN_UART_DLH);
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r0 = 0x00(Z);
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w[p0] = r0.L;
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ssync;
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p0.h = hi(UART_GCTL);
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p0.l = lo(UART_GCTL);
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p0.h = hi(BFIN_UART_GCTL);
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p0.l = lo(BFIN_UART_GCTL);
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r0 = 0x0(Z);
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w[p0] = r0.L; /* To enable UART clock */
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ssync;
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@ -88,20 +88,25 @@
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
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/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART_THR 0xFFC00400 /* Transmit Holding register */
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#define UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART_LCR 0xFFC0040C /* Line Control Register */
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#define UART_MCR 0xFFC00410 /* Modem Control Register */
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#define UART_LSR 0xFFC00414 /* Line Status Register */
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/*
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* Because include/linux/serial_reg.h have defined UART_*,
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* So we define blackfin uart regs to BFIN_UART_*.
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*/
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#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
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#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
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#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
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#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
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#if 0
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#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
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#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
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#endif
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#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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@ -82,8 +82,6 @@
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#define STATUS_P1 0x02
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#define STATUS_P0 0x01
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/* UART 0*/
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/* DMA Channnel */
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#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
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#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
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@ -106,37 +104,37 @@
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/* MMR Registers*/
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#define bfin_read_UART_THR() bfin_read_UART0_THR()
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#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
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#define UART_THR UART0_THR
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#define BFIN_UART_THR UART0_THR
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#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
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#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
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#define UART_RBR UART0_RBR
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#define BFIN_UART_RBR UART0_RBR
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#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
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#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
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#define UART_DLL UART0_DLL
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#define BFIN_UART_DLL UART0_DLL
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#define bfin_read_UART_IER() bfin_read_UART0_IER()
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#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
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#define UART_IER UART0_IER
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#define BFIN_UART_IER UART0_IER
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#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
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#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
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#define UART_DLH UART0_DLH
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#define BFIN_UART_DLH UART0_DLH
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#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
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#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
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#define UART_IIR UART0_IIR
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#define BFIN_UART_IIR UART0_IIR
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#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
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#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
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#define UART_LCR UART0_LCR
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#define BFIN_UART_LCR UART0_LCR
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#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
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#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
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#define UART_MCR UART0_MCR
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#define BFIN_UART_MCR UART0_MCR
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#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
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#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
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#define UART_LSR UART0_LSR
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#define BFIN_UART_LSR UART0_LSR
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#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
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#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
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#define UART_SCR UART0_SCR
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#define BFIN_UART_SCR UART0_SCR
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#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
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#define UART_GCTL UART0_GCTL
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#define BFIN_UART_GCTL UART0_GCTL
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/* DPMC*/
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#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
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@ -153,17 +153,18 @@
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#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
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#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
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#define UART_THR UART1_THR
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#define UART_RBR UART1_RBR
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#define UART_DLL UART1_DLL
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#define UART_IER UART1_IER
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#define UART_DLH UART1_DLH
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#define UART_IIR UART1_IIR
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#define UART_LCR UART1_LCR
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#define UART_MCR UART1_MCR
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#define UART_LSR UART1_LSR
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#define UART_SCR UART1_SCR
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#define UART_GCTL UART1_GCTL
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#define BFIN_UART_THR UART1_THR
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#define BFIN_UART_RBR UART1_RBR
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#define BFIN_UART_DLL UART1_DLL
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#define BFIN_UART_IER UART1_IER
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#define BFIN_UART_DLH UART1_DLH
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#define BFIN_UART_IIR UART1_IIR
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#define BFIN_UART_LCR UART1_LCR
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#define BFIN_UART_MCR UART1_MCR
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#define BFIN_UART_LSR UART1_LSR
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#define BFIN_UART_SCR UART1_SCR
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#define BFIN_UART_GCTL UART1_GCTL
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/* PLL_DIV Masks */
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#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
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@ -110,18 +110,23 @@
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#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
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/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART_THR 0xFFC00400 /* Transmit Holding register */
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#define UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART_LCR 0xFFC0040C /* Line Control Register */
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#define UART_MCR 0xFFC00410 /* Modem Control Register */
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#define UART_LSR 0xFFC00414 /* Line Status Register */
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#define UART_MSR 0xFFC00418 /* Modem Status Register */
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#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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/*
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* Because include/linux/serial_reg.h have defined UART_*,
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* So we define blackfin uart regs to BFIN_UART0_*.
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*/
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#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
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#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
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#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
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#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
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#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
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#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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