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dt-bindings: PCI: meson: Update PCIE bindings documentation

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Now that a new PHYs has been introduced for AXG SoC family, update
dt bindings documentation.

Please note that this breaks backward compatibility but as not a single
devicetree uses that yet that seems ok.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Remi Pommarel 2020-01-24 00:29:39 +01:00 committed by Lorenzo Pieralisi
parent b09b48b3d0
commit 6e5f77031c
1 changed files with 9 additions and 13 deletions
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22
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
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@ -18,7 +18,6 @@ Required properties:
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@ -26,13 +25,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
- reset-names: must contain "phy" "port" and "apb"
- "phy" Share PHY reset for AXG SoC Family
- reset-names: must contain "port" and "apb"
- "port" Port A or B reset
- "apb" Share APB reset
- phys: should contain a phandle to the shared phy for G12A SoC Family
- phys: should contain a phandle to the PCIE phy
- phy-names: must contain "pcie"
- device_type:
should be "pci". As specified in designware-pcie.txt
@ -43,9 +42,8 @@ Example configuration:
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xf9800000 0x0 0x400000
0x0 0xff646000 0x0 0x2000
0x0 0xff644000 0x0 0x2000
0x0 0xf9f00000 0x0 0x100000>;
reg-names = "elbi", "cfg", "phy", "config";
reg-names = "elbi", "cfg", "config";
reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
@ -58,17 +56,15 @@ Example configuration:
ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
clocks = <&clkc CLKID_USB
&clkc CLKID_MIPI_ENABLE
&clkc CLKID_PCIE_A
&clkc CLKID_PCIE_CML_EN0>;
clock-names = "general",
"mipi",
"pclk",
"port";
resets = <&reset RESET_PCIE_PHY>,
<&reset RESET_PCIE_A>,
resets = <&reset RESET_PCIE_A>,
<&reset RESET_PCIE_APB>;
reset-names = "phy",
"port",
reset-names = "port",
"apb";
phys = <&pcie_phy>;
phy-names = "pcie";
};