mirror of
https://github.com/torvalds/linux.git
synced 2024-11-22 12:11:40 +00:00
just cleanups and fixes
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This commit is contained in:
Linus Torvalds
commit
6e51b4b5bb
@ -35,6 +35,7 @@
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#include <asm/bootinfo.h>
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#include <bcm47xx.h>
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#include <bcm47xx_board.h>
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#include "bcm47xx_private.h"
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static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
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@ -123,7 +124,7 @@ void __init prom_init(void)
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/* Stripped version of tlb_init, with the call to build_tlb_refill_handler
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* dropped. Calling it at this stage causes a hang.
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*/
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void early_tlb_init(void)
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static void early_tlb_init(void)
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{
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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@ -5,50 +5,143 @@
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#include <dt-bindings/reset/mt7621-reset.h>
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/ {
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compatible = "mediatek,mt7621-soc";
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7621-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <0>;
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device_type = "cpu";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "mips,mips1004Kc";
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reg = <1>;
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device_type = "cpu";
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};
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};
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cpuintc: cpuintc {
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compatible = "mti,cpu-interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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mmc_fixed_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "mmc_power";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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regulator-always-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "mmc_power";
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};
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mmc_fixed_1v8_io: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "mmc_io";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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regulator-always-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "mmc_io";
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};
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pinctrl: pinctrl {
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compatible = "ralink,mt7621-pinctrl";
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i2c_pins: i2c0-pins {
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pinmux {
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groups = "i2c";
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function = "i2c";
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};
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};
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mdio_pins: mdio0-pins {
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pinmux {
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groups = "mdio";
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function = "mdio";
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};
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};
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nand_pins: nand0-pins {
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sdhci-pinmux {
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groups = "sdhci";
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function = "nand2";
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};
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spi-pinmux {
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groups = "spi";
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function = "nand1";
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};
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};
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pcie_pins: pcie0-pins {
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pinmux {
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groups = "pcie";
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function = "gpio";
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};
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};
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rgmii1_pins: rgmii1-pins {
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pinmux {
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groups = "rgmii1";
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function = "rgmii1";
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};
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};
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rgmii2_pins: rgmii2-pins {
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pinmux {
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groups = "rgmii2";
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function = "rgmii2";
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};
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};
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sdhci_pins: sdhci0-pins {
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pinmux {
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groups = "sdhci";
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function = "sdhci";
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};
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};
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spi_pins: spi0-pins {
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pinmux {
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groups = "spi";
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function = "spi";
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};
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};
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uart1_pins: uart1-pins {
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pinmux {
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groups = "uart1";
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function = "uart1";
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};
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};
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uart2_pins: uart2-pins {
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pinmux {
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groups = "uart2";
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function = "uart2";
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};
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};
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uart3_pins: uart3-pins {
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pinmux {
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groups = "uart3";
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function = "uart3";
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};
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};
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};
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palmbus: palmbus@1e000000 {
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@ -62,12 +155,15 @@
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sysc: syscon@0 {
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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"250m", "270m";
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ralink,memctl = <&memc>;
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};
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wdt: watchdog@100 {
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@ -77,13 +173,16 @@
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};
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gpio: gpio@600 {
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compatible = "mediatek,mt7621-gpio";
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reg = <0x600 0x100>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "mediatek,mt7621-gpio";
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 95>;
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interrupt-controller;
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reg = <0x600 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -92,18 +191,19 @@
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compatible = "mediatek,mt7621-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysc MT7621_CLK_I2C>;
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clock-names = "i2c";
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resets = <&sysc MT7621_RST_I2C>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&sysc MT7621_CLK_I2C>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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resets = <&sysc MT7621_RST_I2C>;
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reset-names = "i2c";
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status = "disabled";
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};
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memc: memory-controller@5000 {
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@ -170,135 +270,53 @@
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};
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spi0: spi@b00 {
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status = "disabled";
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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clocks = <&sysc MT7621_CLK_SPI>;
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clock-names = "spi";
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resets = <&sysc MT7621_RST_SPI>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "spi";
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clocks = <&sysc MT7621_CLK_SPI>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,mt7621-pinctrl";
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reset-names = "spi";
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resets = <&sysc MT7621_RST_SPI>;
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i2c_pins: i2c0-pins {
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pinmux {
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groups = "i2c";
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function = "i2c";
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};
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};
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spi_pins: spi0-pins {
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pinmux {
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groups = "spi";
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function = "spi";
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};
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};
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uart1_pins: uart1-pins {
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pinmux {
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groups = "uart1";
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function = "uart1";
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};
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};
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uart2_pins: uart2-pins {
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pinmux {
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groups = "uart2";
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function = "uart2";
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};
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};
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uart3_pins: uart3-pins {
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pinmux {
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groups = "uart3";
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function = "uart3";
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};
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};
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rgmii1_pins: rgmii1-pins {
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pinmux {
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groups = "rgmii1";
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function = "rgmii1";
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};
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};
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rgmii2_pins: rgmii2-pins {
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pinmux {
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groups = "rgmii2";
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function = "rgmii2";
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};
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};
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mdio_pins: mdio0-pins {
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pinmux {
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groups = "mdio";
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function = "mdio";
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};
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};
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pcie_pins: pcie0-pins {
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pinmux {
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groups = "pcie";
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function = "gpio";
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};
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};
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nand_pins: nand0-pins {
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spi-pinmux {
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groups = "spi";
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function = "nand1";
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};
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sdhci-pinmux {
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groups = "sdhci";
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function = "nand2";
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};
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};
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sdhci_pins: sdhci0-pins {
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pinmux {
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groups = "sdhci";
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function = "sdhci";
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};
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status = "disabled";
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};
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};
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mmc: mmc@1e130000 {
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status = "disabled";
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compatible = "mediatek,mt7620-mmc";
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reg = <0x1e130000 0x4000>;
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bus-width = <4>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&mmc_fixed_3v3>;
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vqmmc-supply = <&mmc_fixed_1v8_io>;
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disable-wp;
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&sdhci_pins>;
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pinctrl-1 = <&sdhci_pins>;
|
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cap-mmc-highspeed;
|
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cap-sd-highspeed;
|
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|
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clocks = <&sysc MT7621_CLK_SHXC>,
|
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<&sysc MT7621_CLK_50M>;
|
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clock-names = "source", "hclk";
|
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|
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disable-wp;
|
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interrupt-parent = <&gic>;
|
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
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max-frequency = <48000000>;
|
||||
|
||||
pinctrl-names = "default", "state_uhs";
|
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pinctrl-0 = <&sdhci_pins>;
|
||||
pinctrl-1 = <&sdhci_pins>;
|
||||
|
||||
vmmc-supply = <&mmc_fixed_3v3>;
|
||||
vqmmc-supply = <&mmc_fixed_1v8_io>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@1e1c0000 {
|
||||
@ -321,15 +339,15 @@
|
||||
compatible = "mti,gic";
|
||||
reg = <0x1fbc0000 0x2000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
|
||||
mti,reserved-cpu-vectors = <7>;
|
||||
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
clocks = <&sysc MT7621_CLK_CPU>;
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -347,46 +365,22 @@
|
||||
compatible = "mediatek,mt7621-eth";
|
||||
reg = <0x1e100000 0x10000>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
|
||||
clock-names = "fe", "ethif";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
|
||||
reset-names = "fe", "eth";
|
||||
clock-names = "fe", "ethif";
|
||||
clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
mediatek,ethsys = <&sysc>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "trgmii";
|
||||
reset-names = "fe", "eth";
|
||||
resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
mediatek,ethsys = <&sysc>;
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
@ -395,73 +389,105 @@
|
||||
switch0: switch@1f {
|
||||
compatible = "mediatek,mt7621";
|
||||
reg = <0x1f>;
|
||||
mediatek,mcm;
|
||||
resets = <&sysc MT7621_RST_MCM>;
|
||||
reset-names = "mcm";
|
||||
interrupt-controller;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
reset-names = "mcm";
|
||||
resets = <&sysc MT7621_RST_MCM>;
|
||||
|
||||
mediatek,mcm;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
status = "disabled";
|
||||
reg = <0>;
|
||||
label = "swp0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "disabled";
|
||||
reg = <1>;
|
||||
label = "swp1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "disabled";
|
||||
reg = <2>;
|
||||
label = "swp2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "disabled";
|
||||
reg = <3>;
|
||||
label = "swp3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
status = "disabled";
|
||||
reg = <4>;
|
||||
label = "swp4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
speed = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "trgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
speed = <1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
|
||||
phy-mode = "trgmii";
|
||||
|
||||
fixed-link {
|
||||
full-duplex;
|
||||
pause;
|
||||
speed = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
full-duplex;
|
||||
pause;
|
||||
speed = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pcie: pcie@1e140000 {
|
||||
@ -470,84 +496,106 @@
|
||||
<0x1e142000 0x100>, /* pcie port 0 RC control registers */
|
||||
<0x1e143000 0x100>, /* pcie port 1 RC control registers */
|
||||
<0x1e144000 0x100>; /* pcie port 2 RC control registers */
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
|
||||
<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
|
||||
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xF800 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 0>;
|
||||
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
|
||||
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ranges;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_PCIE0>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&sysc MT7621_RST_PCIE0>;
|
||||
clocks = <&sysc MT7621_CLK_PCIE0>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
|
||||
phy-names = "pcie-phy0";
|
||||
ranges;
|
||||
phys = <&pcie0_phy 1>;
|
||||
|
||||
resets = <&sysc MT7621_RST_PCIE0>;
|
||||
};
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
ranges;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_PCIE1>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&sysc MT7621_RST_PCIE1>;
|
||||
clocks = <&sysc MT7621_CLK_PCIE1>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
|
||||
phy-names = "pcie-phy1";
|
||||
ranges;
|
||||
phys = <&pcie0_phy 1>;
|
||||
|
||||
resets = <&sysc MT7621_RST_PCIE1>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
ranges;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_PCIE2>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&sysc MT7621_RST_PCIE2>;
|
||||
clocks = <&sysc MT7621_CLK_PCIE2>;
|
||||
phys = <&pcie2_phy 0>;
|
||||
|
||||
phy-names = "pcie-phy2";
|
||||
ranges;
|
||||
phys = <&pcie2_phy 0>;
|
||||
|
||||
resets = <&sysc MT7621_RST_PCIE2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_phy: pcie-phy@1e149000 {
|
||||
compatible = "mediatek,mt7621-pci-phy";
|
||||
reg = <0x1e149000 0x0700>;
|
||||
clocks = <&sysc MT7621_CLK_XTAL>;
|
||||
|
||||
#phy-cells = <1>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_XTAL>;
|
||||
};
|
||||
|
||||
pcie2_phy: pcie-phy@1e14a000 {
|
||||
compatible = "mediatek,mt7621-pci-phy";
|
||||
reg = <0x1e14a000 0x0700>;
|
||||
clocks = <&sysc MT7621_CLK_XTAL>;
|
||||
|
||||
#phy-cells = <1>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_XTAL>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -37,6 +37,7 @@
|
||||
#define CFI_SECTIONS
|
||||
#endif
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
/*
|
||||
* LEAF - declare leaf routine
|
||||
*/
|
||||
@ -122,6 +123,8 @@ symbol = value
|
||||
#define ASM_PRINT(string)
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Stack alignment
|
||||
*/
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
#ifndef _MIPS_SETUP_H
|
||||
#define _MIPS_SETUP_H
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <uapi/asm/setup.h>
|
||||
|
||||
@ -29,4 +30,9 @@ extern void per_cpu_trap_init(bool);
|
||||
extern void cpu_cache_init(void);
|
||||
extern void tlb_init(void);
|
||||
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
extern void * __init relocate_kernel(void);
|
||||
extern int plat_post_relocation(long);
|
||||
#endif
|
||||
|
||||
#endif /* __SETUP_H */
|
||||
|
||||
@ -308,17 +308,12 @@
|
||||
jal octeon_mult_restore
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_HAS_SMARTMIPS
|
||||
LONG_L $24, PT_ACX(sp)
|
||||
mtlhx $24
|
||||
LONG_L $24, PT_HI(sp)
|
||||
mtlhx $24
|
||||
LONG_L $14, PT_ACX(sp)
|
||||
LONG_L $24, PT_LO(sp)
|
||||
mtlhx $24
|
||||
LONG_L $15, PT_HI(sp)
|
||||
#elif !defined(CONFIG_CPU_MIPSR6)
|
||||
LONG_L $24, PT_LO(sp)
|
||||
mtlo $24
|
||||
LONG_L $24, PT_HI(sp)
|
||||
mthi $24
|
||||
LONG_L $15, PT_HI(sp)
|
||||
#endif
|
||||
#ifdef CONFIG_32BIT
|
||||
cfi_ld $8, PT_R8, \docfi
|
||||
@ -327,6 +322,14 @@
|
||||
cfi_ld $10, PT_R10, \docfi
|
||||
cfi_ld $11, PT_R11, \docfi
|
||||
cfi_ld $12, PT_R12, \docfi
|
||||
#ifdef CONFIG_CPU_HAS_SMARTMIPS
|
||||
mtlhx $14
|
||||
mtlhx $15
|
||||
mtlhx $24
|
||||
#elif !defined(CONFIG_CPU_MIPSR6)
|
||||
mtlo $24
|
||||
mthi $15
|
||||
#endif
|
||||
cfi_ld $13, PT_R13, \docfi
|
||||
cfi_ld $14, PT_R14, \docfi
|
||||
cfi_ld $15, PT_R15, \docfi
|
||||
|
||||
6
arch/mips/pci/pcie-octeon.c
Normal file → Executable file
6
arch/mips/pci/pcie-octeon.c
Normal file → Executable file
@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
|
||||
{
|
||||
union cvmx_pcie_address pcie_addr;
|
||||
union cvmx_pciercx_cfg006 pciercx_cfg006;
|
||||
union cvmx_pciercx_cfg032 pciercx_cfg032;
|
||||
|
||||
pciercx_cfg006.u32 =
|
||||
cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
|
||||
if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
|
||||
return 0;
|
||||
|
||||
pciercx_cfg032.u32 =
|
||||
cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
|
||||
if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1))
|
||||
return 0;
|
||||
|
||||
pcie_addr.u64 = 0;
|
||||
pcie_addr.config.upper = 2;
|
||||
pcie_addr.config.io = 1;
|
||||
|
||||
@ -197,7 +197,7 @@ void rb532_gpio_set_func(unsigned gpio)
|
||||
}
|
||||
EXPORT_SYMBOL(rb532_gpio_set_func);
|
||||
|
||||
int __init rb532_gpio_init(void)
|
||||
static int __init rb532_gpio_init(void)
|
||||
{
|
||||
struct resource *r;
|
||||
|
||||
|
||||
@ -46,7 +46,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
|
||||
return simple_strtoul(num, 0, 10);
|
||||
}
|
||||
|
||||
void __init prom_setup_cmdline(void)
|
||||
static void __init prom_setup_cmdline(void)
|
||||
{
|
||||
static char cmd_line[COMMAND_LINE_SIZE] __initdata;
|
||||
char *cp, *board;
|
||||
|
||||
@ -277,7 +277,6 @@ void __init arch_init_irq(void)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
struct fwnode_handle *fn;
|
||||
int i;
|
||||
|
||||
mips_cpu_irq_init();
|
||||
|
||||
@ -286,20 +285,16 @@ void __init arch_init_irq(void)
|
||||
* Mark these as reserved right away so they won't be used accidentally
|
||||
* later.
|
||||
*/
|
||||
for (i = 0; i <= CPU_CALL_B_IRQ; i++)
|
||||
set_bit(i, hub_irq_map);
|
||||
|
||||
for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)
|
||||
set_bit(i, hub_irq_map);
|
||||
bitmap_set(hub_irq_map, 0, CPU_CALL_B_IRQ + 1);
|
||||
bitmap_set(hub_irq_map, NI_BRDCAST_ERR_A, MSC_PANIC_INTR - NI_BRDCAST_ERR_A + 1);
|
||||
|
||||
fn = irq_domain_alloc_named_fwnode("HUB");
|
||||
WARN_ON(fn == NULL);
|
||||
if (!fn)
|
||||
if (WARN_ON(fn == NULL))
|
||||
return;
|
||||
|
||||
domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT,
|
||||
&hub_domain_ops, NULL);
|
||||
WARN_ON(domain == NULL);
|
||||
if (!domain)
|
||||
if (WARN_ON(domain == NULL))
|
||||
return;
|
||||
|
||||
irq_set_default_host(domain);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user