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staging: fsl-dpaa2/eth: Add Freescale DPAA2 Ethernet driver
Introduce the DPAA2 Ethernet driver, which manages Datapath Network Interface (DPNI) objects discovered on the MC bus. In addition to DPNIs, the Ethernet driver uses several other MC objects to build a network interface abstraction: buffer pools (DPBPs), I/O Portals (DPIOs) and concentrators (DPCONs). A more detailed description of the driver can be found in the associated README file. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ioana Radulescu
Greg Kroah-Hartman
parent
0352d1d852
commit
6e2387e8f1
@ -4,4 +4,4 @@
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obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o
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obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o
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fsl-dpaa2-eth-objs := dpni.o
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fsl-dpaa2-eth-objs := dpaa2-eth.o dpni.o
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2455
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
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2455
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
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Load Diff
304
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
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drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
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/* Copyright 2014-2016 Freescale Semiconductor Inc.
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* Copyright 2016 NXP
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DPAA2_ETH_H
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#define __DPAA2_ETH_H
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include "../../fsl-mc/include/dpaa2-io.h"
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#include "../../fsl-mc/include/dpaa2-fd.h"
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#include "../../fsl-mc/include/dpbp.h"
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#include "../../fsl-mc/include/dpcon.h"
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#include "dpni.h"
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#include "dpni-cmd.h"
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#define DPAA2_ETH_STORE_SIZE 16
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/* Maximum number of scatter-gather entries in an ingress frame,
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* considering the maximum receive frame size is 64K
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*/
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#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
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/* Maximum acceptable MTU value. It is in direct relation with the hardware
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* enforced Max Frame Length (currently 10k).
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*/
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#define DPAA2_ETH_MFL (10 * 1024)
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#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
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/* Convert L3 MTU to L2 MFL */
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#define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
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/* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
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* frames in the Rx queues (length of the current frame is not
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* taken into account when making the taildrop decision)
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*/
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#define DPAA2_ETH_TAILDROP_THRESH (64 * 1024)
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/* Buffer quota per queue. Must be large enough such that for minimum sized
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* frames taildrop kicks in before the bpool gets depleted, so we compute
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* how many 64B frames fit inside the taildrop threshold and add a margin
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* to accommodate the buffer refill delay.
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*/
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#define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64)
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#define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
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#define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE
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/* Maximum number of buffers that can be acquired/released through a single
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* QBMan command
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*/
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#define DPAA2_ETH_BUFS_PER_CMD 7
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/* Hardware requires alignment for ingress/egress buffer addresses
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* and ingress buffer lengths.
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*/
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#define DPAA2_ETH_RX_BUF_SIZE 2048
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#define DPAA2_ETH_TX_BUF_ALIGN 64
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#define DPAA2_ETH_RX_BUF_ALIGN 256
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#define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \
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((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN)
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/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress
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* buffers large enough to allow building an skb around them and also account
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* for alignment restrictions
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*/
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#define DPAA2_ETH_BUF_RAW_SIZE \
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(DPAA2_ETH_RX_BUF_SIZE + \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \
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DPAA2_ETH_RX_BUF_ALIGN)
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/* We are accommodating a skb backpointer and some S/G info
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* in the frame's software annotation. The hardware
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* options are either 0 or 64, so we choose the latter.
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*/
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#define DPAA2_ETH_SWA_SIZE 64
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/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
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struct dpaa2_eth_swa {
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struct sk_buff *skb;
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struct scatterlist *scl;
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int num_sg;
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int num_dma_bufs;
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};
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/* Annotation valid bits in FD FRC */
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#define DPAA2_FD_FRC_FASV 0x8000
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#define DPAA2_FD_FRC_FAEADV 0x4000
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#define DPAA2_FD_FRC_FAPRV 0x2000
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#define DPAA2_FD_FRC_FAIADV 0x1000
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#define DPAA2_FD_FRC_FASWOV 0x0800
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#define DPAA2_FD_FRC_FAICFDV 0x0400
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/* Annotation bits in FD CTRL */
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#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
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#define DPAA2_FD_CTRL_PTA 0x00800000
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#define DPAA2_FD_CTRL_PTV1 0x00400000
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/* Frame annotation status */
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struct dpaa2_fas {
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u8 reserved;
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u8 ppid;
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__le16 ifpid;
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__le32 status;
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} __packed;
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/* Frame annotation status word is located in the first 8 bytes
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* of the buffer's hardware annoatation area
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*/
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#define DPAA2_FAS_OFFSET 0
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#define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
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/* Error and status bits in the frame annotation status word */
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/* Debug frame, otherwise supposed to be discarded */
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#define DPAA2_FAS_DISC 0x80000000
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/* MACSEC frame */
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#define DPAA2_FAS_MS 0x40000000
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#define DPAA2_FAS_PTP 0x08000000
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/* Ethernet multicast frame */
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#define DPAA2_FAS_MC 0x04000000
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/* Ethernet broadcast frame */
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#define DPAA2_FAS_BC 0x02000000
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#define DPAA2_FAS_KSE 0x00040000
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#define DPAA2_FAS_EOFHE 0x00020000
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#define DPAA2_FAS_MNLE 0x00010000
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#define DPAA2_FAS_TIDE 0x00008000
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#define DPAA2_FAS_PIEE 0x00004000
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/* Frame length error */
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#define DPAA2_FAS_FLE 0x00002000
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/* Frame physical error */
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#define DPAA2_FAS_FPE 0x00001000
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#define DPAA2_FAS_PTE 0x00000080
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#define DPAA2_FAS_ISP 0x00000040
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#define DPAA2_FAS_PHE 0x00000020
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#define DPAA2_FAS_BLE 0x00000010
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/* L3 csum validation performed */
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#define DPAA2_FAS_L3CV 0x00000008
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/* L3 csum error */
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#define DPAA2_FAS_L3CE 0x00000004
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/* L4 csum validation performed */
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#define DPAA2_FAS_L4CV 0x00000002
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/* L4 csum error */
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#define DPAA2_FAS_L4CE 0x00000001
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/* Possible errors on the ingress path */
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#define DPAA2_ETH_RX_ERR_MASK (DPAA2_FAS_KSE | \
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DPAA2_FAS_EOFHE | \
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DPAA2_FAS_MNLE | \
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DPAA2_FAS_TIDE | \
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DPAA2_FAS_PIEE | \
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DPAA2_FAS_FLE | \
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DPAA2_FAS_FPE | \
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DPAA2_FAS_PTE | \
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DPAA2_FAS_ISP | \
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DPAA2_FAS_PHE | \
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DPAA2_FAS_BLE | \
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DPAA2_FAS_L3CE | \
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DPAA2_FAS_L4CE)
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/* Tx errors */
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#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_FAS_KSE | \
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DPAA2_FAS_EOFHE | \
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DPAA2_FAS_MNLE | \
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DPAA2_FAS_TIDE)
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/* Time in milliseconds between link state updates */
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#define DPAA2_ETH_LINK_STATE_REFRESH 1000
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/* Number of times to retry a frame enqueue before giving up.
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* Value determined empirically, in order to minimize the number
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* of frames dropped on Tx
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*/
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#define DPAA2_ETH_ENQUEUE_RETRIES 10
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/* Maximum number of queues associated with a DPNI */
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#define DPAA2_ETH_MAX_RX_QUEUES 16
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#define DPAA2_ETH_MAX_TX_QUEUES NR_CPUS
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#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
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DPAA2_ETH_MAX_TX_QUEUES)
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#define DPAA2_ETH_MAX_DPCONS NR_CPUS
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enum dpaa2_eth_fq_type {
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DPAA2_RX_FQ = 0,
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DPAA2_TX_CONF_FQ,
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};
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struct dpaa2_eth_priv;
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struct dpaa2_eth_fq {
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u32 fqid;
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u32 tx_qdbin;
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u16 flowid;
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int target_cpu;
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struct dpaa2_eth_channel *channel;
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enum dpaa2_eth_fq_type type;
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void (*consume)(struct dpaa2_eth_priv *,
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struct dpaa2_eth_channel *,
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const struct dpaa2_fd *,
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struct napi_struct *);
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};
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struct dpaa2_eth_channel {
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struct dpaa2_io_notification_ctx nctx;
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struct fsl_mc_device *dpcon;
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int dpcon_id;
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int ch_id;
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int dpio_id;
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struct napi_struct napi;
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struct dpaa2_io_store *store;
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struct dpaa2_eth_priv *priv;
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int buf_count;
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};
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struct dpaa2_eth_hash_fields {
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u64 rxnfc_field;
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enum net_prot cls_prot;
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int cls_field;
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int size;
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};
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/* Driver private data */
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struct dpaa2_eth_priv {
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struct net_device *net_dev;
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u8 num_fqs;
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struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
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u8 num_channels;
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struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
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int dpni_id;
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struct dpni_attr dpni_attrs;
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/* Insofar as the MC is concerned, we're using one layout on all 3 types
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* of buffers (Rx, Tx, Tx-Conf).
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*/
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struct dpni_buffer_layout buf_layout;
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u16 tx_data_offset;
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struct fsl_mc_device *dpbp_dev;
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struct dpbp_attr dpbp_attrs;
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u16 tx_qdid;
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struct fsl_mc_io *mc_io;
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/* Cores which have an affine DPIO/DPCON.
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* This is the cpu set on which Rx and Tx conf frames are processed
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*/
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struct cpumask dpio_cpumask;
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/* Standard statistics */
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struct rtnl_link_stats64 __percpu *percpu_stats;
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u16 mc_token;
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struct dpni_link_state link_state;
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bool do_link_poll;
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struct task_struct *poll_thread;
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};
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/* default Rx hash options, set during probing */
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#define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
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| RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
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| RXH_L4_B_2_3)
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#define dpaa2_eth_hash_enabled(priv) \
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((priv)->dpni_attrs.num_queues > 1)
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/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
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#define DPAA2_CLASSIFIER_DMA_SIZE 256
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int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
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static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
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{
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return priv->dpni_attrs.num_queues;
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}
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#endif /* __DPAA2_H */
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