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MIPS: KVM: Emulate FPU bits in COP0 interface
Emulate FPU related parts of COP0 interface so that the guest will be able to enable/disable the following once the FPU capability has been wired up: - The FPU (Status.CU1) - 64-bit FP register mode (Status.FR) - Hybrid FP register mode (Config5.FRE) Changing Status.CU1 has no immediate effect if the FPU state isn't live, as the FPU state is restored lazily on first use. After that, changes take place immediately in the host Status.CU1, so that the guest can start getting coprocessor unusable exceptions right away for guest FPU operations if it is disabled. The FPU state is saved lazily too, as the FPU may get re-enabled in the near future anyway. Any change to Status.FR causes the FPU state to be discarded and FPU disabled, as the register state is architecturally UNPREDICTABLE after such a change. This should also ensure that the FPU state is fully initialised (with stale state, but that's fine) when it is next used in the new FP mode. Any change to the Config5.FRE bit is immediately updated in the host state so that the guest can get the relevant exceptions right away for single-precision FPU operations. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
This commit is contained in:
James Hogan
parent
98e91b8457
commit
6cdc65e31d
@ -893,8 +893,13 @@ enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
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*/
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unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
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{
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/* Read-only */
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return 0;
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unsigned int mask = 0;
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/* Permit FPU to be present if FPU is supported */
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if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
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mask |= MIPS_CONF1_FP;
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return mask;
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}
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/**
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@ -932,8 +937,19 @@ unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
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*/
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unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
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{
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/* Read-only */
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return 0;
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unsigned int mask = 0;
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/*
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* Permit guest FPU mode changes if FPU is enabled and the relevant
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* feature exists according to FIR register.
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*/
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if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
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if (cpu_has_fre)
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mask |= MIPS_CONF5_FRE;
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/* We don't support UFR or UFE */
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}
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return mask;
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}
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enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
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@ -1073,18 +1089,91 @@ enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
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kvm_mips_write_compare(vcpu,
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vcpu->arch.gprs[rt]);
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} else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
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kvm_write_c0_guest_status(cop0,
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vcpu->arch.gprs[rt]);
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unsigned int old_val, val, change;
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old_val = kvm_read_c0_guest_status(cop0);
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val = vcpu->arch.gprs[rt];
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change = val ^ old_val;
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/* Make sure that the NMI bit is never set */
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val &= ~ST0_NMI;
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/*
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* Make sure that CU1 and NMI bits are
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* never set
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* Don't allow CU1 or FR to be set unless FPU
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* capability enabled and exists in guest
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* configuration.
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*/
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kvm_clear_c0_guest_status(cop0,
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(ST0_CU1 | ST0_NMI));
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if (!kvm_mips_guest_has_fpu(&vcpu->arch))
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val &= ~(ST0_CU1 | ST0_FR);
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/*
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* Also don't allow FR to be set if host doesn't
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* support it.
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*/
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if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
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val &= ~ST0_FR;
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/* Handle changes in FPU mode */
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preempt_disable();
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/*
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* FPU and Vector register state is made
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* UNPREDICTABLE by a change of FR, so don't
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* even bother saving it.
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*/
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if (change & ST0_FR)
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kvm_drop_fpu(vcpu);
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/*
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* Propagate CU1 (FPU enable) changes
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* immediately if the FPU context is already
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* loaded. When disabling we leave the context
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* loaded so it can be quickly enabled again in
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* the near future.
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*/
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if (change & ST0_CU1 &&
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vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
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change_c0_status(ST0_CU1, val);
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preempt_enable();
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kvm_write_c0_guest_status(cop0, val);
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#ifdef CONFIG_KVM_MIPS_DYN_TRANS
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kvm_mips_trans_mtc0(inst, opc, vcpu);
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/*
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* If FPU present, we need CU1/FR bits to take
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* effect fairly soon.
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*/
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if (!kvm_mips_guest_has_fpu(&vcpu->arch))
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kvm_mips_trans_mtc0(inst, opc, vcpu);
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#endif
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} else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
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unsigned int old_val, val, change, wrmask;
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old_val = kvm_read_c0_guest_config5(cop0);
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val = vcpu->arch.gprs[rt];
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/* Only a few bits are writable in Config5 */
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wrmask = kvm_mips_config5_wrmask(vcpu);
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change = (val ^ old_val) & wrmask;
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val = old_val ^ change;
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/* Handle changes in FPU modes */
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preempt_disable();
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/*
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* Propagate FRE changes immediately if the FPU
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* context is already loaded.
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*/
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if (change & MIPS_CONF5_FRE &&
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vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
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change_c0_config5(MIPS_CONF5_FRE, val);
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preempt_enable();
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kvm_write_c0_guest_config5(cop0, val);
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} else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
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uint32_t old_cause, new_cause;
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