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ARM: clps711x: make all virtual addresses definition via one macro

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This patch make all virtual addresses definition via one macro.
This modification allows to avoid warning "BUG: mapping for 0x80000000
at 0xff000000 out of vmalloc space".

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Alexander Shiyan 2012-10-10 19:45:31 +04:00 committed by Arnd Bergmann
parent 36504ac131
commit 6cb1b145b9
8 changed files with 38 additions and 94 deletions
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13
arch/arm/mach-clps711x/autcpu12.c
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@ -39,19 +39,10 @@
#include "common.h"
/*
* The on-chip registers are given a size of 1MB so that a section can
* be used to map them; this saves a page table. This is the place to
* add mappings for ROM, expansion memory, PCMCIA, etc. (if static
* mappings are chosen for those areas).
*
*/
static struct map_desc autcpu12_io_desc[] __initdata = {
/* memory-mapped extra io and CS8900A Ethernet chip */
/* ethernet chip */
/* Memory-mapped extra io and CS8900A Ethernet chip */
{
.virtual = AUTCPU12_VIRT_CS8900A,
.virtual = IO_ADDRESS(AUTCPU12_PHYS_CS8900A),
.pfn = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE

4
arch/arm/mach-clps711x/cdb89712.c
View File

@ -40,8 +40,8 @@
*/
static struct map_desc cdb89712_io_desc[] __initdata = {
{
.virtual = ETHER_BASE,
.pfn =__phys_to_pfn(ETHER_START),
.virtual = IO_ADDRESS(ETHER_PHYS_BASE),
.pfn = __phys_to_pfn(ETHER_PHYS_BASE),
.length = ETHER_SIZE,
.type = MT_DEVICE
}

2
arch/arm/mach-clps711x/common.c
View File

@ -45,7 +45,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
{
.virtual = (unsigned long)CLPS711X_VIRT_BASE,
.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
.length = SZ_1M,
.length = SZ_64K,
.type = MT_DEVICE
}
};

16
arch/arm/mach-clps711x/edb7211-mm.c
View File

@ -51,23 +51,23 @@ extern void clps711x_map_io(void);
* happens).
*/
static struct map_desc edb7211_io_desc[] __initdata = {
{ /* memory-mapped extra keyboard row */
.virtual = EP7211_VIRT_EXTKBD,
{ /* Memory-mapped extra keyboard row */
.virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* and CS8900A Ethernet chip */
.virtual = EP7211_VIRT_CS8900A,
}, { /* CS8900A Ethernet chip */
.virtual = IO_ADDRESS(EP7211_PHYS_CS8900A),
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE,
}, { /* flash banks */
.virtual = EP7211_VIRT_FLASH1,
}, { /* Flash bank 0 */
.virtual = IO_ADDRESS(EP7211_PHYS_FLASH1),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
.length = SZ_8M,
.type = MT_DEVICE,
}, {
.virtual = EP7211_VIRT_FLASH2,
}, { /* Flash bank 1 */
.virtual = IO_ADDRESS(EP7211_PHYS_FLASH2),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
.length = SZ_8M,
.type = MT_DEVICE,

14
arch/arm/mach-clps711x/include/mach/autcpu12.h
View File

@ -20,12 +20,8 @@
#ifndef __ASM_ARCH_AUTCPU12_H
#define __ASM_ARCH_AUTCPU12_H
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*/
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE
/*
* The flash bank is wired to chip select 0
@ -34,11 +30,9 @@
/* offset for device specific information structure */
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
/*
* Videomemory is the internal SRAM (CS 6)
*/
/* Videomemory in the internal SRAM (CS 6) */
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
#define AUTCPU12_VIRT_VIDEO (0xfd000000)
/*
* All special IO's are tied to CS1

54
arch/arm/mach-clps711x/include/mach/hardware.h
View File

@ -24,7 +24,10 @@
#include <mach/clps711x.h>
#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
(((x) >> 2) & 0x3c000000)))
#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
#ifndef __ASSEMBLY__
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
@ -61,58 +64,25 @@
#define CS7_PHYS_BASE (0x00000000)
#endif
#define SYSPLD_VIRT_BASE 0xfe000000
#define SYSPLD_BASE SYSPLD_VIRT_BASE
#if defined (CONFIG_ARCH_CDB89712)
#define ETHER_START 0x20000000
#define ETHER_PHYS_BASE CS2_PHYS_BASE
#define ETHER_SIZE 0x1000
#define ETHER_BASE 0xfe000000
#endif
#if defined (CONFIG_ARCH_EDB7211)
/*
* The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
* and repeat across it. This is the mapping for it.
*
* In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE
/*
* The CS8900A ethernet chip has its I/O registers wired to chip select 2
* (nCS2). This is the mapping for it.
*
* In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
* was cause for much consternation and headscratching. This should probably
* be made a compile/run time kernel option.
*/
#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.
*
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
* in jumpered boot mode.
*/
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
/* The two flash banks are wired to chip selects 0 and 1 */
#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE
#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE
#endif /* CONFIG_ARCH_EDB7211 */

9
arch/arm/mach-clps711x/include/mach/syspld.h
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@ -23,14 +23,9 @@
#define __ASM_ARCH_SYSPLD_H
#define SYSPLD_PHYS_BASE (0x10000000)
#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
#ifndef __ASSEMBLY__
#include <asm/types.h>
#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
#else
#define SYSPLD_REG(type,off) (off)
#endif
#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
#define PLD_INT SYSPLD_REG(u32, 0x000000)
#define PLD_INT_PENIRQ (1 << 5)

14
arch/arm/mach-clps711x/p720t.c
View File

@ -40,21 +40,15 @@
/*
* Map the P720T system PLD. It occupies two address spaces:
* SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
* We map both here.
* 0x10000000 and 0x10400000. We map both regions as one.
*/
static struct map_desc p720t_io_desc[] __initdata = {
{
.virtual = SYSPLD_VIRT_BASE,
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
.length = SZ_1M,
.type = MT_DEVICE
}, {
.virtual = 0xfe400000,
.pfn = __phys_to_pfn(0x10400000),
.length = SZ_1M,
.type = MT_DEVICE
}
.length = SZ_8M,
.type = MT_DEVICE,
},
};
static void __init