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perf/x86: Move perf_event_intel_uncore.[ch] .. => x86/events/intel/uncore.[ch]
Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1455098123-11740-10-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -8,3 +8,4 @@ endif
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obj-$(CONFIG_CPU_SUP_INTEL) += intel/core.o intel/bts.o intel/cqm.o
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obj-$(CONFIG_CPU_SUP_INTEL) += intel/cstate.o intel/ds.o intel/lbr.o
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obj-$(CONFIG_CPU_SUP_INTEL) += intel/pt.o intel/rapl.o
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obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += intel/uncore.o
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@ -1,4 +1,4 @@
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#include "perf_event_intel_uncore.h"
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#include "uncore.h"
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static struct intel_uncore_type *empty_uncore[] = { NULL, };
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struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
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@ -2,7 +2,7 @@
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/perf_event.h>
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#include "perf_event.h"
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#include "../../kernel/cpu/perf_event.h"
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#define UNCORE_PMU_NAME_LEN 32
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#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
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@ -33,8 +33,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
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ifdef CONFIG_PERF_EVENTS
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o
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obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += perf_event_intel_uncore.o \
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perf_event_intel_uncore_snb.o \
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obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += perf_event_intel_uncore_snb.o \
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perf_event_intel_uncore_snbep.o \
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perf_event_intel_uncore_nhmex.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_msr.o
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@ -1,5 +1,5 @@
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/* Nehalem-EX/Westmere-EX uncore support */
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#include "perf_event_intel_uncore.h"
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#include "../../events/intel/uncore.h"
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/* NHM-EX event control */
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#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
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@ -1,5 +1,5 @@
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/* Nehalem/SandBridge/Haswell uncore support */
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#include "perf_event_intel_uncore.h"
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#include "../../events/intel/uncore.h"
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/* Uncore IMC PCI IDs */
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#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
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@ -1,6 +1,5 @@
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/* SandyBridge-EP/IvyTown uncore support */
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#include "perf_event_intel_uncore.h"
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#include "../../events/intel/uncore.h"
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/* SNB-EP Box level control */
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#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
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